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| v850e/ma1 32-bit single-chip microcontroller hardware user?s manual pd703103a pd703105a pd703106a pd703106a(a) pd703107a pd703107a(a) pd70f3107a pd70f3107a(a) printed in japan document no. u14359ej5v1ud00 (5th edition) date published april 2004 n cp(k) ?
user?s manual u14359ej5v1ud 2 [memo] user?s manual u14359ej5v1ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices user?s manual u14359ej5v1ud 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of january, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": user?s manual u14359ej5v1ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: user?s manual u14359ej5v1ud 6 introduction readers this manual is intended for users who wish to understand the functions of the v850e/ma1 to design application systems using the v850e/ma1. the target products are as follows: ? standard models: pd703103a, 703105a, 703106a, 703107a, and 70f3107a ? special models: pd703106a(a) note , 703107a(a) note , and 70f3107a(a) note under development purpose the purpose of this manual is for us ers to gain an understanding of the hardware functions of the v850e/ma1. organization the v850e/ma1 user?s manual is divided into two parts: hardware (this manual) and architecture (v850e1 user?s manual architecture) . the organization of each manual is as follows: hardware architecture ? pin functions ? data type ? cpu function ? register set ? internal peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. cautions 1. application examples in this manual are intended for the ?standard? quality models for general-purpose electronic systems. when using an example in this manual for an application that requires the ?special? quality grad e, evaluate each component and circuit to be actually used to see if they satisfy the required quality standard. 2. to use this manual for the pr oducts of special grade, take it as follows: pd703106a pd703106a(a) pd703107a pd703107a(a) pd70f3107a pd70f3107a(a) ? to find the details of a regi ster where the name is known refer to appendix c register index . ? to understand the details of an instruction function refer to the v850e1 architecture user?s manual . user?s manual u14359ej5v1ud 7 ? to know the electrical spec ifications of the v850e/ma1 refer to the chapter 17 electrical specifications. ? to understand the overall f unctions of the v850e/ma1 read this manual according to the contents . ? how to interpret the register format for a bit whose bit number is enclosed in brackets, its bit name is defined as a reserved word in the device file. the mark shows major revised points . conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresse s on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 data type: word ... 32 bits halfword ... 16 bits byte ... 8 bits user?s manual u14359ej5v1ud 8 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. document related to v850e/ma1 document name document no. v850e1 architecture user?s manual u14559e v850e/ma1 hardware user?s manual this manual v850e/ma1 hardware application note u15179e v850 series flash memory self-progr amming library user?s manual u16573e document related to developm ent tools (user?s manuals) document name document no. ie-v850e-mc, ie-v850e-mc-a (i n-circuit emulator) u14487e ie-703107-mc-em1 (in-circuit em ulator option board) u14481e operation u16053e c language u16054e ca850 ver. 2.50 c compiler package assembly language u16042e pm plus ver. 5.10 u16569e id850 ver. 2.50 integrated debugger operation u16217e sm850 ver. 2.40 system simulator operation u15182e sm850 ver. 2.00 or later system simulato r external part user open interface specification u14873e basics u13430e installation u13410e rx850 ver. 3.13 or later real-time os technical u13431e basics u13773e installation u13774e rx850 pro ver. 3.15 real-time os technical u13772e rd850 ver. 3.01 task debugger u13737e rd850 pro ver. 3.01 task debugger u13916e az850 ver. 3.10 system performance analyzer u14410e pg-fp4 flash memory programmer u15260e user?s manual u14359ej5v1ud 9 contents chapter 1 introduction ...................................................................................................... .........18 1.1 outline........................................................................................................................ ...............................18 1.2 featur es ....................................................................................................................... .............................19 1.3 applications ................................................................................................................... ..........................21 1.4 ordering info rmation ........................................................................................................... ....................21 1.5 pin configuration .............................................................................................................. .......................22 1.6 function blocks ................................................................................................................ .......................26 1.6.1 internal bl ock di agram ......................................................................................................... .........26 1.6.2 on-chip units.................................................................................................................. ..............27 1.7 differences am ong products..................................................................................................... .............29 chapter 2 pin functions ..................................................................................................... ..........30 2.1 list of pin functions.......................................................................................................... ......................30 2.2 pin status ..................................................................................................................... ............................37 2.3 description of pin functions ................................................................................................... ...............38 2.4 pin i/o circuits and recommende d connection of unused pins........................................................53 2.5 pin i/o circuits ............................................................................................................... ..........................55 chapter 3 cpu function...................................................................................................... ..........56 3.1 featur es ....................................................................................................................... .............................56 3.2 cpu regist er set............................................................................................................... .......................57 3.2.1 program regi ster set ........................................................................................................... .........58 3.2.2 system regi ster set ............................................................................................................ ..........59 3.3 operating modes................................................................................................................ ......................62 3.3.1 operating modes ................................................................................................................ .........62 3.3.2 operating mode specific ation................................................................................................... ....63 3.4 address sp ace .................................................................................................................. .......................64 3.4.1 cpu addre ss space .............................................................................................................. .......64 3.4.2 image .......................................................................................................................... .................65 3.4.3 wrap-around of cpu address s pace ...........................................................................................66 3.4.4 memory map ..................................................................................................................... ...........67 3.4.5 area ........................................................................................................................... ..................69 3.4.6 external memo ry expans ion...................................................................................................... ...74 3.4.7 recommended use of address s pace..........................................................................................75 3.4.8 peripheral i/o regist ers ....................................................................................................... .........77 3.4.9 specific re gisters............................................................................................................. .............86 3.4.10 system wait control register (vswc)...........................................................................................8 6 3.4.11 cautio ns....................................................................................................................... ................86 chapter 4 bus control function.............................................................................................8 7 4.1 featur es ....................................................................................................................... .............................87 4.2 bus contro l pins ............................................................................................................... .......................88 4.2.1 pin status during internal rom, internal ram, and on-chip per ipheral i/o access ......................88 user?s manual u14359ej5v1ud 10 4.3 memory bloc k function.......................................................................................................... .................89 4.3.1 chip select co ntrol f unction ................................................................................................... .......90 4.4 bus cycle type c ontrol function................................................................................................ ...........93 4.5 bus ac cess ..................................................................................................................... ..........................95 4.5.1 number of ac cess cl ocks ........................................................................................................ .....95 4.5.2 bus sizing functi on ............................................................................................................ ...........96 4.5.3 endian contro l func tion........................................................................................................ .........97 4.5.4 big endian method usage restrictions in nec electronics dev elopment t ools ..............................98 4.5.5 bus wid th...................................................................................................................... ..............100 4.6 wait function.................................................................................................................. ........................111 4.6.1 programmable wa it func tion..................................................................................................... ..111 4.6.2 external wait function ......................................................................................................... ........116 4.6.3 relationship between programmable wait a nd external wait......................................................116 4.6.4 bus cycles in which wait function is valid ...................................................................................11 7 4.7 idle state inser tion function .................................................................................................. ...............118 4.8 bus hold function .............................................................................................................. ...................119 4.8.1 function ov erview .............................................................................................................. ........119 4.8.2 bus hold pr ocedure ............................................................................................................. .......120 4.8.3 operation in po wer-save mode ..................................................................................................1 20 4.8.4 bus hold timi ng (sram) ......................................................................................................... ....121 4.8.5 bus hold timing (edo dram) ....................................................................................................1 23 4.8.6 bus hold timi ng (s dram) ........................................................................................................ ..127 4.9 bus priority order ............................................................................................................. .....................131 4.10 boundary operat ion conditions .................................................................................................. .........131 4.10.1 program space.................................................................................................................. .........131 4.10.2 data s pace ..................................................................................................................... ............131 chapter 5 memory access control function ................................................................. 132 5.1 sram, external rom, ex ternal i/o interface..................................................................................... ...132 5.1.1 featur es ....................................................................................................................... ..............132 5.1.2 sram conn ecti on ................................................................................................................ ......133 5.1.3 sram, external rom, external i/o access ................................................................................135 5.2 page rom cont roller (r omc) ..................................................................................................... ..........141 5.2.1 featur es ....................................................................................................................... ..............141 5.2.2 page rom co nnecti on ............................................................................................................ ...142 5.2.3 on-page/off-pa ge judgm ent ...................................................................................................... .143 5.2.4 page rom configurati on register (prc) ....................................................................................145 5.2.5 page rom access ................................................................................................................ .....146 5.3 dram controller (edo dram)..................................................................................................... .........150 5.3.1 featur es ....................................................................................................................... ..............150 5.3.2 dram conn ection ................................................................................................................ ......151 5.3.3 address multip lex func tion ..................................................................................................... ....152 5.3.4 dram configuration registers 1, 3, 4, 6 (s cr1, scr3, scr4 , scr6 ) ......................................153 5.3.5 dram a ccess .................................................................................................................... ........156 5.3.6 refresh contro l func tion ....................................................................................................... ......161 user?s manual u14359ej5v1ud 11 5.3.7 self-refresh cont rol function .................................................................................................. .....166 5.4 dram controlle r (sdram )........................................................................................................ ............168 5.4.1 featur es....................................................................................................................... ..............168 5.4.2 sdram con nection............................................................................................................... .....168 5.4.3 address multip lex func tion ..................................................................................................... ....169 5.4.4 sdram configuration regist ers 1, 3, 4, 6 (scr1, scr3, scr4 , scr6 ) ...................................174 5.4.5 sdram a ccess................................................................................................................... .......176 5.4.6 refresh contro l func tion ....................................................................................................... ......190 5.4.7 self-refresh cont rol function .................................................................................................. .....195 5.4.8 sdram initializa tion sequence .................................................................................................. 197 chapter 6 dma functions (dma controller) .....................................................................200 6.1 featur es ....................................................................................................................... ...........................200 6.2 configuration .................................................................................................................. .......................201 6.3 control re gisters .............................................................................................................. .....................202 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3 )..............................................................202 6.3.2 dma destination address register s 0 to 3 (dda 0 to dda 3) ....................................................... 204 6.3.3 dma byte count registers 0 to 3 (dbc0 to dbc3 ) .....................................................................206 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc 3).................................................... 207 6.3.5 dma channel control register s 0 to 3 (dchc 0 to dchc3 ) ........................................................209 6.3.6 dma disable status register (ddis) ...........................................................................................21 1 6.3.7 dma restart regi ster (drst).................................................................................................... ..211 6.3.8 dma terminal count output c ontrol register (dtoc) ..................................................................212 6.3.9 dma trigger factor registers 0 to 3 (dtfr0 to dtfr 3).............................................................. 213 6.4 dma bus states ................................................................................................................. ....................216 6.4.1 types of bus states............................................................................................................ ........216 6.4.2 dmac bus cycle st ate trans ition ................................................................................................ 218 6.5 transfer modes ................................................................................................................. .....................219 6.5.1 single trans fer m ode........................................................................................................... .......219 6.5.2 single-step tran sfer mode ...................................................................................................... ....221 6.5.3 block trans fer m ode ............................................................................................................ .......222 6.6 transfer types ................................................................................................................. ......................223 6.6.1 2-cycle tr ansfer ............................................................................................................... ...........223 6.6.2 flyby tr ansfer ................................................................................................................. ............239 6.7 transfer target s............................................................................................................... ......................250 6.7.1 transfer type and tr ansfer ta rgets............................................................................................. .250 6.7.2 external bus cycles dur ing dma tr ansfer ...................................................................................251 6.8 dma channel priori ties ......................................................................................................... ................251 6.9 next address se tting function.................................................................................................. ...........252 6.10 dma transfer st art fact ors ..................................................................................................... .............254 6.11 terminal count output upon dma transf er en d ................................................................................256 6.12 forcible su spensi on............................................................................................................ ..................257 6.13 forcible te rmination........................................................................................................... ...................258 6.13.1 restriction related to dma tr ansfer forcible terminatio n .............................................................259 6.14 times related to dma tr ansfer .................................................................................................. ..........261 user?s manual u14359ej5v1ud 12 6.15 response time for dm a transfer request......................................................................................... .261 6.15.1 example of respons e time for dm a request.............................................................................. .261 6.15.2 maximum response time fo r dma transfe r reques t ....................................................................263 6.16 cautions....................................................................................................................... ...........................264 6.16.1 suspen sion factors.................................................................................................... .................265 6.17 dma transf er end ............................................................................................................... ...................265 chapter 7 interrupt/exception processing function............................................... 266 7.1 featur es ....................................................................................................................... ...........................266 7.2 non-maskable interrupts ........................................................................................................ ...............269 7.2.1 operation ...................................................................................................................... .............270 7.2.2 restore........................................................................................................................ ...............272 7.2.3 non-maskable interrupt status fl ag (np) ....................................................................................273 7.2.4 noise elim ination .............................................................................................................. ..........273 7.2.5 edge detecti on func tion........................................................................................................ ......273 7.3 maskable in terrupts ............................................................................................................ ...................274 7.3.1 operation ...................................................................................................................... .............274 7.3.2 restore........................................................................................................................ ...............276 7.3.3 priorities of ma skable inte rrupts .............................................................................................. ...277 7.3.4 interrupt control r egister ( xxicn)............................................................................................. ....281 7.3.5 interrupt mask registers 0 to 3 (imr0 to imr3 ) ..........................................................................284 7.3.6 in-service priority register (ispr) ............................................................................................ ...285 7.3.7 maskable interrupt st atus flag (id) ............................................................................................ .286 7.3.8 noise elim ination .............................................................................................................. ..........287 7.3.9 interrupt trigger mode sele ction............................................................................................... ...287 7.4 software ex ception ............................................................................................................. ...................291 7.4.1 operation ...................................................................................................................... .............291 7.4.2 restore........................................................................................................................ ...............292 7.4.3 exception stat us flag (ep) ..................................................................................................... .....293 7.5 exception trap ................................................................................................................. ......................294 7.5.1 illegal opcode definit ion...................................................................................................... ........294 7.5.2 debug trap ..................................................................................................................... ............296 7.6 multiple interrupt servicing control ........................................................................................... ..........298 7.7 interrupt la tency time......................................................................................................... ..................300 7.8 periods in which interrupt s are not ackn owledge d ..........................................................................301 chapter 8 prescaler unit (prs)............................................................................................ 302 chapter 9 clock generation function............................................................................. 303 9.1 featur es ....................................................................................................................... ...........................303 9.2 configuration.................................................................................................................. ........................303 9.3 input clock selection.......................................................................................................... ...................304 9.3.1 direct mode.................................................................................................................... ............304 9.3.2 pll mode....................................................................................................................... ............305 9.3.3 peripheral command re gister (p hcmd) .....................................................................................305 user?s manual u14359ej5v1ud 13 9.3.4 clock control regi ster (ckc) ................................................................................................... ...306 9.3.5 peripheral status register (phs) ............................................................................................... .308 9.4 pll lockup ..................................................................................................................... .......................309 9.5 power-save control ............................................................................................................. ..................310 9.5.1 overvi ew ....................................................................................................................... .............310 9.5.2 control re gisters.............................................................................................................. ...........312 9.5.3 halt mode...................................................................................................................... ..........315 9.5.4 idle mode ...................................................................................................................... ...........317 9.5.5 software st op m ode ............................................................................................................. ...320 9.6 securing oscillation stabilization time ........................................................................................ .......323 9.6.1 oscillation stabilization time security spec ificatio n .....................................................................323 9.6.2 time base coun ter (tbc)........................................................................................................ ...325 chapter 10 timer/counter function (real-time pulse unit) ...................................326 10.1 timer c........................................................................................................................ ............................326 10.1.1 features (t imer c)............................................................................................................. .........326 10.1.2 function overview (timer c) .................................................................................................... ...326 10.1.3 basic configurati on of ti mer c ................................................................................................. ...327 10.1.4 timer c ........................................................................................................................ ..............328 10.1.5 timer c contro l regist ers...................................................................................................... ......332 10.1.6 timer c oper atio n .............................................................................................................. ........337 10.1.7 application exampl es (timer c) ................................................................................................. .344 10.1.8 cautions (t imer c)............................................................................................................. .........351 10.2 timer d........................................................................................................................ ............................352 10.2.1 features (t imer d)............................................................................................................. .........352 10.2.2 function overview (timer d) .................................................................................................... ...352 10.2.3 basic configurati on of ti mer d ................................................................................................. ...352 10.2.4 timer d ........................................................................................................................ ..............353 10.2.5 timer d contro l regist ers...................................................................................................... ......356 10.2.6 timer d oper atio n .............................................................................................................. ........358 10.2.7 application exampl es (timer d) ................................................................................................. .360 10.2.8 cautions (t imer d)............................................................................................................. .........360 chapter 11 serial interface function ..............................................................................361 11.1 featur es ....................................................................................................................... ...........................361 11.1.1 switching between uart and csi modes .................................................................................361 11.2 asynchronous serial interface s 0 to 2 (uart 0 to uart 2) ................................................................362 11.2.1 featur es....................................................................................................................... ..............362 11.2.2 configur ation.................................................................................................................. ............363 11.2.3 control re gisters.............................................................................................................. ...........365 11.2.4 interrupt requests............................................................................................................. ..........373 11.2.5 operation ...................................................................................................................... .............374 11.2.6 dedicated baud rate generator s 0 to 2 (brg0 to brg2 )...........................................................386 11.2.7 cautio ns....................................................................................................................... ..............393 11.3 clocked serial interfaces 0 to 2 (csi0 to csi2) ................................................................................ ...394 user?s manual u14359ej5v1ud 14 11.3.1 featur es ....................................................................................................................... ..............394 11.3.2 configur ation.................................................................................................................. ............394 11.3.3 control re gisters.............................................................................................................. ...........396 11.3.4 operation ...................................................................................................................... .............403 11.3.5 output pins .................................................................................................................... .............406 11.3.6 system configur ation example ................................................................................................... 407 chapter 12 a/d converter .................................................................................................... .... 408 12.1 featur es ....................................................................................................................... ...........................408 12.2 configuration.................................................................................................................. ........................408 12.3 control re gisters .............................................................................................................. .....................411 12.4 a/d converter operation ........................................................................................................ ...............418 12.4.1 basic operation of a/d conv erter............................................................................................... .418 12.4.2 operation mode and trigger mode .............................................................................................419 12.5 operation in a/ d trigger mode .................................................................................................. ...........424 12.5.1 select mode operation .......................................................................................................... .....424 12.5.2 scan mode op eratio ns ........................................................................................................... ....426 12.6 operation in time r trigger mode................................................................................................ ..........427 12.6.1 select mode operation .......................................................................................................... .....428 12.6.2 scan mode op eration ............................................................................................................ .....432 12.7 operation in extern al trigger mode ............................................................................................. ........436 12.7.1 select mode operations (e xternal trigge r select ) ........................................................................436 12.7.2 scan mode operation (ext ernal trigge r scan) .............................................................................438 12.8 notes on op eration ............................................................................................................. ...................440 12.8.1 stopping conversi on operat ion.................................................................................................. .440 12.8.2 timer trigger/external trigger interval........................................................................................ ..440 12.8.3 operation in standby mode ...................................................................................................... ..440 12.8.4 compare match interrupt in timer tri gger mo de.......................................................................... 441 12.8.5 reconversion operation in timer 1 tri gger m ode......................................................................... 442 12.8.6 supplementary information on a/d conversi on time ..................................................................443 12.9 how to read a/d converter? s characteristi c tabl e ............................................................................445 chapter 13 pwm unit .......................................................................................................... ........... 449 13.1 featur es ....................................................................................................................... ...........................449 13.2 block di agram .................................................................................................................. ......................449 13.3 control re gister ............................................................................................................... ......................450 13.4 operation ...................................................................................................................... ..........................452 13.4.1 basic oper ations............................................................................................................... ..........452 13.4.2 repetition frequenc y ........................................................................................................... .......455 13.5 cautions....................................................................................................................... ...........................455 chapter 14 port functions .................................................................................................. ... 456 14.1 featur es ....................................................................................................................... ...........................456 14.2 port config uration............................................................................................................. .....................457 14.3 port pin functions ............................................................................................................. ....................474 user?s manual u14359ej5v1ud 15 14.3.1 port 0 ......................................................................................................................... ................474 14.3.2 port 1 ......................................................................................................................... ................477 14.3.3 port 2 ......................................................................................................................... ................479 14.3.4 port 3 ......................................................................................................................... ................483 14.3.5 port 4 ......................................................................................................................... ................486 14.3.6 port 5 ......................................................................................................................... ................489 14.3.7 port 7 ......................................................................................................................... ................491 14.3.8 port al ........................................................................................................................ ...............492 14.3.9 port ah ........................................................................................................................ ..............494 14.3.10 port dl........................................................................................................................ ...............496 14.3.11 port cs ........................................................................................................................ ..............498 14.3.12 port ct ........................................................................................................................ ..............502 14.3.13 port cm........................................................................................................................ ..............504 14.3.14 port cd ........................................................................................................................ ..............507 14.3.15 port bd ........................................................................................................................ ..............510 14.4 setting to use alternate function of port pin .................................................................................. ...511 14.5 operation of port function ..................................................................................................... ..............520 14.5.1 writing data to i/o port....................................................................................................... ........520 14.5.2 reading data fr om i/o port..................................................................................................... ....520 14.5.3 output status of alternate function in co ntrol m ode.................................................................... 520 14.6 cautions.................................................................................................................. ................................521 chapter 15 reset functions................................................................................................. ...522 15.1 featur es ....................................................................................................................... ...........................522 15.2 pin functions .................................................................................................................. .......................522 15.3 initialization ................................................................................................................. ...........................524 chapter 16 flash memory ( pd70f3107a) ...........................................................................527 16.1 featur es ....................................................................................................................... ...........................527 16.2 writing with flash programmer .................................................................................................. ..........527 16.3 programming en vironm ent........................................................................................................ ...........532 16.4 communicati on mode............................................................................................................. ...............532 16.5 pin connection................................................................................................................. ......................533 16.5.1 mode2/v pp pin..........................................................................................................................5 33 16.5.2 serial inte rface pin ........................................................................................................... ..........533 16.5.3 reset pin ...................................................................................................................... ...........535 16.5.4 nmi pin ........................................................................................................................ ..............535 16.5.5 mode0 to mo de2 pi ns ............................................................................................................ .535 16.5.6 port pins...................................................................................................................... ...............535 16.5.7 other signa l pi ns .............................................................................................................. ..........535 16.5.8 power su pply ................................................................................................................... ..........535 16.6 programming method ............................................................................................................. ...............536 16.6.1 flash memory cont rol ........................................................................................................... .....536 16.6.2 flash memory pr ogramming mode ............................................................................................537 16.6.3 selection of comm unication mode .............................................................................................537 user?s manual u14359ej5v1ud 16 16.6.4 communication command s........................................................................................................5 38 16.7 flash memory programming by self-pr ogrammi ng............................................................................539 16.7.1 outline of self -programming .................................................................................................... ...539 16.7.2 self-programmi ng func tion ...................................................................................................... ...540 16.7.3 outline of self-progr amming inte rface ........................................................................................54 0 16.7.4 hardware en vironment ........................................................................................................... ....541 16.7.5 software env ironment ........................................................................................................... .....543 16.7.6 self-programming function number ............................................................................................544 16.7.7 calling pa rameters ............................................................................................................. ........545 16.7.8 contents of ra m paramet ers..................................................................................................... 546 16.7.9 errors during se lf-programming................................................................................................. .547 16.7.10 flash info rmation.............................................................................................................. ..........547 16.7.11 area num ber .................................................................................................................... ..........548 16.7.12 flash programming mode cont rol register (flpmc ) ..................................................................549 16.7.13 calling device inte rnal proc essing ............................................................................................. .551 16.7.14 erasing flash memory flow ...................................................................................................... ...554 16.7.15 successive wr iting flow ........................................................................................................ ......555 16.7.16 internal ve rify flow ........................................................................................................... ...........556 16.7.17 acquiring flash in formation flow............................................................................................... ...557 16.7.18 self-programmi ng libr ary ....................................................................................................... .....558 16.8 how to distinguish flash memo ry and mask ro m versi ons .............................................................560 chapter 17 electrical specifications ............................................................................... 561 17.1 normal operat ion mode.......................................................................................................... ...............561 17.2 flash memory programming mode ( pd70f3107a and 70f310 7a(a) on ly).....................................617 chapter 18 package drawings .............................................................................................. 62 0 chapter 19 recommended soldering conditions......................................................... 622 appendix a notes on target system design ................................................................. 624 appendix b cautions ......................................................................................................... ........... 627 b.1 restriction on pa ge rom access................................................................................................. ........627 b.1.1 descrip tion .................................................................................................................... .............627 b.1.2 counterm easur es................................................................................................................ .......628 b.2 restriction on conflict between sld instruction and interrupt request ............................................629 b.2.1 de scripti on ............................................................................................................ .....................629 b.2.2 count ermeas ure ......................................................................................................... ...............629 appendix c register index .................................................................................................. ..... 630 appendix d instruction set list ........................................................................................... 638 d.1 conventions.................................................................................................................... ........................638 d.2 instruction set (in alphabetical order)........................................................................................ .........641 user?s manual u14359ej5v1ud 17 appendix e revision history ................................................................................................. ....648 e.1 major revisions in this edition .......................................................................................... ..................648 e.2 revision history up to preceding edition................................................................................. ...........650 user?s manual u14359ej5v1ud 18 chapter 1 introduction the v850e/ma1 is a product of nec electronics? single-c hip microcontroller ?v850 series?. this chapter gives a simple outline of the v850e/ma1. 1.1 outline the v850e/ma1 is a 32-bit single-chip microcontroller that integrates the v850e1 cp u, which is a 32-bit risc- type cpu core for asic, newly developed as the cpu core central to system lsi for the current age of system-on- chip. this device incorporates rom, ram, and various peripheral functions such as memory controllers, a dma controller, real-time pulse unit, serial interfaces, and an a/d converter for realizing high-capacity data processing and sophisticated real-time control. (1) v850e1 cpu the v850e1 cpu is a cpu core that enhances the external bus interf ace performance of the v850 cpu, which is the cpu core integrated in the v850 series , and has added instructions supporting high-level languages, such as c-language switch statement processing, table lookup branching, stack frame creation/deletion, and data conversion. this enhances the performance of both data processing and control. it is possible to use the software resources of the v850 cpu integrated system since the instruction codes of the v850e1 are upwardly compatible at the obj ect code level with those of the v850 cpu. (2) external memory interface function the v850e/ma1 features various on-chip external memory interfaces including separately configured address (26 bits) and data (16 bits) buses, and sdram and rom interfaces, as well as on-chip memory controllers that can be directly linked to edo dram, page rom, etc., thereby ra ising system performance and reducing the number of part s needed for application systems. also, through the dma controller, cpu internal ca lculations and data transfers can be performed simultaneously with transfers to and from the external memory, so it is possible to process large volumes of image data or voice data, etc., and through high-speed execution of instructions using internal rom and ram, motor control, communications control and other r eal-time control tasks can be realized simultaneously. (3) on-chip flash memory ( pd70f3107a) the on-chip flash memory version ( pd70f3107a) has on-chip flash memory, which is capable of high- speed access, and since it is possible to rewrite a program with the v850e/ma1 mounted as is in the application system, system development time can be reduced and system maintainability after shipping can be markedly improved. (4) a full range of middleware and development environment products the v850e/ma1 can execute middleware such as j peg, jbig, and mh/mr/mmr at high speed. also, middleware that enables speech recognition, voice synthes is, and other such processing is available, and by including these middleware programs, a mu ltimedia system can be easily realized. a development environment system that includes an optimized c compiler, debugger, in-circuit emulator, simulator, system performance analyzer, an d other elements is also available. chapter 1 introduction user?s manual u14359ej5v1ud 19 1.2 features { number of instructions: 83 { minimum instruction execution time: 20 ns (at internal 50 mhz operation) { general-purpose registers: 32 bits 32 { instruction set: v850e1 cpu signed multiplication (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits): 1 to 2 clocks saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock bit manipulation instructions load/store instructions with long/short format signed load instructions { memory space: 256 mb linear addre ss space (common program/data use) chip select output function: 8 spaces memory block division function: 2, 4, 8 mb/block programmable wait function idle state insertion function { external bus interface: 16-bit data bus (address/data separated) 16-/8-bit bus sizing function bus hold function external wait function address setup wait function endian control function part number internal rom internal ram pd703103a none 4 kb pd703105a 128 kb (mask rom) 4 kb pd703106a 128 kb (mask rom) 10 kb pd703107a 256 kb (mask rom) 10 kb { internal memory pd70f3107a 256 kb (flash memory) 10 kb { interrupts/exceptions: external interrupts: 25 (including nmi) internal interrupts: 33 sources exceptions: 1 source eight levels of priorities can be set. { memory access controller dram controller (compatible with edo dram and sdram) page rom controller chapter 1 introduction user?s manual u14359ej5v1ud 20 { dma controller: 4 channels transfer unit: 8 bits/16 bits maximum transfer count: 65,536 (2 16 ) transfer type: flyby (1-cycle)/2-cycle transfer mode: single/single step/block transfer target: memory ? memory, memory ? i/o transfer request: external request/on-chip peripheral i/o/software dma transfer terminate (terminal count) output signal next address setting function { i/o lines: input ports: 9 i/o ports: 106 { real-time pulse unit: 16-bit timer/event counter: 4 channels 16-bit timers: 4 16-bit capture/compare registers: 8 16-bit interval timer: 4 channels { serial interfaces (sio): asynchronous serial interface (uart) clocked serial interface (csi) csi/uart: 2 channels uart: 1 channel csi: 1 channel { a/d converter: 10-bit resolution a/d converter: 8 channels { pwm (pulse width modulation): 8-/9-/10-/12-bit resolution pwm: 2 channels { clock generator: a 10 function through a pll clock synthesizer. divide-by-two function through an external clock input. { power-save function: halt/idle/software stop mode { package: 144-pin plastic lqfp (fine pitch) (20 20) 161-pin plastic fbga (13 13) { cmos technology: all static circuits chapter 1 introduction user?s manual u14359ej5v1ud 21 1.3 applications ink-jet printers, facsimiles, digital still cameras, dvd players, video printers, ppc, information equipment, etc. 1.4 ordering information part number package quality grade pd703103agj-uen 144-pin plasti c lqfp (fine pitch) (20 20) standard (for general-pur pose electronic systems) pd703105agj- -uen 144-pin plastic lq fp (fine pitch) (20 20) standard (for general-pur pose electronic systems) pd703106agj- -uen 144-pin plastic lq fp (fine pitch) (20 20) standard (for general-pur pose electronic systems) pd703107agj- -uen 144-pin plastic lq fp (fine pitch) (20 20) standard (for general-pur pose electronic systems) pd70f3107agj-uen 144-pin plasti c lqfp (fine pitch) (20 20) standard (for general-pur pose electronic systems) pd703106af1- -en4 161-pin plastic fbga (13 13) standard (for general-pur pose electronic systems) pd703107af1- -en4 161-pin plastic fbga (13 13) standard (for general-pur pose electronic systems) pd70f3107af1-en4 161-pin plastic fbga (13 13) standard (for general-pur pose electronic systems) pd703106agj(a)- -uen note 144-pin plastic lqfp (fine pitch) (20 20) special (for high-reliability electronic systems) pd703107agj(a)- -uen note 144-pin plastic lqfp (fine pitch) (20 20) special (for high-reliability electronic systems) pd70f3107agj(a)-uen 144-pin plastic lqfp (fine pitch) (20 20) special (for high-reliability electronic systems) note under development remark indicates rom code suffix. the pd703106a, 703107a, and 70f3107a do not differ from the pd703106a(a), 703107a(a), and 70f3107a(a) except the quality grade. please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec electronics corporation to know the specification of qualit y grade on the devices and its recommended applications. chapter 1 introduction user?s manual u14359ej5v1ud 22 1.5 pin configuration ? 144-pin plastic lqfp (fine pitch) (20 20) pd703103agj-uen pd703106agj(a)- -uen pd703105agj- -uen pd703107agj(a)- -uen pd703106agj- -uen pd70f3107agj(a)-uen pd703107agj- -uen pd70f3107agj-uen top view d14/pdl14 d13/pdl13 d12/pdl12 d11/pdl11 d10/pdl10 d9/pdl9 d8/pdl8 v dd v ss d7/pdl7 d6/pdl6 d5/pdl5 d4/pdl4 d3/pdl3 d2/pdl2 d1/pdl1 d0/pdl0 mode2 (v pp /mode2) dmarq3/intp103/p07 dmarq2/intp102/p06 dmarq1/intp101/p05 dmarq0/intp100/p04 to00/p03 intp001/p02 ti000/intp000/p01 pwm0/p00 v dd v ss dmaak3/pbd3 dmaak2/pbd2 dmaak1/pbd1 dmaak0/pbd0 to01/p13 intp011/p12 ti010/intp010/p11 pwm1/p10 pcd3/ube/sdras pcs0/cs0 pcs1/cs1/ras1 pcs2/cs2/iowr pcs3/cs3/ras3 pcs4/cs4/ras4 pcs5/cs5/iord pcs6/cs6/ras6 pcs7/cs7 v ss v dd pct0/lcas/lwr/ldqm pct1/ucas/uwr/udqm pct4/rd pct5/we pct6/oe pct7/bcyst pcm0/wait pcm1/clkout/busclk pcm2/hldak pcm3/hldrq pcm4/refrq pcm5/selfref p50/intp030/ti030 p51/intp031 p52/to03 v ss v dd p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 v dd v ss tc3/intp113/p27 tc2/intp112/p26 tc1/intp111/p25 tc0/intp110/p24 to02/p23 intp021/p22 ti020/intp020/p21 nmi/p20 v dd v ss adtrg/intp123/p37 intp122/p36 intp121/p35 rxd2/intp120/p34 txd2/intp133/p33 sck2/intp132/p32 si2/intp131/p31 so2/intp130/p30 mode1 mode0 reset cksel cv dd x2 x1 cv ss sck1/p45 rxd1/si1/p44 txd1/so1/p43 sck0/p42 rxd0/si0/p41 txd0/so0/p40 av dd /av ref av ss pdl15/d15 pal0/a0 pal1/a1 pal2/a2 pal3/a3 pal4/a4 pal5/a5 pal6/a6 pal7/a7 v ss v dd pal8/a8 pal9/a9 pal10/a10 pal11/a11 pal12/a12 pal13/a13 pal14/a14 pal15/a15 v ss v dd pah0/a16 pah1/a17 pah2/a18 pah3/a19 pah4/a20 pah5/a21 pah6/a22 pah7/a23 pah8/a24 pah9/a25 v ss v dd pcd0/sdcke pcd1/sdclk pcd2/lbe/sdcas 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 remark items in parentheses are pin names in the pd70f3107a. chapter 1 introduction user?s manual u14359ej5v1ud 23 ? 161-pin plastic fbga (13 13) pd703106af1- -en4 pd703107af1- -en4 pd70f3107af1-en4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 top view bottom view pnmlk jhgfedcba abcdefghj klmnp index mark index mark (1/2) pin number pin name pin number pin name pin number pin name a1 ? b7 a13/pal13 c13 cs2/iowr/pcs2 a2 d15/pdl15 b8 v ss c14 ? a3 a2/pal2 b9 a18/pah2 d1 v ss a4 a5/pal5 b10 a21/pah5 d2 d10/pdl10 a5 ? b11 a25/pah9 d3 d14/pdl14 a6 a9/pal9 b12 sdclk/pcd1 d4 a3/pal3 a7 a12/pal12 b13 cs1/ras1/pcs1 d5 a6/pal6 a8 a15/pal15 b14 ? d6 a10/pal10 a9 a17/pah1 c1 ? d7 a14/pal14 a10 ? c2 d9/pdl9 d8 a16/pah0 a11 a24/pah8 c3 d13/pdl13 d9 a20/pah4 a12 v dd c4 a1/pal1 d10 a23/pah7 a13 lbe/sdcas/pcd2 c5 a7/pal7 d11 sdcke/pcd0 a14 ube/sdras/pcd3 c6 v dd d12 cs0/pcs0 b1 ? c7 a11/pal11 d13 cs5/iord/pcs5 b2 d12/pdl12 c8 v dd d14 ? b3 a0/pal0 c9 a19/pah3 e1 d5/pdl5 b4 a4/pal4 c10 a22/pah6 e2 d7/pdl7 b5 v ss c11 v ss e3 d8/pdl8 b6 a8/pal8 c12 cs3/ras3/pcs3 e4 d11/pdl11 chapter 1 introduction user?s manual u14359ej5v1ud 24 (2/2) pin number pin name pin number pin name pin number pin name e5 ? j12 ti030/intp030/p50 m10 sck1/p45 e11 cs6/ras6/pcs6 j13 selfref/pcm5 m11 txd0/so0/p40 e12 cs4/ras4/pcs4 j14 intp031/p51 m12 ani6/p76 e13 cs7/pcs7 k1 pwm0/p00 m13 ani5/p75 e14 v ss k2 v ss m14 ? f1 d2/pdl2 k3 dmaak1/pbd1 n1 ? f2 d3/pdl3 k4 dmaak3/pbd3 n2 pwm1/p10 f3 d4/pdl4 k11 ani1/p71 n3 tc3/intp113/p27 f4 v dd k12 ani0/p70 n4 tc0/intp110/p24 f11 rd/pct4 k13 v ss n5 nmi/p20 f12 v dd k14 v dd n6 adtrg/intp123/p37 f13 lcas/lwr/ldqm/pct0 l1 ? n7 txd2/intp133/p33 f14 ucas/uwr/udqm/pct1 l2 dmaak2/pbd2 n8 so2/intp130/p30 g1 mode2 (mode2/v pp ) l3 ti010/intp010/p11 n9 x2 g2 dmarq3/intp103/p07 l4 dmaak0/pbd0 n10 cv ss g3 d0/pdl0 l5 to02/p23 n11 sck0/p42 g4 d6/pdl6 l6 v dd n12 av dd /av ref g11 wait/pcm0 l7 intp122/p36 n13 av ss g12 we/pct5 l8 si2/intp131/p31 n14 ? g13 bcyst/pct7 l9 reset p1 v dd g14 oe/pct6 l10 txd1/so1/p43 p2 v ss h1 dmarq2/intp102/p06 l11 ani7/p77 p3 tc1/intp111/p25 h2 dmarq1/intp101/p05 l12 ani4/p74 p4 intp021/p22 h3 dmarq0/intp100/p04 l13 ani3/p73 p5 ? h4 d1/pdl1 l14 ani2/p72 p6 intp121/p35 h11 refrq/pcm4 m1 ? p7 sck2/intp132/p32 h12 hldrq/pcm3 m2 intp011/p12 p8 mode1 h13 hldak/pcm2 m3 to01/p13 p9 cv dd h14 clkout/busclk/pcm1 m4 tc2/intp112/p26 p10 x1 j1 to00/p03 m5 ti020/intp020/p21 p11 ? j2 ti000/intp000/p01 m6 v ss p12 rxd1/si1/p44 j3 v dd m7 rxd2/intp120/p34 p13 rxd0/si0/p41 j4 intp001/p02 m8 mode0 p14 ? j11 to03/p52 m9 cksel remarks 1. leave the a1, a5, a10, b1, b14, c1, c14, d14, e5, l1, m1, m14, n1, n14, p5, p11, and p14 pins open. 2. items in parentheses are pin names in the pd70f3107a. chapter 1 introduction user?s manual u14359ej5v1ud 25 pin identification a0 to a25: address bus p70 to p77: port 7 adtrg: a/d trigger input pah0 to pah9: port ah ani0 to ani7: analog input pal0 to pal15: port al av dd : analog power supply pbd0 to pbd3: port bd av ref : analog reference voltage pcd0 to pcd3: port cd av ss : analog ground pcm0 to pcm5: port cm bcyst: bus cycle start timing pcs0 to pcs7: port cs busclk: bus clock output pct0, pct1, : port ct cksel: clock generator operating mode select pct4 to pct7 clkout: clock output pdl0 to pdl15: port dl cs0 to cs7: chip select pwm0, pwm1: pulse width modulation cv dd : clock generator power supply ras1, ras3, : row address strobe cv ss : clock generator ground ras4, ras6 d0 to d15: data bus rd: read strobe dmaak0 to dmaak3: dma acknowledge refrq: refresh request dmarq0 to dmarq3: dma request reset: reset hldak: hold acknowledge rxd0 to rxd2: receive data hldrq: hold request sck0 to sck2: serial clock intp000, intp001, : external interrupt input sdcas: sdram column address strobe intp010, intp011, sdcke: sdram clock enable intp020, intp021, sdclk: sdram clock output intp030, intp031, sdras: sdram row address strobe intp100 to intp103, selfref: self-refresh request intp110 to intp113, si0 to si2: serial input intp120 to intp123, so0 to so2: serial output intp130 to intp133 tc0 to tc3: terminal count signal iord: i/o read strobe ti000, ti010, : timer input iowr: i/o write strobe ti020, ti030 lbe: lower byte enable to00 to to03: timer output lcas: lower column address strobe txd0 to txd2: transmit data ldqm: lower dq mask enable ube: upper byte enable lwr: lower write strobe ucas: upper column address strobe mode0 to mode2: mode udqm: upper dq mask enable nmi: non-maskable interrupt request uwr: upper write strobe oe: output enable v dd : power supply p00 to p07: port 0 v pp : programming power supply p10 to p13: port 1 v ss : ground p20 to p27: port 2 wait: wait p30 to p37: port 3 we: write enable p40 to p45: port 4 x1, x2: crystal p50 to p52: port 5 chapter 1 introduction user?s manual u14359ej5v1ud 26 1.6 function blocks 1.6.1 internal block diagram nmi intp000 to intp001, intp010 to intp011, intp020 to intp021, intp030 to intp031 intp100 to intp103, intp110 to intp113, intp120 to intp123, intp130 to intp133 to00 to to03 ti000, ti010, ti020, ti030 intc rpu sio rom note 1 ram note 2 cpu 32-bit barrel shifter pc system registers general-purpose registers (32 bits 32) alu multiplier (32 32 64) ports pdl0 to pdl15 pal0 to pal15 pah0 to pah9 pcs0 to pcs7 pct0, pct1, pct4 to pct7 pcm0 to pcm5 pcd0 to pcd3 pbd0 to pbd3 p70 to p77 p50 to p52 p40 to p45 p30 to p37 p21 to p27 p20 p10 to p13 p00 to p07 cg system controller bcu clkout cksel x1 x2 cv dd cv ss mode0, mode1 mode2/v pp note 3 reset v dd v ss uart0/csi0 uart1/csi1 uart2 csi2 adc so0/txd0 si0/rxd0 sck0 so1/txd1 si1/rxd1 sck1 txd2 rxd2 pwm0 so2 si2 sck2 ani0 to ani7 av ref /av dd av ss adtrg instruction queue memc hldrq hldak cs0, cs7 cs1/ras1, cs3/ras3 cs4/ras4, cs6/ras6 cs2/iord cs5/iowr selfref refrq bcyst lbe/sdcas ube/sdras sdclk sdcke we rd oe uwr/ucas/udqm lwr/lcas/ldqm wait a0 to a25 d0 to d15 busclk dramc dmac romc pwm0 pwm1 pwm1 dmarq0 to dmarq3 dmaak0 to dmaak3 tc0 to tc3 notes 1. pd703103a: romless pd703105a, 703106a: 128 kb (mask rom) pd703107a: 256 kb (mask rom) pd70f3107a: 256 kb (flash memory) 2. pd703103a, 703105a: 4 kb pd703106a, 703107a, 70f3107a: 10 kb 3. valid for pd70f3107a only chapter 1 introduction user?s manual u14359ej5v1ud 27 1.6.2 on-chip units (1) cpu the cpu uses five-stage pipeline control to enable sing le-clock execution of addres s calculations, arithmetic logic operations, data transfers, and almo st all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits) and a barrel shifter (32 bits), help acce lerate processing of complex instructions. (2) bus control unit (bcu) the bcu starts the required external bus cycle bas ed on the physical address obtained by the cpu. when an instruction is fetched from external memory area an d the cpu does not send a bus cycle start request, the bcu generates a prefetch address a nd prefetches the instruction code. the prefetched in struction code is stored in an instruction queue in the cpu. the bcu controls a dram controll er (dramc), page rom controller (romc), and dma controller (dmac) and performs external memory access and dma transfer. (a) dram controller (dramc) (i) sdram the dram controller generates the sdras, s dcas, udqm, and ldqm signals and performs access control for sdram. cas latency 2 and 3 are supported, and the burst length is fixed to 1. a refresh function that su pports the cbr refresh cycle and a dyna mic self-refresh function based on an external input are also available. (ii) edo dram the dram controller generates the ras, ucas, and lcas signals (2cas control) and performs access control for edo dram. edo dram is supported, and there are two ty pes of access: normal access (off page) and page access (on page). a refresh function that su pports the cbr refresh cycle and a dyna mic self-refresh function based on an external input are also available. (b) page rom controller (romc) this controller supports accessing rom that includes the page access function. it performs address comparisons with the immediately preceding bus cycle and executes wait control for normal access (off-page)/page access (on-page). it can handle page widths of 8 to 128 bytes. (c) dma controller (dmac) this controller controls data transfer between memory and i/o instead of the cpu. there are two address modes: flyby (1-cycle) transfer, and 2-cycle transfer. there are three bus modes, single transfer, single step transfer, and block transfer. chapter 1 introduction user?s manual u14359ej5v1ud 28 (3) rom the pd703105a and 703106a have 128 kb of on-chip mask rom, the pd703107a has 256 kb of on-chip mask rom and the pd70f3107a has 256 kb of on-chip flash memory. the pd703103a does not include on-chip rom. during instruction fetch, rom/flash memory c an be accessed from the cpu in 1-clock cycles. if single-chip mode 0 or flash memory programming mode is set, memory mapping occurs from address 00000000h. if single-chip mode 1 is set, memory mapping occurs from address 00100000h. if romless mode is set, access is not possible. (4) ram ram is mapped from address ffffc000h. during instruction fetch or data access, data c an be accessed from the cpu in 1-clock cycles. (5) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0n0, intp0n1, intp1nn) from on-chip peripheral i/o and external hardware (n = 0 to 3). eight le vels of interrupt priorities can be specified for these interrupt requests, and multiple-interrupt servici ng control can be performed for interrupt sources. (6) clock generator (cg) this clock generator supplies frequencies which are 10 times the input clock (f x ) (using an on-chip pll) or 1/2 the input clock (w hen an on-chip pll is not used) as the internal system clock (f xx ). as the input clock, an external oscillator is connected to pins x1 and x2 (only when an on-chip pll synthesizer is used) or an external clock is input from the x1 pin. (7) real-time pulse unit (rpu) this unit incorporates a 4-channel 16-bit timer/event counter and 4-channel 16-bit interval timer, and can measure pulse widths or frequency and output a programmable pulse. (8) serial interfaces (sio) the serial interfaces consist of 4 channels divided between an asynchronous serial interface (uart) and clocked serial interface (csi). two of these chan nels can be switched between uart and csi, one channel is fixed to csi, and the remaining channel is fixed to uart. uart transfers data by using the txdn and rxdn pins (n = 0 to 2). csi transfers data by using the son, sin, and sckn pins (n = 0 to 2). (9) a/d converter (adc) this high-speed, high-resolution 10-bit a/d converter in cludes 8 analog input pins. conversion is performed using the successive approximation method. (10) pwm two channels for pwm signal output of 8-/9-/10-/12-bit resolution have been provided. by connecting an external low-pass filter, pwm output can be used as digital to analog conversion output. pwm is ideal for actuator control signals such as those in motors. chapter 1 introduction user?s manual u14359ej5v1ud 29 (11) ports as shown below, the following ports have general port functions and control pin functions. port port function control function port 0 8-bit i/o real-time pulse unit i/o, exte rnal interrupt input, pwm output, dma controller input port 1 4-bit i/o real-time pulse unit i/o , external interrupt input, pwm output port 2 1-bit input, 7-bit i/o nmi input, real-time pulse unit i/o, exter nal interrupt input, dma controller output port 3 8-bit i/o serial interface i/o, external in terrupt input, a/d converter external trigger input port 4 6-bit i/o serial interface i/o port 5 3-bit i/o real-time pulse unit i/o, external interrupt input port 7 8-bit input a/d converter input port al 8-/16-bit i/o external address bus port ah 8-/10-bit i/o external address bus port dl 8-/16-bit i/o external data bus port cs 8-bit i/o external bus interface control signal output port ct 6-bit i/o external bus interface control signal output port cm 6-bit i/o wait insertion signal input, in ternal system clock outpu t, external bus interface control signal i/o, self-ref resh request signal input port cd 4-bit i/o external bus interface control signal output port bd 4-bit i/o dma controller output 1.7 differences among products item pd703103a pd703105a pd703106a pd703107a pd703106a(a) pd703107a(a) pd70f3107a pd70f3107a(a) mask rom flash memory internal rom none 128 kb 256 kb 128 kb 256 kb 256 kb internal ram 4 kb 10 kb flash memory programming mode none provided v pp pin none provided package 144lqfp 144lqfp 161fbga 144lqfp 144lqfp 161fbga 144lqfp quality grade standard s pecial standard special electrical characteristics power consumption differs (refer to chapter 17 electrical specifications ). others noise immunity and noise r adiation differ because the circuit scale and mask layout differ. remark 144lqfp: 144-pin plastic lqfp (fine pitch) (20 20) 161fbga: 161-pin plastic fbga (13 13) user?s manual u14359ej5v1ud 30 chapter 2 pin functions the names and functions of the pins in the v850e/ma1 are listed below. these pins can be divided into port pins and non-port pins according to their functions. 2.1 list of pin functions (1) port pins (1/3) pin name i/o function alternate function p00 pwm0 p01 ti000/intp000 p02 intp001 p03 to00 p04 dmarq0/intp100 p05 dmarq1/intp101 p06 dmarq2/intp102 p07 i/o port 0 8-bit i/o port input/output can be specified in 1-bit units. dmarq3/intp103 p10 pwm1 p11 intp010/ti010 p12 intp011 p13 i/o port 1 4-bit i/o port input/output can be specified in 1-bit units. to01 p20 input nmi p21 intp020/ti020 p22 intp021 p23 to02 p24 tc0/intp110 p25 tc1/intp111 p26 tc2/intp112 p27 i/o port 2 p20 is an input port dedicated to checking the nmi input status. if a valid edge is input, it operates as an nmi input. p21 to p27 are a 7-bit i/o port. input/output can be specified in 1-bit units. tc3/intp113 p30 so2/intp130 p31 si2/intp131 p32 sck2/intp132 p33 txd2/intp133 p34 rxd2/intp120 p35 intp121 p36 intp122 p37 i/o port 3 8-bit i/o port input/output can be specified in 1-bit units. adtrg/intp123 chapter 2 pin functions user?s manual u14359ej5v1ud 31 (2/3) pin name i/o function alternate function p40 txd0/so0 p41 rxd0/si0 p42 sck0 p43 txd1/so1 p44 rxd1/si1 p45 i/o port 4 6-bit i/o port input/output can be specified in 1-bit units. sck1 p50 intp030/ti030 p51 intp031 p52 i/o port 5 3-bit i/o port input/output can be specified in 1-bit units. to03 p70 to p77 input port 7 8-bit input-only port ani0 to ani7 pbd0 to pbd3 i/o port bd 4-bit i/o port input/output can be specified in 1-bit units. dmaak0 to dmaak3 pcm0 wait pcm1 clkout/busclk pcm2 hldak pcm3 hldrq pcm4 refrq pcm5 i/o port cm 6-bit i/o port input/output can be specified in 1-bit units. selfref pct0 lcas/lwr/ldqm pct1 ucas/uwr/udqm pct4 rd pct5 we pct6 oe pct7 i/o port ct 6-bit i/o port input/output can be specified in 1-bit units. bcyst pcs0 cs0 pcs1 cs1/ras1 pcs2 cs2/iowr pcs3 cs3/ras3 pcs4 cs4/ras4 pcs5 cs5/iord pcs6 cs6/ras6 pcs7 i/o port cs 8-bit i/o port input/output can be specified in 1-bit units. cs7 pcd0 sdcke pcd1 sdclk pcd2 lbe/sdcas pcd3 i/o port cd 4-bit i/o port input/output can be specified in 1-bit units. ube/sdras chapter 2 pin functions user?s manual u14359ej5v1ud 32 (3/3) pin name i/o function alternate function pah0 to pah9 i/o port ah 8-/10-bit i/o port input/output can be specified in 1-bit units. a16 to a25 pal0 to pal15 i/o port al 8-/16-bit i/o port input/output can be specified in 1-bit units. a0 to a15 pdl0 to pdl15 i/o port dl 8-/16-bit i/o port input/output can be specified in 1-bit units. d0 to d15 chapter 2 pin functions user?s manual u14359ej5v1ud 33 (2) non-port pins (1/4) pin name i/o function alternate function to00 p03 to01 p13 to02 p23 to03 output pulse signal output of timer c0 to c3 p52 ti000 p01/intp000 ti010 p11/intp010 ti020 p21/intp020 ti030 input external count clock input of timer c0 to c3 p50/intp030 intp000 p01/ti000 intp001 external maskable interrupt request input, or timer c0 external capture trigger input p02 intp010 p11/ti010 intp011 external maskable interrupt request input, or timer c1 external capture trigger input p12 intp020 p21/ti020 intp021 external maskable interrupt request input, or timer c2 external capture trigger input p22 intp030 p50/ti030 intp031 input external maskable interrupt request input, or timer c3 external capture trigger input p51 intp100 p04/dmarq0 intp101 p05/dmarq1 intp102 p06/dmarq2 intp103 p07/dmarq3 intp110 p24/tc0 intp111 p25/tc1 intp112 p26/tc2 intp113 p27/tc3 intp120 p34/rxd2 intp121 p35 intp122 p36 intp123 p37/adtrg intp130 p30/so2 intp131 p31/si2 intp132 p32/sck2 intp133 input external maskable interrupt request input p33/txd2 so0 p40/txd0 so1 p43/txd1 so2 output csi0 to sci2 serial transmission data output (3-wire) p30/intp130 chapter 2 pin functions user?s manual u14359ej5v1ud 34 (2/4) pin name i/o function alternate function si0 p41/rxd0 si1 p44/rxd1 si2 input csi0 to csi2 serial reception data input (3-wire) p31/intp131 sck0 p42 sck1 p45 sck2 i/o csi0 to csi2 serial clock i/o (3-wire) p32/intp132 txd0 p40/so0 txd1 p43/so1 txd2 output uart0 to uart2 serial transmission data output p33/intp133 rxd0 p41/si0 rxd1 p44/si1 rxd2 input uart0 to uart2 serial reception data input p34/intp120 pwm0 p00 pwm1 output pwm pulse signal output p10 ani0 to ani7 input analog inputs to a/d converter p70 to p77 adtrg input a/d converter external trigger input p37/intp123 dmarq0 p04/intp100 dmarq1 p05/intp101 dmarq2 p06/intp102 dmarq3 input dma request signal input p07/intp103 dmaak0 pbd0 dmaak1 pbd1 dmaak2 pbd2 dmaak3 output dma acknowledge signal output pbd3 tc0 p24/intp110 tc1 p25/intp111 tc2 p26/intp112 tc3 output dma transfer end (terminal count) signal output p27/intp113 nmi input non-maskable interrupt request signal input p20 mode0 ? mode1 ? mode2 input v850e/ma1 operating mode specification v pp v pp input flash memory programmi ng power-supply application pin ( pd70f3107a only) mode2 wait input control signal input that inserts a wait in the bus cycle pcm0 hldak output bus hold acknowledge output pcm2 hldrq input bus hold request input pcm3 refrq output refresh request signal output for dram pcm4 selfref input self-refresh request input for dram pcm5 chapter 2 pin functions user?s manual u14359ej5v1ud 35 (3/4) pin name i/o function alternate function lcas output column address strobe signal output for dram lower data pct0/lwr/ldqm ucas output column address strobe signal output for dram higher data pct1/uwr/udqm lwr output external data lower byte write strobe signal output pct0/lcas/ldqm uwr output external data higher byte wr ite strobe signal output pct1/ucas/udqm ldqm output output disable/write mask signal output for sdram lower data pct0/lcas/lwr udqm output output disable/write mask signal output for sdram higher data pct1/ucas/uwr rd output external data bus read strobe signal output pct4 we output write enable signal output for dram pct5 oe output output enable signal output for dram pct6 bcyst output strobe signal output that shows the start of the bus cycle pct7 cs0 pcs0 cs1 pcs1/ras1 cs2 pcs2/iowr cs3 pcs3/ras3 cs4 pcs4/ras4 cs5 pcs5/iord cs6 pcs6/ras6 cs7 output chip select signal output pcs7 ras1 pcs1/cs1 ras3 pcs3/cs3 ras4 pcs4/cs4 ras6 output row address strobe signal output for dram pcs6/cs6 iowr output dma write strobe signal output pcs2/cs2 iord output dma read strobe signal output pcs5/cs5 sdcke output sdram clock enable signal output pcd0 sdclk output sdram clock signal output pcd1 sdcas output column address strobe signal output for sdram pcd2/lbe sdras output row address strobe signal output for sdram pcd3/ube lbe output external data bus lower byte enable signal output pcd2/sdcas ube output external data bus higher byte enable signal output pcd3/sdras d0 to d15 i/o 16-bit data bus for external memory pdl0 to pdl15 a0 to a15 pal0 to pal15 a16 to a25 output 26-bit address bus for external memory pah0 to pah9 reset input system reset input ? x1 input ? x2 ? connects the crystal resonator for system clock oscillation. in the case of an external source supplyi ng the clock, it is input to x1. ? clkout output system clock output pcm1/busclk busclk output bus clock output pcm1/clkout chapter 2 pin functions user?s manual u14359ej5v1ud 36 (4/4) pin name i/o function alternate function cksel input input specifying the clock generator's operating mode ? av ref input reference voltage applied to a/d converter av dd av dd ? positive power supply for a/d converter av ref av ss ? ground potential for a/d converter ? cv dd ? positive power supply for dedicated clock generator ? cv ss ? ground potential for dedicated clock generator ? v dd ? positive power supply ? v ss ? ground potential ? chapter 2 pin functions user?s manual u14359ej5v1ud 37 2.2 pin status the status of each pin after reset, in power-save mo de (software stop, idle, halt modes), and during dma transfer, refresh, and bus hold (th) is shown below. operating status pin reset (single-chip mode 0) reset (single-chip mode 1, romless mode 0,1) idle mode/software stop mode halt mode/during dma transfer, refresh bus hold (th) note a0 to a15 (pal0 to pal15) hi-z hi-z hi-z operating hi-z a16 to a25 (pah0 to pah9) hi-z hi-z hi-z operating hi-z d0 to d15 (pdl0 to pdl15) hi-z hi-z hi-z operating hi-z cs0 to cs7 (pcs0 to pcs7) hi-z hi-z self operating hi-z ras1, ras3, ras4, ras6 (pcs1, pcs3, pcs4, pcs6) cbr operating hi-z iowr (pcs2) h operating hi-z iord (pcs5) h operating hi-z lwr, uwr (pct0, pct1) hi-z hi-z h operating hi-z lcas, ucas (pct0, pct1) cbr operating hi-z ldqm, udqm (pct0, pct1) h operating hi-z rd (pct4) hi-z hi-z h operating hi-z we (pct5) hi-z hi-z h operating hi-z oe (pct6) hi-z hi-z h operating hi-z bcyst (pct7) hi-z hi -z h operating hi-z wait (pcm0) hi-z hi-z ? operating ? clkout (pcm1) hi-z operating l oper ating operating busclk (pcm1) l operating operating hldak (pcm2) hi-z hi-z h operating l hldrq (pcm3) hi-z hi-z ? operating operating refrq (pcm4) hi-z hi-z cbr operating operating selfref (pcm5) hi-z hi-z ? operating ? sdcke (pcd0) hi-z hi-z l operating operating sdclk (pcd1) hi-z hi-z l operating operating sdcas (pcd2) self operating hi-z lbe (pcd2) hi-z hi-z h operating hi-z sdras (pcd3) self operating hi-z ube (pcd3) hi-z hi-z h operating hi-z dmaak0 to dmaak3 (pbd0 to pbd3) hi-z hi-z h operating h note the pin set in the port mode hold s the status immediately before. remark hi-z: high-impedance h: high-level output l: low-level output ? : no sampling of input : no select function at reset cbr: a dram refresh state self: self-refresh state when pins are connected to sdram chapter 2 pin functions user?s manual u14359ej5v1ud 38 2.3 description of pin functions (1) p00 to p07 (port 0) 3-state i/o p00 to p07 function as an 8-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as i/o for the real-time pulse unit (rpu), external interrupt request input s, a pwm output, and dma request inputs. the operation mode can be set to port or control mode in 1-bit units, specified by the port 0 mode control register (pmc0). (a) port mode p00 to p07 can be set to input or output in 1- bit units using the port 0 mode register (pm0). (b) control mode p00 to p07 can be set to port/control mode in 1-bit units using the pmc0 register. (i) pwm0 (pulse width modulation) output this pin outputs the pwm pulse signal. (ii) ti000 (timer input) input this is the external count clock input pin for timer c0. (iii) to00 (timer output) output this pin outputs the pulse signals for timer c0. (iv) intp000, intp001 (external interrupt input) input these are external interrupt reques t input pins and the external capture trigger input pins for timer c0. (v) intp100 to intp103 (externa l interrupt input) input these are external interrupt request input pins. (vi) dmarq0 to dmarq3 (dma request) input these are dma service request signals. they correspond to dma channels 0 to 3, respectively, and operate independently of each other. the priority order is fixed to dmarq0 > dmarq1 > dmarq2 > dmarq3. these signals are sampled at the falling edge of the clkout signal. maintain an active level until a dma request is acknowledged. chapter 2 pin functions user?s manual u14359ej5v1ud 39 (2) p10 to p13 (port 1) 3-state i/o p10 to p13 function as a 4-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as i/o for the real-time pulse unit (rpu), external interrupt request inputs, and a pwm output. the operation mode can be set to port or control mode in 1-bit units, specified by the port 1 mode control register (pmc1). (a) port mode p10 to p13 can be set to input or output in 1- bit units using the port 1 mode register (pm1). (b) control mode p10 to p13 can be set to port/control mode in 1-bit units using the pmc1 register. (i) pwm1 (pulse width modulation) output this pin outputs the pwm pulse signal. (ii) ti010 (timer input) input this is the external count clock input pin for timer c1. (iii) to01 (timer output) output this pin outputs the pulse signal for timer c1. (iv) intp010, intp011 (external interrupt input) input these are external interrupt reques t input pins and the external capture trigger input pins for timer c1. chapter 2 pin functions user?s manual u14359ej5v1ud 40 (3) p20 to p27 (port 2) 3-state i/o port 2, except p20, which is an i nput pin dedicated to checki ng the input status of nmi, is a 7-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as i/o for the real-time pulse unit (rpu), external interrupt request inputs, and dma transfer termination outputs (terminal count). the operation mode can be set to port or control mode in 1-bit units, specified by the port 2 mode control register (pmc2). (a) port mode p21 to p27 can be set to input or output in 1-bit unit s using the port 2 mode register (pm2). p20 is an input port dedicated to checking the nmi input status, and if a valid edge is input, it operates as an nmi input. (b) control mode p21 to p27 can be set to port/control mode in 1-bit units using the pmc2 register. (i) nmi (non-maskable inte rrupt request) input this is the non-maskable interrupt request input pin. (ii) ti020 (timer input) input this is the external count clock input pin for timer c2. (iii) to02 (timer output) output this pin outputs the pulse signal for timer c2. (iv) intp020, intp021 (external interrupt input) input these are external interrupt reques t input pins and the external capture trigger input pins for timer c2. (v) intp110 to intp113 (externa l interrupt input) input these are external interrupt request input pins. (vi) tc0 to tc3 (terminal count) output these are signals from the dma controller indicati ng that dma transfer is complete. these signals become active for 1 clock at the rising edge of the clkout signal. chapter 2 pin functions user?s manual u14359ej5v1ud 41 (4) p30 to p37 (port 3) 3-state i/o p30 to p37 function as an 8-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as i/o for the serial interfaces (csi2, uart2), external interrupt request inputs , and the a/d converter external trigger input. the operation mode can be set to port or control mode in 1-bit units, specified by the port 3 mode control register (pmc3). (a) port mode p30 to p37 can be set to input or output in 1- bit units using the port 3 mode register (pm3). (b) control mode p30 to p37 can be set to port/control mode in 1-bit units using the pmc3 register. (i) txd2 (transmit data) output this pin outputs the serial transmit data of uart2. (ii) rxd2 (receive data) input this pin inputs the serial receive data of uart2. (iii) so2 (serial output) output this pin outputs the serial transmit data of csi2. (iv) si2 (serial input) input this pin inputs the serial receive data of csi2. (v) sck2 (serial clock) 3-state i/o this is the csi2 serial clock i/o pin. (vi) intp120 to intp123, intp130 to intp133 (external interrupt input) input these are external interrupt request input pins. (vii) adtrg (a/d trigger input) input this is the external trigger input pin for the a/d converter. chapter 2 pin functions user?s manual u14359ej5v1ud 42 (5) p40 to p45 (port 4) 3-state i/o p40 to p45 function as a 6-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as i/o for the serial interfaces (uart0/csi0, uart1/csi1). the operation mode can be set to port or control mode in 1-bit units, specified by the port 4 mode control register (pmc4). (a) port mode p40 to p45 can be set to input or output in 1-bi t units using the port 4 mode register (pm4). (b) control mode p40 to p45 can be set to port/control mode in 1-bit units using the pmc4 register. (i) txd0, txd1 (trans mit data) output these pins output uart0, ua rt1 serial transmit data. (ii) rxd0, rxd1 (receive data) input these pins input uart0, ua rt1 serial receive data. (iii) so0, so1 (serial output) output these pins output csi0, csi1 serial transmit data. (iv) si0, si1 (serial input) input these pins input csi0, cs i1 serial receive data. (v) sck0, sck1 (serial clock) 3-state i/o these are the csi0, csi1 serial clock i/o pins. chapter 2 pin functions user?s manual u14359ej5v1ud 43 (6) p50 to p52 (port 5) 3-state i/o p50 to p52 function as a 3-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as i/o for the real-time pulse unit (rpu) and external interrupt request inputs. the operation mode can be set to port or control mode in 1-bit units, specified by the port 5 mode control register (pmc5). (a) port mode p50 to p52 can be set to input or output in 1- bit units using the port 5 mode register (pm5). (b) control mode p50 to p52 can be set to port/control mode in 1-bit units using the pmc5 register. (i) ti030 (timer input) input this is the external count clock input pin for timer c3. (ii) to03 (timer output) output this pin outputs the pulse signal for timer c3. (iii) intp030, intp031 (external interrupt input) input these are external interrupt reques t input pins and the external capture trigger input pins for timer c3. (7) p70 to p77 (port 7) 3-state i/o p70 to p77 function as an 8-bit input-only port in which all pins are fixed as input pins. besides functioning as a port, in the control mode, these pins operate as analog inputs for the a/d converter. however, the input ports and analog input pins cannot be switched. (a) port mode p70 to p77 are input-only pins. (b) control mode p70 to p77 have alternate functions as pins ani0 to ani7, but these alternate functions are not switchable. (i) ani0 to ani7 (analog input) input these are analog input pins for the a/d converter. connect a capacitor between these pins and av ss to prevent noise-related operation faults. also, do not apply voltage that is outside the range for av ss and av ref to pins that are being used as inputs for the a/d converter. if it is possible for noise above the av ref range or below the av ss to enter, clamp these pins using a diode that has a small v f value. chapter 2 pin functions user?s manual u14359ej5v1ud 44 (8) pbd0 to pbd3 (port bd) 3-state i/o pbd0 to pbd3 function as a 4-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as dma acknowledge outputs. the operation mode can be set to port or control in 1-bi t units, specified by the port bd mode control register (pmcbd). (a) port mode pbd0 to pbd3 can be set to input or output in 1-bi t units using the port bd mode register (pmbd). (b) control mode pbd0 to pbd3 can be set to port/control mode in 1-bit units using the pmcbd register. (i) dmaak0 to dmaak3 (dma acknowledge) output these signals show that a dma service request was granted. they correspond to dma channel 0 to 3, respectively, and operate independently of each other. these signals become active only when external memory is being accessed. when dma transfers are being executed between internal ram and on- chip peripheral i/o, they do not become active. these signals are activated at the falling edge of t he clkout signal in the t0, t1r, t1fh state of the dma cycle, and maintained at an active level during dma transfers. (9) pcm0 to pcm5 (port cm) 3-state i/o pcm0 to pcm5 function as a 6-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in the control mode, thes e pins operate as the wait insertion signal input, system clock output, bus hold control signal, refresh request signal output for dram, and self-refresh request signal input. the operation mode can be set to port or control in 1-bit units, specified by the por t cm mode control register (pmccm). (a) port mode pcm0 to pcm5 can be set to input or output in 1- bit units using the port cm mode register (pmcm). (b) control mode pcm0 to pcm5 can be set to port/control mode in 1-bit units using the pmccm register. (i) wait (wait) input this is the control signal input pi n at which a data wait is inserted in the bus cycle. the wait signal can be input asynchronously to the clkout signal . when the clkout signal rises, sampling is executed. when the set/hold time is not terminat ed within the sampling timing, wait insertion may not be executed. caution in romless modes 0 and 1 and single-chip mode 1, input to the wait pin is valid immediately after release of reset. if a low level is input to the wait pin because an external pull-down resistor is connected to it, the external bus is placed in the wait status. chapter 2 pin functions user?s manual u14359ej5v1ud 45 (ii) clkout (clock output) output this is the internal system clock output pin. in single-chip mode 0, because port mode is entered during the reset period, output does not occur from the clkout pin. clkout output can be executed by setting the port cm mode control regi ster (pmccm) and the port cm function control register (pfccm). (iii) busclk (bus clock output) output this pin outputs a bus clock only in the bus cycle when the external bus cycl e period is set to two times that of the normal. the bus clock operates at the operating frequency of 1/2 the internal system clock by setting the bus cycle period control re gister (bcp). to execute busclk output, set the port cm mode control register (pmccm) and the port cm function control register (pfccm). (iv) hldak (hold ack nowledge) output in this mode, this pin is the acknowledge signal ou tput pin that indicates t he high impedance status for the address bus, data bus, and control bus when the v850e/ma1 receives a bus hold request. while this signal is active, the impedance of the address bus, data bus and control bus becomes high and the bus mastership is transferred to the external bus master. (v) hldrq (hold request) input in this mode, this pin is the input pin through wh ich an external device requests the v850e/ma1 to release the address bus, data bus, and control bus. the hldrq signal can be input asynchronously to the clkout signal. when this pin is active, the address bus, data bus, and control bus are set to the high impedance status. this occurs either when the v850e/ma1 completes execution of the current bus cycle or immediately if no bus cycle is being executed, then the hldak signal is set as active and the bus is released. in order to make the bus hold state secure, k eep the hldrq signal active until the hldak signal is output. caution in romless modes 0 and 1 and single-chi p mode 1, input to the hldrq pin is valid immediately after release of reset. if a low level is input to the hldrq pin because an external pull-down resistor is connected to it, the external bus is placed in the bus hold status. (vi) refrq (refresh request) output this is the refresh request signal for dram. this signal becomes active during the refresh cycle. also, during bus hold, it becomes active when a refresh request is generated and informs the exte rnal bus master that a refresh request was generated. also, in cases when the address is decoded by an external circuit to increase the connected dram, or in cases when external simm?s are connected, this signal is used for ras control during the refresh cycle. (vii) selfref (self-refresh request) input this is a self-refresh request signal input for dram. the internal rom and internal ram can be accessed even in the self-refresh cycle. however, access to a peripheral i/o register or external devic e is held pending until the self-refresh cycle is cancelled. chapter 2 pin functions user?s manual u14359ej5v1ud 46 caution in romless modes 0 and 1, and singl e-chip mode 1, inpu t to the selfref pin becomes valid immediately a fter the reset signal has b een cleared. note that, consequently, if a high level is input to the selfref pin by an external pull-up resistor, the normal instructi on fetch cycle does not occur. (10) pct0, pct1, pct4 to pc t7 (port ct) 3-state i/o pct0, pct1, pct4 to pct7 function as a 6-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in the control mode, these pins operate as control signal outputs for when memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port ct mode control register (pmcct). (a) port mode pct0, pct1, pct4 to pct7 can be set to input or out put in 1-bit units using the port ct mode register (pmct). (b) control mode pct0, pct1, pct4 to pct7 can be set to port/control mode in 1-bit units using the pmcct register. (i) lcas (lower column address strobe) 3-state output this is the column address strobe signal for dram and the strobe signal for the cbr refresh cycle. for the data bus, the lower byte is valid. (ii) ucas (upper column address strobe) 3-state output this is the column address strobe signal for dram and the strobe signal for the cbr refresh cycle. for the data bus, the higher byte is valid. (iii) lwr (lower byte write strobe) 3-state output this strobe signal shows whether the bus cycle cu rrently being executed is a write cycle for the sram, external rom, or ex ternal peripheral i/o area. for the data bus, the lower byte becomes valid. if the bus cycle is a lower me mory write, it becomes active at the falling edge of the clkout signal in the t1 state and becomes inactive at the falling edge of the clkout signal in the t2 state. (iv) uwr (upper byte write strobe) 3-state output this strobe signal shows whether the bus cycle cu rrently being executed is a write cycle for the sram, external rom, or ex ternal peripheral i/o area. for the data bus, the higher byte becomes valid. if the bus cycle is a higher memory write, it becomes active at the falling edge of the clkout signal in the t1 st ate and becomes inactive at the falling edge of the clkout signal in the t2 state. (v) ldqm (lower dq mask enable) 3-state output this is a control signal for the data bus to sdram. for the data bus, the lower byte is valid. this signal carries out sdram output disable contro l during a read operation, and sdram byte mask control during a write operation. chapter 2 pin functions user?s manual u14359ej5v1ud 47 (vi) udqm (upper dq mask enable) 3-state output this is a control signal for the data bus to sdram. for the data bus, the higher byte is valid. this signal carries out sdram output disable contro l during a read operation, and sdram byte mask control during a write operation. (vii) rd (read strobe) 3-state output this strobe signal shows that the bus cycle current ly being executed is a read cycle for the sram, external rom, external peripheral i/o, or page rom area. in the idle state (ti), it becomes inactive. (viii) we (write enable) 3-state output this signal shows that the bus cycle currently being executed is a write cycle for the dram area. in the idle state (ti), it becomes inactive. (ix) oe (output enab le) 3-state output this signal shows that the bus cycle currently being executed is a read cycle for the dram area. in the idle state (ti), it becomes inactive. (x) bcyst (bus cycle start timing) 3-state output this outputs a status signal show ing the start of the bus cycle. it becomes active for 1-clock cycle from the start of each cycle. in the idle state (ti), it becomes inactive. chapter 2 pin functions user?s manual u14359ej5v1ud 48 (11) pcs0 to pcs7 (port cs) 3-state i/o pcs0 to pcs7 function as an 8-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in the control mode, th ese pins operate as control signal outputs for when memory and peripheral i/o are expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port cs mode control register (pmccs). (a) port mode pcs0 to pcs7 can be set to input or output in 1- bit units using the port cs mode register (pmcs). (b) control mode pcs0 to pcs7 can be set to port/control mode in 1-bit units using the pmccs register. (i) cs0 to cs7 (chip select) 3-state output these are the chip select sig nals for the sram, external rom, external peripheral i/o, and page rom area. the csn signal is assigned to memory block n (n = 0 to 7). it becomes active while the bus cycle that accesses the correspondi ng memory block is activated. (ii) ras1, ras3, ras4, ras6 (row address strobe) 3-state output these are the row address strobe signals for the dram area and the strobe signal for the refresh cycle. the rasn signal is assigned to me mory block n (n = 1, 3, 4, 6). during on-page disable, after the dram access bus cycle ends, it becomes inactive. during on-page enable, even after the dram access bus cycle ends, it remains in the active state. during the reset period and during a bus hold period, it is in the high-impedanc e state, so connect it to v dd via a resistor. (iii) iowr (i/o write) 3-state output this is the write strobe signal for external i/o durin g dma flyby transfer. it indicates whether the bus cycle currently being executed is a write cycle for external i/o during flyby transfer, or a write cycle for the sram area. note that if the ioen bit of the bcp register is set (1), this signal can be output even in the normal sram, external rom, or external i/o cycle. (iv) iord (i/o read) 3-state output this is the read strobe signal for external i/o during dma flyby transfer. it indicates whether the bus cycle currently being executed is a read cycle for external i/o during flyby transfer, or a read cycle for the sram area. note that if the ioen bit of the bcp register is set (1), this signal can be output even in the normal sram, external rom, or external i/o cycle. chapter 2 pin functions user?s manual u14359ej5v1ud 49 (12) pcd0 to pcd3 (port cd) 3-state i/o pcd0 to pcd3 function as a 4-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in control mode, these pins operate as control signal outputs for when the memory and peripheral i/o are expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port cd mode control register (pmccd). (a) port mode pcd0 to pcd3 can be set to input or output in 1-bit units using the port cd mode register (pmcd). (b) control mode pcd0 to pcd3 can be set to port or control mode in 1-bit units using the pmccd register. (i) sdcke (sdram clock enable) 3-state output this is the sdram clock enable output signal. it becomes inactive in self-refresh and standby mode. (ii) sdclk (sdram clock output) 3-state output this is an sdram dedicated clock output signal. the same frequency as the internal system clock is output. (iii) sdcas (sdram column address strobe) 3-state output this is a command output signal for sdram. (iv) sdras (sdram row address strobe) 3-state output this is a command output signal for sdram. (v) lbe (lower byte enable) 3-state output this is the signal that enables the lower byte of the external data bus. (vi) ube (upper byte enable) 3-state output this is the signal that enables the higher byte of the external data bus. chapter 2 pin functions user?s manual u14359ej5v1ud 50 (13) pah0 to pah9 (port ah) 3-state i/o pah0 to pah9 function as an 8- or 10-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in control mode (externa l expansion mode), these pins operate as an address bus (a16 to a25) for when the memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port ah mode control register (pmcah). (a) port mode pah0 to pah9 can be set to input or output in 1-bi t units using the port ah mode register (pmah). (b) control mode pah0 to pah9 can be set to function alternately as a16 to a25 using the pmcah register. (i) a16 to a25 (address) 3-state output these are the address output pins of the higher 10 bits of the address bus?s 26-bit address when the external memory is accessed. the output changes in synchronization with the rise of the clkout signal in the t1 state. in the idle state (ti), the address of the bus cycle immediately before is retained. (14) pal0 to pal15 (port al) 3-state i/o pal0 to pal15 function as an 8- or 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in control mode (externa l expansion mode), these pins operate as an address bus (a0 to a15) for when the memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port al mode control register (pmcal). (a) port mode pal0 to pal15 can be set to input or output in 1-bi t units using the port al mode register (pmal). (b) control mode pal0 to pal15 can be set to function alternately as a0 to a15 using the pmcal register. (i) a0 to a15 (address) 3-state output these are the address output pins of the lower 16 bits of the addr ess bus?s 26-bit address when the external memory is accessed. the output changes in synchronization with the rise of the clkout signal in the t1 state. in the idle state (ti), the address of the bus cycle immediately before is retained. chapter 2 pin functions user?s manual u14359ej5v1ud 51 (15) pdl0 to pdl15 (port dl) 3-state i/o pdl0 to pdl15 function as an 8- or 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in control mode (exter nal expansion mode), these pins operate as a data bus (d0 to d15) for when the memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port dl mode control register (pmcdl). (a) port mode pdl0 to pdl15 can be set to input or output in 1-bi t units using the port dl mode register (pmdl). (b) control mode pdl0 to pdl15 can be set to function alternately as d0 to d15 using the pmcdl register. (i) d0 to d15 (data) 3-state i/o these pins constitute a data bus for when the exte rnal memory is accessed. these are 16-bit data i/o bus pins. the output changes in synchronization with the clkout signal in the t1 state. in the idle state (ti), these pins become high impedance. (16) cksel (clock generator op erating mode select) input this is an input pin used to specify the clock generator?s operating mode. (17) mode0 to mode2 (mode) input these are input pins used to specify the operating mode. fix the operatio n mode of this pin via a resistor. (18) reset (reset) input reset is a signal that is input asynchronously and t hat has a constant low level width regardless of the operating clock?s status. when this signal is input, a system reset is executed as the first priority ahead of all other operations. in addition to being used for ordinary initialization/star t operations, this pin can also be used to release a standby mode (halt, idle, or software stop). (19) x1, x2 (crystal) these pins are used to connect the res onator that generates the system clock. (20) cv dd (power supply for clock generator) this pin supplies positive power to the clock generator. (21) cv ss (ground for clock generator) this is the ground pin for the clock generator. (22) v dd (power supply) these are the positive power supply pins for each internal unit. all the v dd pins should be connected to a positive power source. (23) v ss (ground) these are ground pins. all the v ss pins should be grounded. chapter 2 pin functions user?s manual u14359ej5v1ud 52 (24) av dd (analog power supply) this is the analog positive power su pply pin for the a/d converter. (25) av ss (analog ground) this is the ground pin for the a/d converter. (26) av ref (analog reference voltage) input this is the reference voltage supply pin for the a/d converter. (27) v pp (programming power supply) this is the positive power supply pin used for flash memory programming mode. this pin is used for the pd70f3107a. chapter 2 pin functions user?s manual u14359ej5v1ud 53 2.4 pin i/o circuits and recommende d connection of unused pins it is recommended that 1 to 10 k ? resistors be used when connecting to v dd or v ss via resistors. (1/2) pin name i/o circuit type recommended connection p00/pwm0 5 p01/intp000/ti000 p02/intp001 5-ac p03/to00 5 p04/dmarq0/intp100 to p07/dmarq3/intp103 5-ac p10/pwm1 5 p11/intp010/ti010, p12/intp011 5-ac p13/to01 5 input: independently connect to v dd or v ss via a resistor output: leave open p20/nmi 2 connect to v ss directly. p21/intp020/ti020, p22/intp021 5-ac p23/to02 5 p24/tc0/intp110 to p27/tc3/intp113 p30/so2/intp130 p31/si2/intp131 p32/sck2/intp132 p33/txd2/intp133 p34/rxd2/intp120 p35/intp121 p36/intp122 p37/adtrg/intp123 5-ac p40/txd0/so0 5 p41/rxd0/si0 p42/sck0 5-ac p43/txd1/so1 5 p44/rxd1/si1 p45/sck1 p50/intp030/ti030, p51/intp031 5-ac p52/to03 5 input: independently connect to v dd or v ss via a resistor output: leave open p70/ani0 to p77/ani7 9 connect to v ss directly. pbd0/dmaak0 to pbd3/dmaak3 5 input: independently connect to v dd or v ss via a resistor output: leave open pcm0/wait 5 input: independently connect to v dd via a resistor pcm1/clkout/busclk 5 input: independently connect to v dd or v ss via a resistor output: leave open chapter 2 pin functions user?s manual u14359ej5v1ud 54 (2/2) pin name i/o circuit type recommended connection pcm2/hldak 5 input: independently connect to v dd or v ss via a resistor output: leave open pcm3/hldrq 5 input: independently connect to v dd via a resistor pcm4/refrq 5 input: independently connect to v dd or v ss via a resistor output: leave open pcm5/selfref 5 input: independently connect to v ss via a resistor pct0/lcas/lwr/ldqm pct1/ucas/uwr/udqm pct4/rd pct5/we pct6/oe pct7/bcyst pcs0/cs0 pcs1/cs1/ras1 pcs2/cs2/iowr pcs3/cs3/ras3 pcs4/cs4/ras4 pcs5/cs5/iord pcs6/cs6/ras6 pcs7/cs7 pcd0/sdcke pcd1/sdclk pcd2/lbe/sdcas pcd3/ube/sdras pah0/a16 to pah9/a25 pal0/a0 to pal15/a15 pdl0/d0 to pdl15/d15 5 input: independently connect to v dd or v ss via a resistor output: leave open mode0, mode1 mode2 note 1 mode2/v pp note 2 ? reset ? cksel 2 ? av ss ? connect to v ss . av dd /av ref ? connect to v dd . notes 1. pd703103a, 703105a, 703106a, 703107a only. 2. pd70f3107a only chapter 2 pin functions user?s manual u14359ej5v1ud 55 2.5 pin i/o circuits type 2 type 5 p-ch n-ch v dd in/out data output disable input enable type 5-ac p-ch n-ch v dd in/out data output disable input enable in comparator + v ref (threshold voltage) p-ch n-ch input enable type 9 in schmitt-triggered input with hysteresis characteristics remark type 2, type 5, and type 5-ac are 5 v tolerant buffe rs. design the pattern ensuring that the coupling capacitance is small. user?s manual u14359ej5v1ud 56 chapter 3 cpu function the cpu of the v850e/ma1 is based on risc architecture and executes almost all the instructions in one clock cycle using 5-stage pipeline control. 3.1 features minimum instruction cycle: 20 ns (@ 50 mhz internal operation) memory space program space: 64 mb linear data space: 4 gb linear thirty-two 32-bit general-purpose registers internal 32-bit architecture five-stage pipeline control multiply/divide instructions saturated operation instructions one-clock 32-bit shift instruction load/store instruction with long/short instruction format four types of bit manipulation instructions set1 clr1 not1 tst1 chapter 3 cpu function user?s manual u14359ej5v1ud 57 3.2 cpu register set the registers of the v850e/ma1 can be classified into tw o categories: a general-purpose program register set and a dedicated system register set. a ll the registers have a 32-bit width. for details, refer to v850e1 user?s manual architecture . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrrupt source register) fepc fepsw (status saving register during nmi) (status saving register during nmi) eipc eipsw (status saving register during interrupt) (status saving register during interrupt) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (status saving register during exception/debug trap) (status saving register during exception/debug trap) ctpc ctpsw (status saving register during callt execution) (status saving register during callt execution) chapter 3 cpu function user?s manual u14359ej5v1ud 58 3.2.1 program register set the program register set includes general -purpose registers and a program counter. (1) general-purpose registers thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instruct ions, and care must be exercised when using these registers. r0 is a register that always holds 0, and is used for operations using 0 and offset 0 addressing. r30 is used, by means of the sld and sst instructions, as a base pointer for when memory is accessed. also, r1, r3 to r5, and r31 are implicitly used by the as sembler and c compiler. ther efore, before using these registers, their contents must be save d so that they are not lost. th e contents must be restored to the registers after the registers have been used. r2 may be used by the real-time os. if the real-time os does not use r2, it can be used as a variable register. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register working register for genera ting 32-bit immediate data r2 address/data variable register (when r2 is not used by the real-time os) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (where program code is located) r6 to r29 address/dat a variable registers r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution remark for detailed descriptions of r1, r3 to r5, and r31, which are used by the assembler and c compiler, refer to the ca850 (c compiler package) asse mbly language user?s manual . (2) program counter (pc) this register holds the instruction address during program execution. the lower 26 bi ts of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address during execution 0 after reset 00000000h chapter 3 cpu function user?s manual u14359ej5v1ud 59 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. to read/write these system r egisters, specify a system register number indicated below using the system register load/store instruction (lds r or stsr instruction). table 3-2. system register numbers operand specification no. system register name ldsr instruction stsr instruction 0 status saving register during interrupt (eipc) note 1 { { 1 status saving register during interrupt (eipsw) note 1 { { 2 status saving register during nmi (fepc) { { 3 status saving register during nmi (fepsw) { { 4 interrupt source register (ecr) { 5 program status word (psw) { { 6 to 15 reserved for future function ex pansion (operations that access these register numbers cannot be guaranteed). 16 status saving register du ring callt execution (ctpc) { { 17 status saving register du ring callt execution (ctpsw) { { 18 status saving register du ring exception/debug trap (dbpc) { note 2 { 19 status saving register during exception/debug trap (dbpsw) { note 2 { 20 callt base pointer (ctbp) { { 21 to 31 reserved for future function ex pansion (operations that access these register numbers cannot be guaranteed). notes 1. because this register has only one set, to approve mu ltiple interrupts, it is necessary to save this register by program. 2. these registers can be accessed only between dbtr ap instruction execution and dbret instruction execution. caution even if bit 0 of eipc, fepc, or ctpc is set to 1 with the ldsr instruction, bit 0 will be ignored when the program is returned by the reti instruction after in terrupt servicing (because bit 0 of the pc is fixed to 0). when setting the value of eipc, fepc, or ctpc, use an even value (bit 0 = 0). remark { : access allowed : access prohibited (1) interrupt source register (ecr) 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name function 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception/maskable interrupt chapter 3 cpu function user?s manual u14359ej5v1ud 60 (2) program status word (psw) the program status word (psw) is a collection of flags that indicate th e status of the pr ogram (result of instruction execution) and the status of the cpu. if the contents of a bit of this r egister are changed by using the ldsr instruction, the new contents are validated immediately after completion of ldsr instruction execution. interrupt request acknowledgement is held pending while the psw write instruction is being executed by the ldsr instruction. bits 31 to 8 of this register are reserved for fu ture function expansion (these bits are fixed to 0). (1/2) 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupt servicing. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is being pr ocessed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. this flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether a ca rry or a borrow occurred as a result of an operation. 0: carry or borrow did not occur. 1: carry or borrow occurred. 2 ov note indicates whether an overflow occurred during operation. 0: overflow did not occur. 1: overflow occurred. 1 s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. remark also read note on the next page. chapter 3 cpu function user?s manual u14359ej5v1ud 61 (2/2) note the result of a saturation-processed operation is dete rmined by the contents of the ov and s flags in the saturation operation. simply setting the ov flag (1 ) will set the sat flag (1) in a saturation operation. flag status status of operation result sat ov s saturation-processed operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (not exceeding the maximum) 0 negative (not exceeding the maximum) retains the value before operation 0 1 operation result itself chapter 3 cpu function user?s manual u14359ej5v1ud 62 3.3 operating modes 3.3.1 operating modes the v850e/ma1 has the following operating modes. mode specification is carri ed out using the mode0 to mode2 pins. (1) normal operation mode (a) single-chip modes 0, 1 access to the internal rom is enabled. in single-chip mode 0, after system reset is cleared, each pin related to the bus interface enters the port mode, program execution branches to the reset entr y address of the internal rom, and instruction processing starts. by setting the pmcal, pmcah, pmcdl, pmccs, pmcct, pmccm, and pmccd registers to control mode by instruction, an external device can be connected to the external memory area. in single-chip mode 1, after system reset is cleared , each pin related to the bus interface enters the control mode, program execution branches to the ex ternal device?s (memory) reset entry address, and instruction processing starts. the internal rom area is mapped from address 100000h. (b) romless modes 0, 1 after system reset is cleared, each pin related to the bus interface enters t he control mode, program execution branches to the external device?s (memo ry) reset entry address, and instruction processing starts. fetching of instructions and data access for internal rom becomes impossible. in romless mode 0, the data bus is a 16-bit data bus and in romless mode 1, the data bus is an 8-bit data bus. (2) flash memory programming mode ( pd70f3107a only) if this mode is specified, it becomes possible for the flash programmer to run a program to the on-chip flash memory. the initial value of the regist er differs depending on the mode. operating mode pmcal pmcah pmcdl pmccs pmcct pmccm pmccd bsc romless mode 0 ffffh 03ffh ffffh ffh f3h 3fh 0fh 5555h romless mode 1 ffffh 03ffh ffffh ffh f3h 3fh 0fh 0000h single-chip mode 0 0000h 0000h 0000h 00h 00h 00h 00h 5555h normal operation mode single-chip mode 1 ffffh 03ffh ffffh ffh f3h 3fh 0fh 5555h chapter 3 cpu function user?s manual u14359ej5v1ud 63 3.3.2 operating mode specification the operating mode is specified accord ing to the status of t he mode0 to mode2 pins. in an application system fix the specification of these pins and do not change them durin g operation. operation is not guaranteed if these pins are changed during operation. (a) pd703103a mode2 mode1 mode0 oper ating mode remarks l l l romless mode 0 16-bit data bus l l h normal operation mode romless mode 1 8-bit data bus other than above setting prohibited (b) pd703105a, 703106a, 703107a mode2 mode1 mode0 oper ating mode remarks l l l romless mode 0 16-bit data bus l l h romless mode 1 8-bit data bus l h l single-chip mode 0 internal rom area is allocated from address 000000h. l h h normal operation mode single-chip mode 1 internal rom area is allocated from address 100000h. other than above setting prohibited (c) pd70f3107a mode2/ v pp mode1 mode0 operating mode remarks 0 v l l romless mode 0 16-bit data bus 0 v l h romless mode 1 8-bit data bus 0 v h l single-chip mode 0 internal rom area is allocated from address 000000h. 0 v h h normal operation mode single-chip mode 1 internal rom area is allocated from address 100000h. 7.8 v h h/l flash memory programming mode ? other than above setting prohibited remark l: low-level input h: high-level input chapter 3 cpu function user?s manual u14359ej5v1ud 64 3.4 address space 3.4.1 cpu address space the cpu of the v850e/ma1 is of 32-bit architecture and supports up to 4 gb of linear address space (data space) during operand addressing (data access). also, in instru ction address addressing, a maximum of 64 mb of linear address space (program space) is supported. the following shows the cpu address space. figure 3-1. cpu address space ffffffffh 04000000h 03ffffffh 00000000h data area (4 gb linear) program area (64 mb linear) cpu address space chapter 3 cpu function user?s manual u14359ej5v1ud 65 3.4.2 image a 256 mb physical address space is seen as 16 images in the 4 gb cpu address space. in actuality, the same 256 mb physical address space is accessed regardless of the va lues of bits 31 to 28 of the cpu address. figure 3-2 shows the image of the virtual addressing space. physical address x0000000h can be seen as cpu address 00000000h, and in addition, can be seen as address 10000000h, address 20000000h, ? , address e0000000h, or address f0000000h. figure 3-2. images on address space ffffffffh f0000000h efffffffh 00000000h internal rom image image image internal ram on-chip peripheral i/o external memory physical address space fffffffh 0000000h image image e0000000h dfffffffh 20000000h 1fffffffh 10000000h 0fffffffh cpu address space chapter 3 cpu function user?s manual u14359ej5v1ud 66 3.4.3 wrap-around of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to 26 as a result of a branch address calculation, the higher 6 bits ignore the carry or borrow. therefore, the lower-limit address of the program sp ace, address 00000000h, and the upper-limit address 03ffffffh become contiguous addresses. wrap-around refers to a sit uation like this w hereby the lower- limit address and upper-limit address become contiguous. caution the 4 kb area of 03fff000h to 03ffffffh can be seen as an image of 0ffff000h to 0fffffffh. this area is access- prohibited. therefo re, do not execute any branch address calculation in which the result will r eside in any part of this area. 00000001h 00000000h 03ffffffh 03fffffeh program space program space (+) direction ( ) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit address of the program sp ace, address 00000000h, and the upper-limit address ffffffffh are contiguous addresses, and the data space is wrapped around at th e boundary of these addresses. 00000001h 00000000h ffffffffh fffffffeh data space data space (+) direction ( ) direction chapter 3 cpu function user?s manual u14359ej5v1ud 67 3.4.4 memory map the v850e/ma1 reserves areas as shown in figures 3-3 and 3-4. the mode is specified by the mode0 to mode2 pins. figure 3-3. memory map ( pd703103a, 703105a) xfffffffh internal peripheral i/o area internal ram area internal peripheral i/o area internal ram area internal peripheral i/o area internal ram area access prohibited note external memory area internal rom area external memory area internal rom area external memory area single-chip mode 0 single-chip mode 1 romless mode 0, 1 256 mb 1 mb 1 mb 4 kb xffff000h xfffefffh x0200000h x01fffffh x0100000h x00fffffh x0000000h xfffd000h xfffcfffh xfffc000h xfffbfffh 4 kb note by setting the pmcal, pmcah, pmcdl, pmccs, pmcct, pmccm, and pmccd registers to control mode, this area can be used as external memory area. remark for the pd703103a, only romless modes 0 and 1 are supported as the operating mode. chapter 3 cpu function user?s manual u14359ej5v1ud 68 figure 3-4. memory map ( pd703106a, 703107a, 70f3107a) xfffffffh on-chip peripheral i/o area internal ram area on-chip peripheral i/o area internal ram area on-chip peripheral i/o area internal ram area access prohibited note external memory area internal rom area external memory area internal rom area external memory area single-chip mode 0 single-chip mode 1 romless mode 0, 1 256 mb 1 mb 1 mb 4 kb xffff000h xfffefffh x0200000h x01fffffh x0100000h x00fffffh x0000000h xfffe800h xfffe7ffh xfffc000h xfffbfffh 10 kb note by setting the pmcal, pmcah, pmcdl, pmccs, pmcct, pmccm, and pmccd registers to control mode, this area can be used as external memory area. chapter 3 cpu function user?s manual u14359ej5v1ud 69 3.4.5 area (1) internal rom area (a) memory map ( pd703105a, 703106a, 703107a, 70f3107a) 1 mb of internal rom area, addre sses 00000h to fff ffh, is reserved. <1> pd703105a, 703106a 128 kb are provided at the following addres ses as physical internal rom (mask rom). ? in single-chip mode 0: addresses 000000h to 01ffffh ? in single-chip mode 1: addresses 100000h to 11ffffh <2> pd703107a 256 kb are provided at the following addres ses as physical internal rom (mask rom). ? in single-chip mode 0: addresses 000000h to 03ffffh ? in single-chip mode 1: addresses 100000h to 13ffffh <3> pd70f3107a 256 kb are provided at the following addresses as physical internal rom (flash memory). ? in single-chip mode 0: addresses 000000h to 03ffffh ? in single-chip mode 1: addresses 100000h to 13ffffh (b) interrupt/exception table the v850e/ma1 increases the interrupt response s peed by assigning handler addresses corresponding to interrupts/exceptions. the collection of these handler addresses is called an interrupt/exception table, which is located in the internal rom area. when an interrupt/exception re quest is acknowledged, execution jumps to the handler address, and the program written in that me mory is executed. table 3-3 shows the sources of interrupts/exceptions, and the corresponding addresses. remark when in romless modes 0 and 1, in singl e-chip mode 1, or in the case of the pd703103a, in order to restore correct operation after reset, provide a handler address to the reset routine at address 0 of the external memory. chapter 3 cpu function user?s manual u14359ej5v1ud 70 table 3-3. interrupt/exception table (1/2) start address of interrupt/exception table interrupt/exception source 00000000h reset 00000010h nmi 00000040h trap0n (n = 0 to f) 00000050h trap1n (n = 0 to f) 00000060h ilgop/dbg0 00000080h intov00 00000090h intov01 000000a0h intov02 000000b0h intov03 000000c0h intp000/intm000 000000d0h intp001/intm001 000000e0h intp010/intm010 000000f0h intp011/intm011 00000100h intp020/intm020 00000110h intp021/intm021 00000120h intp030/intm030 00000130h intp031/intm031 00000140h intp100 00000150h intp101 00000160h intp102 00000170h intp103 00000180h intp110 00000190h intp111 000001a0h intp112 000001b0h intp113 000001c0h intp120 000001d0h intp121 000001e0h intp122 000001f0h intp123 00000200h intp130 00000210h intp131 00000220h intp132 00000230h intp133 00000240h intcmd0 00000250h intcmd1 00000260h intcmd2 00000270h intcmd3 chapter 3 cpu function user?s manual u14359ej5v1ud 71 table 3-3. interrupt/exception table (2/2) start address of interrupt/exception table interrupt/exception source 00000280h intdma0 00000290h intdma1 000002a0h intdma2 000002b0h intdma3 000002c0h intcsi0 000002d0h intser0 000002e0h intsr0 000002f0h intst0 00000300h intcsi1 00000310h intser1 00000320h intsr1 00000330h intst1 00000340h intcsi2 00000350h intser2 00000360h intsr2 00000370h intst2 00000380h intad (c) internal rom area relocation function if set in single-chip mode 1, the internal rom area is located beginning from address 100000h, so booting from external memory becomes possible. therefore, in order to resume correct operation afte r reset, provide a handler address to the reset routine at address 0 of the external memory. figure 3-5. internal rom area in single-chip mode 1 internal rom area external memory area 200000h 1fffffh 100000h 0fffffh 000000h block 0 chapter 3 cpu function user?s manual u14359ej5v1ud 72 (2) internal ram area the 12 kb area of addresses fffc000h to fffefffh are re served for the internal ram area. the 12 kb area of 3ffc000h to 3ffefffh can be se en as an image of fffc000h to fffefffh. in the pd703103a and 703105a, the 4 kb area of addresses fffc000h to fffcfffh are provided as physical internal ram. in the pd703106a, 703107a, and 70f3107a, the 10 kb ar ea of addresses fffc000h to fffe7ffh are provided as physical internal ram. caution the following are as are access-prohibited. pd703103a, 703105 a: addresses fffd000h to fffefffh pd703106a, 703 107a, 70f3107a: addresses fffe800h to fffefffh pd703103a, 703105a internal ram area (4 kb) fffefffh fffd000h fffcfffh fffc000h pd703106a, 703107a, 70f3107a internal ram area (10 kb) fffefffh fffe800h fffe7ffh fffc000h access prohibited access prohibited chapter 3 cpu function user?s manual u14359ej5v1ud 73 (3) on-chip peripheral i/o area 4 kb of memory, addresses ffff000h to fffffffh, ar e provided as an on-chip peripheral i/o area. an image of addresses ffff000h to fffffffh can be seen at addresses 3fff000h to 3ffffffh note . note addresses 3fff000h to 3ffffffh ar e access-prohibited. to acce ss the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. fffffffh ffff000h on-chip peripheral i/o area (4 kb) peripheral i/o registers associated with the operating mo de specification and the state monitoring for the on- chip peripheral i/o are all memory-mapp ed to the on-chip perip heral i/o area. program fetches cannot be executed from this area. cautions 1. in the v850e/ma1, no registers exist whic h are capable of word access, but if a register is word accessed, halfword access is performe d twice in the order of lower address, then higher address of the word area, disr egarding the lower 2 bits of the address. 2. for registers in which byte access is possible, if halfword access is executed, the higher 8 bits become undefined during the read operation, and the lower 8 bits of data are written to the register during the write operation. 3. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. addresses 3fff000h to 3ffffffh cannot be specified as the source/destination address of dma transfer. be sure to use addresses ffff000h to fffffffh for the source/destination address of dma transfer. (4) external memory area 256 mb are available for external memory area. the lower 64 mb can be used as program/data area and the higher 192 mb as data area. when in single-chip mode 0: x0100000h to xfffbfffh when in single-chip mode 1: x0000000h to x00fffffh, x0200000h to xfffbfffh when in romless modes 0 and 1: x0000000h to xfffbfffh access to the external memory area uses the chip select signal assigned to each memory block (which is carried out in the cs unit set by chip area se lect control registers 0 and 1 (csc0, csc1)). note that the internal rom, intern al ram, and on-chip peripheral i/o ar eas cannot be accessed as external memory areas. chapter 3 cpu function user?s manual u14359ej5v1ud 74 3.4.6 external memory expansion by setting the port n mode control register (pmcn) to c ontrol mode, an external memory device can be connected to the external memory space using each pin of ports al , ah, dl, cs, ct, cm, and cd. each register is set by selecting control mode for each pin of these por ts using pmcn (n = al, ah, dl, cs, ct, cm, cd). note that the status after reset differs as shown below in accordance with the operating mode specification set by pins mode0 to mode2 (refer to 3.3 operating modes for details of the operating modes). (a) in the case of romless mode 0 because each pin of ports al, ah, dl, cs, ct, cm, and cd enters control mode following a reset, external memory can be used without making changes to the port n mode control register (pmcn) (the external data bus width is 16 bits). (b) in the case of romless mode 1 because each pin of ports al, ah, dl, cs, ct, cm, and cd enters control mode following a reset, external memory can be used without making changes to the port n mode control register (pmcn) (the external data bus width is 8 bits). (c) in the case of single-chip mode 0 after reset, since the internal rom area is access ed, each pin of ports al, ah, dl, cs, ct, cm, and cd enters the port mode and external devices cannot be used. to use external memory, set the por t n mode control register (pmcn). (d) in the case of single-chip mode 1 the internal rom area is allocated from address 1000 00h. as a result, because each pin of ports al, ah, dl, cs, ct, cm, and cd enters control mode following a reset, external memory can be used without making changes to the port n mode control regi ster (pmcn) (the external data bus width is 16 bits). remark n = al, ah, dl, cs, ct, cm, cd chapter 3 cpu function user?s manual u14359ej5v1ud 75 3.4.7 recommended use of address space the architecture of the v850e/ma1 r equires that a register that serves as a pointer be secured for address generation in operand data accessing of da ta space. operand data access from instruction can be directly executed at the address in this pointer register 32 kb. however, because the general-purpose registers that can be used as a pointer register are limited, by minimizing the deteriora tion of address calculation performance when changing the pointer value, the number of usable general-purpose register s for handling variables is maximized, and the program size can be saved. (1) program space of the 32 bits of the program counter (pc), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. of those valid bits, a contiguous 64 mb space, starting from address 00000000h, corresponds to the memory map of the program space. (2) data space with the v850e/ma1, a 256 mb physi cal address space is seen as 16 images in the 4 gb cpu address space. the highest bit (bit 25) of this 26-bit address is assigned as an address sign-extended to 32 bits. example application of wrap-around ( pd703105a) 00007fffh (r =) 00000000h ffffd000h ffff8000h internal rom area internal peripheral i/o area external memory area fffff000h ffffefffh ffffbfffh ffffcfffh ffffc000h internal ram area 32 kb 4 kb 4 kb 16 kb 0001ffffh when r = r0 (zero register) is specified with the ld /st disp16 [r] instruction, an addressing range of 00000000h 32 kb can be referenced with the sign-extended disp 16. by mapping the external memory in the 16 kb area in the figure, all resources including internal hardware can be accessed with one pointer. the zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers for the pointer. chapter 3 cpu function user?s manual u14359ej5v1ud 76 figure 3-6. recommended memory map ffffffffh fffffc14h fffffc13h fffff000h ffffefffh ffffc000h ffffbfffh 03ffd000h 03ffcfffh 03fff000h 03ffefffh 03ffc000h 03ffbfffh 00100000h 000fffffh 00020000h 0001ffffh 00000000h 03ffffffh 04000000h xfffffffh xffff000h xfffefffh xfffc000h xffffbfffh xfffd000h xfffcfffh x0100000h x00fffffh x0020000h x001ffffh x0000000h xffffc14h xffffc13h data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram external memory internal rom external memory external memory internal ram on-chip peripheral i/o note program space 64 mb internal rom internal rom note this area is access-prohibited. to access th e on-chip peripheral i/o, specify addresses ffff000h to fffffffh. remarks 1. the arrows indicate the recommended area. 2. this is a recommended memory map when the pd703105a is set to single-chip mode 0, and used in external expansion mode. chapter 3 cpu function user?s manual u14359ej5v1ud 77 3.4.8 peripheral i/o registers (1/9) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff000h port al pal r/w undefined fffff000h port all pall r/w undefined fffff001h port alh palh r/w undefined fffff002h port ah pah r/w undefined fffff002h port ahl pahl r/w undefined fffff003h port ahh pahh r/w undefined fffff004h port dl pdl r/w undefined fffff004h port dll pdll r/w undefined fffff005h port dlh pdlh r/w undefined fffff008h port cs pcs r/w undefined fffff00ah port ct pct r/w undefined fffff00ch port cm pcm r/w undefined fffff00eh port cd pcd r/w undefined fffff012h port bd pbd r/w undefined fffff020h port al mode register pmal r/w ffffh fffff020h port al mode register l pmall r/w ffh fffff021h port al mode register h pmalh r/w ffh fffff022h port ah mode register pmah r/w ffffh fffff022h port ah mode register l pmahl r/w ffh fffff023h port ah mode register h pmahh r/w ffh fffff024h port dl mode register pmdl r/w ffffh fffff024h port dl mode register l pmdll r/w ffh fffff025h port dl mode register h pmdlh r/w ffh fffff028h port cs mode register pmcs r/w ffh fffff02ah port ct mode register pmct r/w ffh fffff02ch port cm mode register pmcm r/w ffh fffff02eh port cd mode register pmcd r/w ffh fffff032h port bd mode register pmbd r/w ffh fffff040h port al mode control register pmcal r/w 0000h/ffffh fffff040h port al mode control register l pmcall r/w 00h/ffh fffff041h port al mode control register h pmcalh r/w 00h/ffh fffff042h port ah mode control register pmcah r/w 0000h/03ffh fffff042h port ah mode control register l pmcahl r/w 00h/ffh fffff043h port ah mode control register h pmcahh r/w 00h/03h chapter 3 cpu function user?s manual u14359ej5v1ud 78 (2/9) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff044h port dl mode control register pmcdl r/w 0000h/ffffh fffff044h port dl mode control register l pmcdll r/w 00h/ffh fffff045h port dl mode control register h pmcdlh r/w 00h/ffh fffff048h port cs mode control register pmccs r/w 00h/ffh fffff049h port cs function control register pfccs r/w 00h fffff04ah port ct mode control register pmcct r/w 00h/f3h fffff04ch port cm mode control register pmccm r/w 00h/3fh fffff04dh port cm function control register pfccm r/w 00h fffff04eh port cd mode control register pmccd r/w 00h/0fh fffff04fh port cd function control register pfccd r/w 00h fffff052h port bd mode control register pmcbd r/w 00h fffff060h chip area select control register 0 csc0 r/w 2c11h fffff062h chip area select control register 1 csc1 r/w 2c11h fffff066h bus size configuration register bsc r/w 0000h/5555h fffff068h endian configuration register bec r/w 0000h fffff06eh system wait control register vswc r/w 77h fffff080h dma source address register 0l dsa0l r/w undefined fffff082h dma source address register 0h dsa0h r/w undefined fffff084h dma destination address register 0l dda0l r/w undefined fffff086h dma destination address register 0h dda0h r/w undefined fffff088h dma source address register 1l dsa1l r/w undefined fffff08ah dma source address register 1h dsa1h r/w undefined fffff08ch dma destination address register 1l dda1l r/w undefined fffff08eh dma destination address register 1h dda1h r/w undefined fffff090h dma source address register 2l dsa2l r/w undefined fffff092h dma source address register 2h dsa2h r/w undefined fffff094h dma destination address register 2l dda2l r/w undefined fffff096h dma destination address register 2h dda2h r/w undefined fffff098h dma source address register 3l dsa3l r/w undefined fffff09ah dma source address register 3h dsa3h r/w undefined fffff09ch dma destination address register 3l dda3l r/w undefined fffff09eh dma destination address register 3h dda3h r/w undefined fffff0c0h dma transfer count register 0 dbc0 r/w undefined fffff0c2h dma transfer count register 1 dbc1 r/w undefined fffff0c4h dma transfer count register 2 dbc2 r/w undefined fffff0c6h dma transfer count register 3 dbc3 r/w undefined fffff0d0h dma addressing control register 0 dadc0 r/w 0000h chapter 3 cpu function user?s manual u14359ej5v1ud 79 (3/9) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff0d2h dma addressing control register 1 dadc1 r/w 0000h fffff0d4h dma addressing control register 2 dadc2 r/w 0000h fffff0d6h dma addressing control register 3 dadc3 r/w 0000h fffff0e0h dma channel control register 0 dchc0 r/w 00h fffff0e2h dma channel control register 1 dchc1 r/w 00h fffff0e4h dma channel control register 2 dchc2 r/w 00h fffff0e6h dma channel control register 3 dchc3 r/w 00h fffff0f0h dma disable status register ddis r 00h fffff0f2h dma restart register drst r/w 00h fffff100h interrupt mask register 0 imr0 r/w ffffh fffff100h interrupt mask register 0l imr0l r/w ffh fffff101h interrupt mask register 0h imr0h r/w ffh fffff102h interrupt mask register 1 imr1 r/w ffffh fffff102h interrupt mask register 1l imr1l r/w ffh fffff103h interrupt mask register 1h imr1h r/w ffh fffff104h interrupt mask register 2 imr2 r/w ffffh fffff104h interrupt mask register 2l imr2l r/w ffh fffff105h interrupt mask register 2h imr2h r/w ffh fffff106h interrupt mask register 3 imr3 r/w ffffh fffff106h interrupt mask register 3l imr3l r/w ffh fffff107h interrupt mask register 3h imr3h r/w ffh fffff110h interrupt control register ovic00 r/w 47h fffff112h interrupt control register ovic01 r/w 47h fffff114h interrupt control register ovic02 r/w 47h fffff116h interrupt control register ovic03 r/w 47h fffff118h interrupt control register p00ic0 r/w 47h fffff11ah interrupt control register p00ic1 r/w 47h fffff11ch interrupt control register p01ic0 r/w 47h fffff11eh interrupt control register p01ic1 r/w 47h fffff120h interrupt control register p02ic0 r/w 47h fffff122h interrupt control register p02ic1 r/w 47h fffff124h interrupt control register p03ic0 r/w 47h fffff126h interrupt control register p03ic1 r/w 47h fffff128h interrupt control register p10ic0 r/w 47h fffff12ah interrupt control register p10ic1 r/w 47h fffff12ch interrupt control register p10ic2 r/w 47h fffff12eh interrupt control register p10ic3 r/w 47h chapter 3 cpu function user?s manual u14359ej5v1ud 80 (4/9) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff130h interrupt control register p11ic0 r/w 47h fffff132h interrupt control register p11ic1 r/w 47h fffff134h interrupt control register p11ic2 r/w 47h fffff136h interrupt control register p11ic3 r/w 47h fffff138h interrupt control register p12ic0 r/w 47h fffff13ah interrupt control register p12ic1 r/w 47h fffff13ch interrupt control register p12ic2 r/w 47h fffff13eh interrupt control register p12ic3 r/w 47h fffff140h interrupt control register p13ic0 r/w 47h fffff142h interrupt control register p13ic1 r/w 47h fffff144h interrupt control register p13ic2 r/w 47h fffff146h interrupt control register p13ic3 r/w 47h fffff148h interrupt control register cmicd0 r/w 47h fffff14ah interrupt control register cmicd1 r/w 47h fffff14ch interrupt control register cmicd2 r/w 47h fffff14eh interrupt control register cmicd3 r/w 47h fffff150h interrupt control register dmaic0 r/w 47h fffff152h interrupt control register dmaic1 r/w 47h fffff154h interrupt control register dmaic2 r/w 47h fffff156h interrupt control register dmaic3 r/w 47h fffff158h interrupt control register csiic0 r/w 47h fffff15ah interrupt control register seic0 r/w 47h fffff15ch interrupt control register sric0 r/w 47h fffff15eh interrupt control register stic0 r/w 47h fffff160h interrupt control register csiic1 r/w 47h fffff162h interrupt control register seic1 r/w 47h fffff164h interrupt control register sric1 r/w 47h fffff166h interrupt control register stic1 r/w 47h fffff168h interrupt control register csiic2 r/w 47h fffff16ah interrupt control register seic2 r/w 47h fffff16ch interrupt control register sric2 r/w 47h fffff16eh interrupt control register stic2 r/w 47h fffff170h interrupt control register adic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power-save control register psc r/w 00h fffff200h a/d converter mode register 0 adm0 r/w 00h chapter 3 cpu function user?s manual u14359ej5v1ud 81 (5/9) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff201h a/d converter mode register 1 adm1 r/w 07h fffff202h a/d converter mode register 2 adm2 r/w 00h fffff210h a/d conversion result register 0 (10 bits) adcr0 r 0000h fffff212h a/d conversion result register 1 (10 bits) adcr1 r 0000h fffff214h a/d conversion result register 2 (10 bits) adcr2 r 0000h fffff216h a/d conversion result register 3 (10 bits) adcr3 r 0000h fffff218h a/d conversion result register 4 (10 bits) adcr4 r 0000h fffff21ah a/d conversion result register 5 (10 bits) adcr5 r 0000h fffff21ch a/d conversion result register 6 (10 bits) adcr6 r 0000h fffff21eh a/d conversion result register 7 (10 bits) adcr7 r 0000h fffff220h a/d conversion result register 0h (8 bits) adcr0h r 00h fffff221h a/d conversion result register 1h (8 bits) adcr1h r 00h fffff222h a/d conversion result register 2h (8 bits) adcr2h r 00h fffff223h a/d conversion result register 3h (8 bits) adcr3h r 00h fffff224h a/d conversion result register 4h (8 bits) adcr4h r 00h fffff225h a/d conversion result register 5h (8 bits) adcr5h r 00h fffff226h a/d conversion result register 6h (8 bits) adcr6h r 00h fffff227h a/d conversion result register 7h (8 bits) adcr7h r 00h fffff400h port 0 p0 r/w undefined fffff402h port 1 p1 r/w undefined fffff404h port 2 p2 r/w undefined fffff406h port 3 p3 r/w undefined fffff408h port 4 p4 r/w undefined fffff40ah port 5 p5 r/w undefined fffff40eh port 7 p7 r/w undefined fffff420h port 0 mode register pm0 r/w ffh fffff422h port 1 mode register pm1 r/w ffh fffff424h port 2 mode register pm2 r/w ffh fffff426h port 3 mode register pm3 r/w ffh fffff428h port 4 mode register pm4 r/w ffh fffff42ah port 5 mode register pm5 r/w ffh fffff440h port 0 mode control register pmc0 r/w 00h fffff442h port 1 mode control register pmc1 r/w 00h fffff444h port 2 mode control register pmc2 r/w 01h fffff446h port 3 mode control register pmc3 r/w 00h fffff448h port 4 mode control register pmc4 r/w 00h fffff44ah port 5 mode control register pmc5 r/w 00h chapter 3 cpu function user?s manual u14359ej5v1ud 82 (6/9) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff460h port 0 function control register pfc0 r/w 00h fffff464h port 2 function control register pfc2 r/w 00h fffff466h port 3 function control register pfc3 r/w 00h fffff468h port 4 function control register pfc4 r/w 00h fffff480h bus cycle type configuration register 0 bct0 r/w 8888h fffff482h bus cycle type configuration register 1 bct1 r/w 8888h fffff484h data wait control register 0 dwc0 r/w 7777h fffff486h data wait control register 1 dwc1 r/w 7777h fffff488h bus cycle control register bcc r/w ffffh fffff48ah address setup wait control register asc r/w ffffh fffff48ch bus cycle period control register bcp r/w 00h fffff49ah page-rom configurat ion register prc r/w 7000h fffff49eh refresh wait control register rwc r/w 00h dram configuration register 1 r/w 3fc1h fffff4a4h sdram configuration register 1 scr1 r/w 0000h refresh control register 1 r/w 0000h fffff4a6h sdram refresh control register 1 rfs1 r/w 0000h dram configuration register 3 r/w 3fc1h fffff4ach sdram configuration register 3 scr3 r/w 0000h refresh control register 3 r/w 0000h fffff4aeh sdram refresh control register 3 rfs3 r/w 0000h dram configuration register 4 r/w 3fc1h fffff4b0h sdram configuration register 4 scr4 r/w 0000h refresh control register 4 r/w 0000h fffff4b2h sdram refresh control register 4 rfs4 r/w 0000h dram configuration register 6 r/w 3fc1h fffff4b8h sdram configuration register 6 scr6 r/w 0000h refresh control register 6 r/w 0000h fffff4bah sdram refresh control register 6 rfs6 r/w 0000h fffff540h timer d0 tmd0 r 0000h fffff542h compare register d0 cmd0 r/w 0000h fffff544h timer mode control register d0 tmcd0 r/w 00h fffff550h timer d1 tmd1 r 0000h fffff552h compare register d1 cmd1 r/w 0000h fffff554h timer mode control register d1 tmcd1 r/w 00h fffff560h timer d2 tmd2 r 0000h fffff562h compare register d2 cmd2 r/w 0000h chapter 3 cpu function user?s manual u14359ej5v1ud 83 (7/9) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff564h timer mode control register d2 tmcd2 r/w 00h fffff570h timer d3 tmd3 r 0000h fffff572h compare register d3 cmd3 r/w 0000h fffff574h timer mode control register d3 tmcd3 r/w 00h fffff600h timer c0 tmc0 r 0000h fffff602h capture/compare register c00 ccc00 r/w 0000h fffff604h capture/compare register c01 ccc01 r/w 0000h fffff606h timer mode control register c00 tmcc00 r/w 00h fffff608h timer mode control register c01 tmcc01 r/w 20h fffff609h valid edge select register c0 sesc0 r/w 00h fffff610h timer c1 tmc1 r 0000h fffff612h capture/compare register c10 ccc10 r/w 0000h fffff614h capture/compare register c11 ccc11 r/w 0000h fffff616h timer mode control register c10 tmcc10 r/w 00h fffff618h timer mode control register c11 tmcc11 r/w 20h fffff619h valid edge select register c1 sesc1 r/w 00h fffff620h timer c2 tmc2 r 0000h fffff622h capture/compare register c20 ccc20 r/w 0000h fffff624h capture/compare register c21 ccc21 r/w 0000h fffff626h timer mode control register c20 tmcc20 r/w 00h fffff628h timer mode control register c21 tmcc21 r/w 20h fffff629h valid edge select register c2 sesc2 r/w 00h fffff630h timer c3 tmc3 r 0000h fffff632h capture/compare register c30 ccc30 r/w 0000h fffff634h capture/compare register c31 ccc31 r/w 0000h fffff636h timer mode control register c30 tmcc30 r/w 00h fffff638h timer mode control register c31 tmcc31 r/w 20h fffff639h valid edge select register c3 sesc3 r/w 00h fffff800h peripheral command register phcmd w undefined fffff802h peripheral status register phs r/w 00h fffff810h dma trigger factor register 0 dtfr0 r/w 00h fffff812h dma trigger factor register 1 dtfr1 r/w 00h fffff814h dma trigger factor register 2 dtfr2 r/w 00h fffff816h dma trigger factor register 3 dtfr3 r/w 00h fffff820h power-save mode register psmr r/w 00h fffff822h clock control register ckc r/w 00h fffff824h lock register lockr r 0xh chapter 3 cpu function user?s manual u14359ej5v1ud 84 (8/9) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff880h external interrupt mode register 0 intm0 r/w 00h fffff882h external interrupt mode register 1 intm1 r/w 00h fffff884h external interrupt mode register 2 intm2 r/w 00h fffff886h external interrupt mode register 3 intm3 r/w 00h fffff888h external interrupt mode register 4 intm4 r/w 00h fffff8a0h dma terminal count output control register dtoc r/w 01h fffff8d4h flash programming mode control register flpmc r/w 08h/0ch/00h fffff900h clocked serial in terface mode register 0 csim0 r/w 00h fffff901h clocked serial interf ace clock select register 0 csic0 r/w 00h fffff902h serial i/o shift register 0 sio0 r 00h fffff903h receive-only serial i/o shift register 0 sioe0 r 00h fffff904h clocked serial interfac e transmit buffer register 0 sotb0 r/w 00h fffff910h clocked serial in terface mode register 1 csim1 r/w 00h fffff911h clocked serial interf ace clock select register 1 csic1 r/w 00h fffff912h serial i/o shift register 1 sio1 r 00h fffff913h receive-only serial i/o shift register 1 sioe1 r 00h fffff914h clocked serial interfac e transmit buffer register 1 sotb1 r/w 00h fffff920h clocked serial in terface mode register 2 csim2 r/w 00h fffff921h clocked serial interf ace clock select register 2 csic2 r/w 00h fffff922h serial i/o shift register 2 sio2 r 00h fffff923h receive-only serial i/o shift register 2 sioe2 r 00h fffff924h clocked serial interfac e transmit buffer register 2 sotb2 r/w 00h fffffa00h asynchronous serial interface mode register 0 asim0 r/w 01h fffffa02h receive buffer register 0 rxb0 r ffh fffffa03h asynchronous serial interf ace status register 0 asis0 r 00h fffffa04h transmit buffer register 0 txb0 r/w ffh fffffa05h asynchronous serial interface transmit status register 0 asif0 r 00h fffffa06h clock select register 0 cksr0 r/w 00h fffffa07h baud rate generator control register 0 brgc0 r/w ffh fffffa10h aynchronous serial interface mode register 1 asim1 r/w 01h fffffa12h receive buffer register 1 rxb1 r ffh fffffa13h asynchronous serial interf ace status register 1 asis1 r 00h fffffa14h transmit buffer register 1 txb1 r/w ffh fffffa15h aynchronous serial interface transmit status register 1 asif1 r 00h fffffa16h clock select register 1 cksr1 r/w 00h fffffa17h baud rate generator control register 1 brgc1 r/w ffh chapter 3 cpu function user?s manual u14359ej5v1ud 85 (9/9) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffffa20h aynchronous serial interface mode register 2 asim2 r/w 01h fffffa22h receive buffer register 2 rxb2 r ffh fffffa23h asynchronous serial interf ace status register 2 asis2 r 00h fffffa24h transmit buffer register 2 txb2 r/w ffh fffffa25h asynchronous serial interface transmit status register 2 asif2 r 00h fffffa26h clock select register 2 cksr2 r/w 00h fffffa27h baud rate generator control register 2 brgc2 r/w ffh fffffc00h pwm control register 0 pwmc0 r/w 40h fffffc02h pwm buffer register 0 pwmb0 r/w 0000h fffffc10h pwm control register 1 pwmc1 r/w 40h fffffc12h pwm buffer register 1 pwmb1 r/w 0000h chapter 3 cpu function user?s manual u14359ej5v1ud 86 3.4.9 specific registers specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. the v850e/ma1 has three specific registers, the power-s ave control register (psc) (refer to 9.5.2 (3) power-save control register (psc) ), clock control register (ckc) (refer to 9.3.4 clock control register (ckc) ), and flash programming mode control register (flpmc) (refer to 16.7.12 flash programming mode control register (flpmc) ). disable dma transfer when writ ing to a specific register. there are also two protection regist ers supporting write operations for spec ific registers to avoid an unexpected stoppage of the app lication system due to errone ous program execution. these two registers are the command register (prcmd) and peripheral command register (phcmd) (refer to 9.5.2 (2) command register (prcmd) and 9.3.3 peripheral command register (phcmd) ). 3.4.10 system wait control register (vswc) the system wait control regist er (vswc) is a register t hat controls the bus access wa it for the on-chip peripheral i/o registers. access to on-chip peripheral i/o registers is made in 3 cl ocks (without wait), however, in the v850e/ma1 waits may be required depending on the operation frequency. set the values described in the table below to the vswc register in accordance with the operation frequency used. this register can be read/written in 8-bit uni ts (address: fffff06eh, initial value: 77h). operation frequency (f xx ) set value of vswc number of waits for on-chip peripheral i/o register access 4 mhz f xx < 33 mhz 11h 2 33 mhz f xx 50 mhz 12h (recommended), or 13h when vswc = 12h: 3 (recommended), or when vswc = 13h: 4 remark if the timing of changing a count value contend with the timing of accessing a register when accessing a register having status flags that indicate the status of the intern al peripheral functions (such as asifn) or a register that indicates the count value of a timer (such as tmcn), the register access is retried. as a result, it may take a longer time to access an on-chip peripheral i/o register. 3.4.11 cautions when using the v850e/ma1, the following registers must be set in the beginning. ? system wait control register (vswc) (see 3.4.10 system wait control register (vswc) ) ? clock control register (ckc) (see 9.3.4 clock control register (ckc) ) after setting vswc and ckc, set other registers if necessary. to use the external bus, initialize each register in the following sequence after setting the above registers. <1> set each pin to the control mode by setting each port-related register. <2> select a chip select space by using chip area select control register n (cscn) (n = 0, 1). <3> specify the type of memory of each chip select space by using bus cycle type configuration register n (bctn). user?s manual u14359ej5v1ud 87 chapter 4 bus control function the v850e/ma1 is provided with an exte rnal bus interface function by whic h external i/o and memories, such as rom and ram, can be connected. 4.1 features 16-bit/8-bit data bus sizing function 8-space chip select function wait function programmable wait function, through which up to 7 wait states can be inserted for each memory block external wait function via wait pin idle state insertion function bus mastership arbitration function bus hold function external device connection enabled via bus control/port alternate function pins chapter 4 bus control function user?s manual u14359ej5v1ud 88 4.2 bus control pins the following pins are used for connection to external devices. bus control pin (function when in control mode) func tion when in port mode register for port/control mode switching data bus (d0 to d15) pdl0 to pdl15 (port dl) pmcdl address bus (a0 to a15) pa l0 to pal15 (port al) pmcal address bus (a16 to a25) pah0 to pah9 (port ah) pmcah chip select (cs0 to sc7, ras1, ras3, ras4, ras6, iowr, iord) pcs0 to pcs7 (port cs) pmccs sdram sync control (sdcke, sdclk) pcd0, pcd1 (port cd) byte access control/sdram control (lbe/sdcas, ube/sdras) pcd2, pcd3 (port cd) pmccd read/write control (lcas/lwr/ldqm, ucas/uwr/udqm, rd, we, oe) pct0, pct1, pct4 to pct6 (port ct) bus cycle start (bcyst) pct7 (port ct) pmcct external wait control (wait) pcm0 (port cm) internal system clock (clkout) pcm1 (port cm) bus hold control (hldrq, hldak) pcm2, pcm3 (port cm) dram refresh control (refrq) pcm4 (port cm) self-refresh control (selfref) pcm5 (port cm) pmccm remark in the case of single-chip mode 1 and romless mo des 0 and 1, when the system is reset, each bus control pin becomes unconditionally valid. (however, d8 to d15 are valid only in single-chip mode 1 and romless mode 0.) 4.2.1 pin status during internal rom, in ternal ram, and on-chip peripheral i/o access while accessing internal rom and ram, the address bus be comes undefined, and the data bus control signals are not output and enter the high-imped ance state. the external bus control signals become inactive. while accessing on-chip peripheral i/o, the address bus outputs the address data of the on-chip peripheral i/o currently being accessed. the data bus enters the output state when write- accessing the on-chip peripheral i/o, and the high-impedanc e state when read-accessing the on -chip peripheral i/o. the external bus control signals become inactive. chapter 4 bus control function user?s manual u14359ej5v1ud 89 4.3 memory block function the 256 mb memory space is divided into memory bloc ks of 2 mb and 64 mb units. the programmable wait function and bus cycle operat ion mode can be indep endently controlled for each block. the area that can be used as progr am area is the 64 mb space of addresses 0000000h to 3ffffffh. fffffffh fffffffh on-chip peripheral i/o area (4 kb) internal ram area (12 kb note 1 ) external memory area external memory area fffc000h fe00000h fdfffffh ffff000h fffefffh fc00000h fbfffffh fa00000h f9fffffh f800000h f7fffffh c000000h bffffffh 8000000h 7ffffffh 4000000h 3ffffffh 0800000h 07fffffh 0600000h 05fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h block 1 (2 mb) block 0 (2 mb) block 2 (2 mb) block 3 (2 mb) 64 mb 64 mb block 5 (2 mb) block 6 (2 mb) block 4 (2 mb) block 7 (2 mb) 3ffffffh on-chip peripheral i/o area (4 kb) note 2 internal ram area (12 kb note 1 ) 3ffc000h 3fff000h 3ffefffh 00fffffh internal rom area (1 mb) note 3 0000000h cs7, cs6, cs5 area 3 area 2 area 1 area 0 cs6 cs4 cs1 cs3 cs2, cs1, cs0 notes 1. pd703103a, 703105a: 4 kb pd703106a, 703107a, 70f3107a: 10 kb 2. this area is access-prohibited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. 3. when in single-chip mode 1 and romless modes 0 and 1, this becomes an external memory area. when in single-chip mode 1, addresses 010 0000h to 01fffffh become an internal rom area. chapter 4 bus control function user?s manual u14359ej5v1ud 90 4.3.1 chip select control function of the 256 mb memory area, the lower 8 mb (00000 00h to 07fffffh) and the hi gher 8 mb (f800000h to fffffffh) can be divided into 2 mb memo ry blocks by chip area select contro l registers 0 and 1 (csc0, csc1) to control the chip select signal. the memory area can be effectively used by dividing it into memory blocks using the chip select control function. the priority order is described below. (1) chip area select control registers 0, 1 (csc0, csc1) these registers can be read/written in 16-bit units and become valid by setting each bit to 1. if different chip select signal outputs are set to the sa me block, the priority order is controlled as follows. csc0: cs0 > cs2 > cs1 csc1: cs7 > cs5 > cs6 if both the cs0m and cs2m bits of the csc0 register ar e set to 0, cs1 is output to the corresponding block (m = 0 to 3). similarly, if both the cs5n and cs7n bits of the csc1 register are set to 0, cs6 is output to the corresponding block (n = 0 to 3). caution write to the csc0 and csc1 registers af ter rest, and then do not change the set value. chapter 4 bus control function user?s manual u14359ej5v1ud 91 15 cs33 csc0 address fffff060h after reset 2c11h 14 cs32 13 cs31 12 cs30 11 cs23 10 cs22 9 cs21 8 cs20 7 cs13 6 cs12 5 cs11 4 cs10 3 cs03 2 cs02 1 cs01 0 cs00 15 cs43 csc1 address fffff062h after reset 2c11h 14 cs42 13 cs41 12 cs40 11 cs53 10 cs52 9 cs51 8 cs50 7 cs63 6 cs62 5 cs61 4 cs60 3 cs73 2 cs72 1 cs71 0 cs70 bit position bit name function chip select chip select is enabled by setting the csnm bit to 1. csnm cs operation cs00 cs0 output during block 0 access cs01 cs0 output during block 1 access. cs02 cs0 output during block 2 access. cs03 cs0 output during block 3 access. cs10 to cs13 setting has no meaning. cs20 cs2 output during block 0 access. cs21 cs2 output during block 1 access. cs22 cs2 output during block 2 access. cs23 cs2 output during block 3 access. cs30 to cs33 setting has no meaning. cs40 to cs43 setting has no meaning. cs50 cs5 output during block 7 access. cs51 cs5 output during block 6 access. cs52 cs5 output during block 5 access. cs53 cs5 output during block 4 access. cs60 to cs63 setting has no meaning. cs70 cs7 output during block 7 access. cs71 cs7 output during block 6 access. cs72 cs7 output during block 5 access. cs73 cs7 output during block 4 access. 15 to 0 csnm (n = 0 to 7) (m = 0 to 3) the following diagram shows the cs signal that is enabled for area 0 w hen the csc0 register is set to 0703h. when the csc0 register is set to 0703h, cs0 and cs2 ar e output to block 0 and block 1, but since cs0 has priority over cs2, cs0 is output if the addr esses of block 0 and block 1 are accessed. if the address of block 3 is accessed, both the cs03 an d cs23 bits of the csc0 register are 0, and cs1 is output. chapter 4 bus control function user?s manual u14359ej5v1ud 92 figure 4-1. example when cs c0 register is set to 0703h 3ffffffh 0600000h 05fffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h block 2 (2 mb) block 3 (2 mb) block 1 (2 mb) block 0 (2 mb) cs1 is output. cs2 is output. cs0 is output. 58 mb 2 mb 4 mb chapter 4 bus control function user?s manual u14359ej5v1ud 93 4.4 bus cycle type control function in the v850e/ma1, the following external devices ca n be connected directly to each memory block. ? sram, external rom, external i/o ? page rom ? edo dram ? sdram connected external devices are spec ified by bus cycle type configuration registers 0 and 1 (bct0 and bct1). chapter 4 bus control function user?s manual u14359ej5v1ud 94 (1) bus cycle type configuration registers 0, 1 (bct0, bct1) these registers can be read/written in 16-bit units. be sure to set bits 14, 10, 9, 6, 2, and 1 of the bct0 re gister to 0, and bits 14, 13, 10, 6, 5 and 2 of the bct1 register to 0. if they are set to 1, the operation is not guaranteed. caution write to the bct0 and bct1 registers after reset, and then do not change the set value. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the bct0 and bct1 registers is complete. however, it is possible to access external memory areas who se initialization setti ngs are complete. 15 me3 bct0 csn signal address fffff480h after reset 8888h 14 0 13 bt31 12 bt30 11 me2 10 0 9 0 8 bt20 7 me1 6 0 5 bt11 4 bt10 3 me0 2 0 1 0 0 bt00 cs3 cs2 cs1 cs0 15 me7 bct1 csn signal address fffff482h after reset 8888h 14 0 13 0 12 bt70 11 me6 10 0 9 bt61 8 bt60 7 me5 6 0 5 0 4 bt50 3 me4 2 0 1 bt41 0 bt40 cs7 cs6 cs5 cs4 bit position bit name function memory controller enable sets memory controller operation enable for each chip select. men memory controller operation enable 0 operation disabled 1 operation enabled 15, 11, 7, 3 (bct0), 15, 11, 7, 3 (bct1) men (n = 0 to 7) bus cycle type specifies the device to be connected to the csn signal. btn0 external device connected to csn signal 0 sram, external i/o 1 page rom 8, 0 (bct0), 12, 4 (bct1) btn0 (n = 0, 2, 5, 7) bus cycle type specifies the device to be connected to the csn signal. btn1 btn0 external device connected to csn signal 0 0 sram, external i/o 0 1 page rom 1 0 edo dram 1 1 sdram 13, 12, 5, 4 (bct0), 9, 8, 1, 0 (bct1) btn1, btn0 (n = 1, 3, 4, 6) chapter 4 bus control function user?s manual u14359ej5v1ud 95 4.5 bus access 4.5.1 number of access clocks the number of basic clocks necessary for ac cessing each resource is as follows. bus cycle configuration resource (bus width) instruction fetch operand data access internal rom (32 bits) 1 note 1 5 internal ram (32 bits) 1 note 2 1 notes 1. 2 for a branch instruction 2. 2 if bus access contends with a data access remark unit: clock/access chapter 4 bus control function user?s manual u14359ej5v1ud 96 4.5.2 bus sizing function the bus sizing function controls the dat a bus width for each cs space. the data bus width is specified by using the bus size configuration register (bsc). (1) bus size configuration register (bsc) this register can be read/ written in 16-bit units. be sure to set bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. write to the bsc register after reset, and then do not change the set value. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the bsc register is complete . however, it is possible to access external memory areas whose initiali zation settings are complete. 2. when the data bus width is specified as 8 bits, only the signals shown below become active. lwr: when accessing sram, external rom, or external i/o (write cycle) lcas: when accessing edo dram 15 0 bsc csn signal address fffff066h after reset note 0000h/5555h 14 bs70 13 0 12 bs60 11 0 10 bs50 9 0 8 bs40 7 0 6 bs30 5 0 4 bs20 3 0 2 bs10 1 0 0 bs00 cs3 cs2 cs1 cs0 cs4 cs5 cs6 cs7 note when in single-chip mode 0, 1: 5555h when in romless mode 0: 5555h when in romless mode 1: 0000h bit position bit name function data bus width sets the data bus width of the csn space. bsn0 data bus width of csn space 0 8 bits 1 16 bits 14, 12, 10, 8, 6, 4, 2, 0 bsn0 (n = 0 to 7) chapter 4 bus control function user?s manual u14359ej5v1ud 97 4.5.3 endian control function the endian control function can be used to set processi ng of word data in memory using either the big endian method or the little endian method for each cs space selected wi th the chip select signals (cs0 to cs7). switching of the endian method is specified using the endian configuration register (bec). caution in the following areas, the data processing method is fixed to little endian, so the setting of the bec register is invalid. ? on-chip peripheral i/o area ? internal rom area ? internal ram area ? program fetch area for external memory (1) endian configuration register (bec) this register can be read/written in 16-bit units. be sure to set bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. if they are set to 1, the operation is not guaranteed. caution write to the bec register after re set, and then do not change the set value. 15 0 bec csn signal address fffff068h after reset 0000h 14 be70 13 0 12 be60 11 0 10 be50 9 0 8 be40 7 0 6 be30 5 0 4 be20 3 0 2 be10 1 0 0 be00 cs3 cs2 cs1 cs0 cs4 cs5 cs6 cs7 bit position bit name function big endian specifies the endian method. ben0 endian control 0 little endian method 1 big endian method 14, 12, 10, 8, 6, 4, 2, 0 ben0 (n = 0 to 7) chapter 4 bus control function user?s manual u14359ej5v1ud 98 figure 4-2. big endian addresses within word 0008h 0009h 000ah 000bh 0004h 0005h 0006h 0007h 0000h 0001h 0002h 0003h 31 24 23 16 15 8 7 0 figure 4-3. little endian addresses within word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 4.5.4 big endian method usage restricti ons in nec electronics development tools (1) when using a debugger (id850) the big endian method is supported only in the memory window display. (2) when using a compiler (ca850) (a) restrictions in c language (i) there are restrictions for variables allocated to/l ocated in the big endian space, as shown below. ? union cannot be used. ? bitfield cannot be used. ? access with cast (changing access size) cannot be used. ? variables with initial values cannot be used. (ii) it is necessary to specify the following optimi zation inhibit options because optimization may cause a change in the access size. ? for global optimization part (opt850)? -wo, -xtb ? for optimization depending on model part (impr 850)? -wi, +arg_reg_opt=off, +stld_trans_opt=off the specification of the optimization inhibit options shown above is not necessary, however, if the access is not an access with cast or with masking/shifting note . note this is on the condition that a pattern that may cause the following optimization is not used. however, because it is very difficult for users to check the patterns comp letely in cases such as when several patterns are mixed (especially for optimization depending on model part), it is recommended that the optimization inhi bit options shown above be specified. chapter 4 bus control function user?s manual u14359ej5v1ud 99 [related global optimization part] ? 1-bit set using bit or int i; i ^=1; ? 1-bit clear using bit and i &= ~1; ? 1-bit not using bit xor i ^= 1; ? 1-bit test using bit and if(i & 1); [related optimization depending on model part] accessing the same variab le in a different size ? cast ? mask ? shift example int i, *ip; char c; . . . c=*((char*)ip); . . . c = 0xff & i; . . . i = (i<<24) >>24; (b) restrictions in assembly language for variables located in the big endian space, a quasi directive that secures an area of other than byte size (.hword, .word, .float, .shword) cannot be used. chapter 4 bus control function user?s manual u14359ej5v1ud 100 4.5.5 bus width the v850e/ma1 accesses on-chip pe ripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the following shows the operation for each type of access. all data is accessed in order starting from the lower order side. (1) byte access (8 bits) (a) when the data bus width is 16 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 byte data 15 8 external data bus 2n + 1 address (b) when the data bus width is 8 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data external data bus 2n address 7 0 7 0 byte data external data bus 2n + 1 address (c) when the data bus width is 16 bits (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 byte data 15 8 external data bus 2n + 1 address chapter 4 bus control function user?s manual u14359ej5v1ud 101 (d) when the data bus width is 8 bits (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data external data bus 2n address 7 0 7 0 byte data external data bus 2n + 1 address (2) halfword access (16 bits) (a) when the bus width is 16 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus 2n address 15 8 2n + 1 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 2 address (b) when the data bus width is 8 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 2n 7 0 7 0 halfword data 15 8 external data bus address 7 0 7 0 halfword data 15 8 external data bus 2n + 2 address 2n + 1 chapter 4 bus control function user?s manual u14359ej5v1ud 102 (c) when the data bus width is 16 bits (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 15 8 2n 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 2 address (d) when the data bus width is 8 bits (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus 2n address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 external data bus 2n + 2 address chapter 4 bus control function user?s manual u14359ej5v1ud 103 (3) word access (32 bits) (a) when the bus width is 16 bits (little endian) (1/2) <1> access to address (4n) 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 <2> access to address (4n + 1) 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 23 16 31 24 chapter 4 bus control function user?s manual u14359ej5v1ud 104 (a) when the bus width is 16 bits (little endian) (2/2) <3> access to address (4n + 2) 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 4n + 5 23 16 31 24 <4> access to address (4n + 3) 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 4n + 5 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 6 address 15 8 23 16 31 24 chapter 4 bus control function user?s manual u14359ej5v1ud 105 (b) when the data bus width is 8 bits (little endian) (1/2) <1> access to address (4n) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 <2> access to address (4n + 1) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 chapter 4 bus control function user?s manual u14359ej5v1ud 106 (b) when the data bus width is 8 bits (little endian) (2/2) <3> access to address (4n + 2) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 <4> access to address (4n + 3) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 6 address 15 8 23 16 31 24 chapter 4 bus control function user?s manual u14359ej5v1ud 107 (c) when the data bus width is 16 bits (big endian) (1/2) <1> access to address (4n) 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n + 3 address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 1 address 15 8 4n 23 16 31 24 <2> access to address (4n + 1) 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 3 address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 23 16 31 24 chapter 4 bus control function user?s manual u14359ej5v1ud 108 (c) when the data bus width is 16 bits (big endian) (2/2) <3> access to address (4n + 2) 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n + 5 address 15 8 4n + 4 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 3 address 15 8 4n + 2 23 16 31 24 <4> access to address (4n + 3) 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 5 address 15 8 4n + 4 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 6 address 15 8 23 16 31 24 chapter 4 bus control function user?s manual u14359ej5v1ud 109 (d) when the data bus width is 8 bits (big endian) (1/2) <1> access to address (4n) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n address 15 8 23 16 31 24 <2> access to address (4n + 1) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 4 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 chapter 4 bus control function user?s manual u14359ej5v1ud 110 (d) when the data bus width is 8 bits (big endian) (2/2) <3> access to address (4n + 2) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 5 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 <4> access to address (4n + 3) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 6 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 chapter 4 bus control function user?s manual u14359ej5v1ud 111 4.6 wait function 4.6.1 programmable wait function (1) data wait control registers 0, 1 (dwc0, dwc1) to facilitate interfacing with low-speed memory and i/os, it is possible to insert up to 7 data wa it states in the starting bus cycle for each cs space. the number of wait states can be specified by program using data wait control registers 0 and 1 (dwc0, dwc1). just after system reset, all blo cks have 7 data wait states inserted. these registers can be read/written in 16-bit units. cautions 1. the internal rom area and intern al ram area are not subject to programmable waits and ordinarily no wait access is carried out. the on-chip pe ripheral i/o area is also not subject to programmable wait states, with wait control performe d by each peripheral function only. 2. in the following cases, the settings of registers dwc0 and dwc1 are invalid (wait control is performed by each memory controller). ? page rom on-page access ? edo dram access ? sdram access 3. write to the dwc0 and dwc1 registers after reset, and then do not change the set values. also, do not access an external memo ry area other than the one for this initialization routine until the initial se tting of the dwc0 and dwc1 registers is complete. however, it is possible to access external memory areas whose initialization settings are complete. chapter 4 bus control function user?s manual u14359ej5v1ud 112 15 dwc0 csn signal address fffff484h after reset 7777h 14131211109876543210 0 dw32 dw31 dw30 0 dw22 dw21 dw20 0 dw12 dw11 dw10 0 dw02 dw01 dw00 0 dw72 dw71 dw70 0 dw62 dw61 dw60 0 dw52 dw51 dw50 0 dw42 dw41 dw40 cs3 cs2 cs1 cs0 cs7 cs6 cs5 cs4 15 dwc1 csn signal address fffff486h after reset 7777h 14131211109876543210 bit position bit name function data wait specifies the number of wait states inserted in the csn space. dwn2 dwn1 dwn0 number of wait states inserted in csn space 0 0 0 not inserted 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 14 to 12, 10 to 8, 6 to 4, 2 to 0 dwn2 to dwn0 (n = 0 to 7) chapter 4 bus control function user?s manual u14359ej5v1ud 113 (2) address setup wait control register (asc) the v850e/ma1 allows insertion of address setup wa it states before the sram /page rom cycle (the setting of the asc register in the ed o dram/sdram cycle is invalid). the number of address setup wait states can be set with the asc register for each cs space. this register can be read/written in 16-bit units. cautions 1. during an address setup wait, the wait pin-based external wait function is disabled. 2. write to the asc register after reset , and then do not ch ange the set value. 15 ac71 asc csn signal address fffff48ah after reset ffffh 14 ac70 13 ac61 12 ac60 11 ac51 10 ac50 9 ac41 8 ac40 7 ac31 6 ac30 5 ac21 4 ac20 3 ac11 2 ac10 1 ac01 0 ac00 cs3 cs2 cs1 cs0 cs4 cs5 cs6 cs7 bit position bit name function address cycle specifies the number of address setup wait states inserted before the sram/page rom cycle for each cs space. acn1 acn0 number of wait states 0 0 not inserted 0 1 1 1 0 2 1 1 3 15 to 0 acn1, acn0 (n = 0 to 7) chapter 4 bus control function user?s manual u14359ej5v1ud 114 (3) bus cycle period control register (bcp) in the v850e/ma1, the bus cycle per iod can be doubled during sram, external rom, and external i/o access. the bus cycle period is contro lled using the bcp register. when t he bcp bit of the bcp register is set to 1, the external bus operates at one ha lf the frequency of the internal system clock. the clock can be output from the busc lk pin only in the bus cycle if the ex ternal bus cycle period is set to two times that of the normal. spec ify the bus cycle period as ?double? wi th the bcp register, then set the port cm mode control register (pmccm) and port cm function control register (pfccm). this register can be read/written in 8-bit units. cautions 1. during a flyby dma transfer for sram, external rom, or external i/o, the iord and iowr signals are always output, irr espective of the ioen bit setting. in page rom and edo dram cycles, on th e other hand, the ioen bit setting has no meaning. 2. write to the bcp register after reset , and then do not change the set values. 3. if the clkout output mode is selected fo r the pcm1 pin by using the pmccm register when the bus cycle period is doubled (bcp = 1), the bus cycle is half the frequency of the internal system clock, but the same frequency as the inte rnal system clock is output from the pcm1 pin. 4. the busclk signal is asserted active onl y when the external memory is accessed. otherwise, it is kept low. address fffff48ch 7 bcp bcp 6 0 5 0 4 0 3 ioen 2 0 1 0 0 0 after reset 00h bit position bit name function bus cycle period specifies the length of the bus cycle period. bcp bus cycle period 0 normal 1 double 7 bcp iord, iowr enable specifies whether to enable/disable the operat ion of iord and iowr in sram, external rom, and external i/o cycles. ioen enable/disable iord and iowr operation 0 disables the operation of iord and iowr in sram, external rom, and external i/o cycles. 1 enables the operation of iord an d iowr in sram, external rom, and external i/o cycles. 3 ioen chapter 4 bus control function user?s manual u14359ej5v1ud 115 figure 4-4. timing example of access to s ram, external rom, and external i/o (read write) t1 t2 data data wait (input) d0 to d15 (i/o) iowr (output) lwr/lcas (output) iord (output) note uwr/ucas (output) we (output) oe (output) rd (output) bcyst (output) a0 to a25 (output) internal system clock t2 t1 csn/rasm (output) lbe (output) ube (output) busclk (output) address address note when the ioen bit of the bcp register is set to 1. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 4 bus control function user?s manual u14359ej5v1ud 116 4.6.2 external wait function when an extremely slow device, i/o, or asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (wait) for synchronization with the external device. just as with programmable waits, acce ssing internal rom, internal ram, and on-chip peripheral i/o areas cannot be controlled by external waits. the external wait signal can be input asynchronously to clkout and is sampled at the rising edge of the clkout signal immediately after the t1 and tw states of a bus cycle. if the set up/hold time in the sampling timing is not satisfied, the wait state may or ma y not be inserted in the next state. 4.6.3 relationship between programm able wait and external wait a wait cycle is inserted as the result of an or operation between the wait cycle specifi ed by the set value of the programmable wait and t he wait cycle controlled by the wait pin. wait control programmable wait wait by wait pin for example, if the timings of the pr ogrammable wait and the wait pin signal are as illustrated below, three wait states will be inserted in the bus cycle. figure 4-5. example of wait insertion t1 tw tw tw t2 clkout wait pin wait by wait pin programmable wait wait control remark the circle { indicates the sampling timing chapter 4 bus control function user?s manual u14359ej5v1ud 117 4.6.4 bus cycles in which wait functi on is valid in the v850e/ma1, the number of waits can be specified a ccording to the memory type specified for each memory block. the following shows t he bus cycles in which the wait function is valid and the re gisters used for wait setting. table 4-1. bus cycles in which wait function is valid programmable wait setting bus cycle type of wait register bit wait count wait from wait pin address setup wait asc acn1, acn0 0 to 3 ? (invalid) sram, external rom, external i/o cycles data access wait dwc0, dwc1 dwn2 to dwn0 0 to 7 (valid) address setup wait asc acn1, acn0 0 to 3 ? (invalid) off-page data access wait dwc0, dwc1 dwn2 to dwn0 0 to 7 (valid) page rom cycle on-page data access wait prc prw2 to prw0 0 to 7 (valid) ras precharge scrm rpc1m, rpc0m 1 to 3 ? (invalid) row address hold scrm rhc1m, rhc0m 0 to 3 ? (invalid) off-page data access wait scrm dac1m, dac0m 0 to 3 ? (invalid) cas precharge scrm cpc1m, cpc0m 0 to 3 ? (invalid) read access on-page data access wait scrm dac1m, dac0m 0 to 3 ? (invalid) ras precharge scrm rpc1m, rpc0m 1 to 3 ? (invalid) row address hold scrm rhc1m, rhc0m 0 to 3 ? (invalid) off-page data access wait scrm dac1m, dac0m 0 to 3 ? (invalid) cas precharge scrm cpc1m, cpc0m 1 to 3 ? (invalid) write access on-page data access wait scrm dac1m, dac0m 0 to 3 ? (invalid) ras precharge rwc rrw1, rrw0 0 to 3 ? (invalid) cbr refresh cycle ras active width rwc rcw2 to rcw0 1 to 7 ? (invalid) ras precharge rwc rrw1, rrw0 0 to 3 ? (invalid) ras active width rwc rcw2 to rcw0 1 to 7 ? (invalid) edo dram cycle cbr self-refresh cycle self-refresh release width rwc srw2 to srw0 0 to 7 ? (invalid) sdram cycle row address precharge scrm bcw1m, bcw0m 1 to 3 ? (invalid) external i/o sram data access wait dwc0, dwc1 dwn2 to dwn0 0 to 7 (valid) ras precharge scrm rpc1m, rpc0m 1 to 3 ? (invalid) row address hold scrm rhc1m, rhc0m 0 to 3 ? (invalid) off-page data access wait scrm dac1m, dac0m 0 to 3 (valid) cas precharge scrm cpc1m, cpc0m 0 to 3 ? (invalid) dram external i/o on-page data access wait scrm dac1m, dac0m 0 to 3 (valid) ras precharge scrm rpc1m, rpc0m 1 to 3 ? (invalid) row address hold scrm rhc1m, rhc0m 0 to 3 (valid) off-page data access wait scrm dac1m, dac0m 0 to 3 ? (invalid) cas precharge scrm cpc1m, cpc0m 1 to 3 (valid) dma flyby transfer cycle external i/o dram on-page data access wait scrm dac1m, dac0m 0 to 3 ? (invalid) remark n = 0 to 7, m = 1, 3, 4, 6 chapter 4 bus control function user?s manual u14359ej5v1ud 118 4.7 idle state insertion function to facilitate interfacing with low-speed me mory devices, an idle state (ti) can be inserted into the current bus cycle after the t2 state to meet the data output float delay time (t df ) on memory read access for each cs space. the bus cycle following the t2 state starts a fter the idle state is inserted. an idle state is inserted at the timing shown below. ? after read/write cycles for sram, external i/o, or external rom ? after a read cycle for page rom ? after a read cycle for edo dram (no idle state is inserted when accessing the same cs space) ? after a read cycle for sdram the idle state insertion setting c an be specified by program using the bus cycle control register (bcc). immediately after the system reset, idle state insertion is aut omatically programmed for all memory blocks. for the timing when an idle state is inserted, see the memory access timings in chapter 5. (1) bus cycle control register (bcc) this register can be read/written in 16-bit units. cautions 1. the internal ro m area, internal ram area, and on- chip peripheral i/o area are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set value. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the bcc register is comple te. however, it is possible to access external memory areas whose initializa tion settings are complete. 15 bc71 bcc csn signal address fffff488h after reset ffffh 14 bc70 13 bc61 12 bc60 11 bc51 10 bc50 9 bc41 8 bc40 7 bc31 6 bc30 5 bc21 4 bc20 3 bc11 2 bc10 1 bc01 0 bc00 cs3 cs2 cs1 cs0 cs4 cs5 cs6 cs7 bit position bit name function data cycle specifies the insertion of an idle state in the csn space. bcn1 bcn0 idle state in csn space 0 0 not inserted 0 1 1 1 0 2 1 1 3 15 to 0 bcn1, bcn0 (n = 0 to 7) chapter 4 bus control function user?s manual u14359ej5v1ud 119 4.8 bus hold function 4.8.1 function overview if the pcm2 and pcm3 pins are specified in the contro l mode, the hldak and hldrq functions become valid. if it is determined that the hldrq pin has become active (low level) as a bus mastership request from another bus master, the external address/data bus and each strobe pin ar e shifted to high impedance and then released (bus hold state). if the hldrq pin becomes inactive (high level) an d the bus mastership request is canceled, driving of these pins begins again. during the bus hold period, the internal operations of t he v850e/ma1 continue until the external memory or an on- chip peripheral i/o register is accessed. the bus hold state can be known by the hldak pin becoming active (low level). the period from when the hldrq pin becomes active (low level) to when the hldak pin becomes acti ve (low level) is at least 2 clocks. in a multiprocessor configurati on, etc., a system with multiple bus masters can be configured. state data bus width access type timing at which bus hold request cannot be acknowledged word access for even address between first and second accesses between first and second accesses word access for odd address between second and third accesses 16 bits halfword access for odd address between first and second accesses between first and second accesses between second and third accesses word access between third and forth accesses cpu bus lock 8 bits halfword access between first and second accesses read modify write access of bit manipulation instruction ? ? between read access and write access cautions 1. when an external bus master accesses edo dram during a bus hold state, make sure that the external bus master secures the ras precharge time. 2. when an external bus master accesses sdram during a bus hold state, make sure that the external bus master executes the all bank precharge command. the cpu always executes the all bank precharge command to release a bus hold state. in a bus hold state, do not allow an external bus master to change the sdram command register value. 3. the hldrq function is invalid during a r eset period. the hldak pin becomes active either immediately after or after the insertion of a 1-clock address cycle from when the reset pin is set to inactive following the simultane ous activation of the reset and hldrq pins. when a bus master other than the v850e/ma1 is extern ally connected, use the reset signal for bus arbitration at power-on. chapter 4 bus control function user?s manual u14359ej5v1ud 120 4.8.2 bus hold procedure the procedure of the bus hold function is illustrated below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests held pending <3> end of current bus cycle <4> transition to bus idle state <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> pending bus cycle start requests released <9> start of bus cycle normal state bus hold state normal state hldak (output) hldrq (input) <1> <2> <3><4> <5> <6> <7><8><9> 4.8.3 operation in power-save mode in the software stop or idle mode, the internal system clock is stopped. consequently , the bus hold state is not set since the hldrq pin cannot be acknow ledged even if it becomes active. in the halt mode, the hldak pin immediately becomes active when the hldrq pin becomes active, and the bus hold state is set. when the hldrq pin becomes inactive a fter that, the hldak pin also becomes inactive. as a result, the bus hold state is cleared and the halt mode is set again. chapter 4 bus control function user?s manual u14359ej5v1ud 121 4.8.4 bus hold timing (sram) (1) sram (when read, no idle states inserted) t1 t2 undefined iowr (output) iord (output) note 2 lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) hldrq (input) hldak (output) a0 to a25 (output) clkout (input) th th ti note 1 ti note 1 lbe (output) wait (input) d0 to d15 (i/o) data ube (output) address notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. when the ioen bit of the bcp register is set to 1. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 4 bus control function user?s manual u14359ej5v1ud 122 (2) sram (when written, three idle states inserted) t1 t2 undefined iowr (output) note 3 iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) hldrq (input) hldak (output) a0 to a25 (output) clkout (input) th th ti note 1 ti note 1 ti note 1 ti note 2 ti note 2 lbe (output) wait (input) d0 to d15 (i/o) ube (output) address data notes 1. this idle state (ti) is inserted by means of a bcc register setting. 2. this idle state (ti) is independ ent of the bcc register setting. 3. when the ioen bit of the bcp register is set to 1. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 4 bus control function user?s manual u14359ej5v1ud 123 4.8.5 bus hold timing (edo dram) (1) edo dram (when read, no idle states inserted) trpw note 1 t1 iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) hldrq (input) hldak (output) a0 to a25 (output) clkout (input) te th t2 th ti note 3 wait (input) d0 to d15 (i/o) row address column address undefined note 2 data notes 1. trpw is always insert ed for 1 or more cycles. 2. this timing applies when in the ras hold mode. 3. this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 4. timing from dram access to bus hold state. chapter 4 bus control function user?s manual u14359ej5v1ud 124 (2) edo dram (when read, thr ee idle states inserted) trpw note 1 t1 iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) hldrq (input) hldak (output) a0 to a25 (output) clkout (input) te th t2 th ti note 4 ti note 3 wait (input) d0 to d15 (i/o) row address column address undefined note 2 data notes 1. trpw is always insert ed for 1 or more cycles. 2. this timing applies when in the ras hold mode. 3. this idle state (ti) is inserted by means of a bcc register setting. the number of idle states (ti) to be inserted depends on the timing of bus hold request acknowledgement. 4. this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 4. timing from dram access to bus hold state. chapter 4 bus control function user?s manual u14359ej5v1ud 125 (3) edo dram (when written) trpw note 1 t1 iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) hldrq (input) hldak (output) a0 to a25 (output) clkout (input) te th t2 th ti note 3 wait (input) d0 to d15 (i/o) row address column address undefined note 2 data notes 1. trpw is always insert ed for 1 or more cycles. 2. this timing applies when in the ras hold mode. 3. this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 4. timing from dram access to bus hold state. chapter 4 bus control function user?s manual u14359ej5v1ud 126 (4) edo dram (when written, when bus hold request acknowledged during on-page access) trpw note 1 tcpw note 1 trpw note 1 off-page cycle t1 iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) hldrq (input) hldak (output) a0 to a25 (output) clkout (input) tb t2 th th ti note 2 ti note 2 wait (input) d0 to d15 (i/o) row address column address column address undefined data data notes 1. trpw and tcpw are always inserted for 1 or more cycles. 2. this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 4. timing from dram access to bus hold state. chapter 4 bus control function user?s manual u14359ej5v1ud 127 4.8.6 bus hold timing (sdram) (1) sdram (when read, latency = 2, no idle states inserted) tpre note 2 tw tact d0 to d15 (i/o) we (output) oe (output) rd (output) sdcas (output) sdras (output) csn (output) bcyst (output) a0 to a9 (output) a10 (output) bank address (output) sdclk (output) tread tlate tbcw tw tlate th th ti note 1 ti note 1 hldrq (input) hldak (output) note 3 (output) sdcke (output) ldqm (output) udqm (output) bcw address address address column address address data bank address row address row address undefined undefined undefined undefined h notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. the all bank precharge command is always executed. 3. addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 chapter 4 bus control function user?s manual u14359ej5v1ud 128 (2) sdram (when read, latency = 2, three idle states inserted) tpre note 3 tw tact d0 to d15 (i/o) we (output) oe (output) rd (output) sdcas (output) sdras (output) csn (output) bcyst (output) a0 to a9 (output) a10 (output) bank address (output) sdclk (output) tread tlate tlate tbcw tw th th ti note 1 ti note 1 ti note 1 ti note 2 ti note 2 hldrq (input) hldak (output) note 4 (output) sdcke (output) ldqm (output) udqm (output) h bcw address address address address bank address row address row address column address undefined undefined undefined undefined data notes 1. this idle state (ti) is inserted by means of a bcc register setting. 2. this idle state (ti) is independ ent of the bcc register setting. 3. the all bank precharge command is always executed. 4. addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 chapter 4 bus control function user?s manual u14359ej5v1ud 129 (3) sdram (when written) tpre note 2 tw tact d0 to d15 (i/o) we (output) oe (output) rd (output) sdcas (output) sdras (output) csn (output) bcyst (output) a0 to a9 (output) a10 (output) bank address (output) sdclk (output) twpre twe tbcw twr tw th th ti note 1 ti note 1 hldrq (input) hldak (output) note 3 (output) sdcke (output) ldqm (output) udqm (output) h address address address address bank address row address row address column address undefined undefined undefined undefined data bcw notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. the all bank precharge command is always executed. 3. addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 chapter 4 bus control function user?s manual u14359ej5v1ud 130 (4) sdram (when written, when bus hold request ackno wledged during on-page access) tpre note 2 tw tact d0 to d15 (i/o) we (output) oe (output) rd (output) sdcas (output) sdras (output) csn (output) bcyst (output) a0 to a9 (output) a10 (output) bank address (output) sdclk (output) twpre twe tbcw twr twr tw th th ti note 1 ti note 1 hldrq (input) hldak (output) note 3 (output) sdcke (output) ldqm (output) udqm (output) h address address bank address row address undefined undefined undefined undefined data data bcw address address address row address column address column address notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. the all bank precharge command is always executed. 3. addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 chapter 4 bus control function user?s manual u14359ej5v1ud 131 4.9 bus priority order there are five external bus cycles: bus hold, instructio n fetch, operand data access, dma cycle, and refresh cycle. in order of priority, bus hold is t he highest, followed by the refresh cycle, dma cycle, operand data access, and instruction fetch, in that order. an instruction fetch may be inserted between a read acce ss and write access during a read modify write access. also, an instruction fetch may be inserted between bus accesses when the cpu bus is locked. table 4-2. bus priority order priority order external bus cycle bus master bus hold external device refresh cycle dram controller dma cycle dma controller operand data access cpu high low instruction fetch cpu 4.10 boundary operation conditions 4.10.1 program space (1) branching to the on-chip peripheral i/o area or successive fetches from the internal ram area to the on-chip peripheral i/o area ar e prohibited. if the above is perf ormed (branching or successive fetch), undefined data is fetched, and fetching from the external memory is not performed. (2) if a branch instruction exists at the upper limit of the internal ram area, a prefetch operation (invalid fetch) that straddles over the on-chip peripheral i/o area does not occur. 4.10.2 data space the v850e/ma1 is provided with an address misalign function. through this function, regardless of the data format (wor d or halfword), data can be allocated to all addresses. however, in the case of word data an d halfword data, if the data is not s ubject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop. (1) in the case of halfword-length data access when the address?s lsb is 1, a byte-len gth bus cycle will be generated 2 times. (2) in the case of word-length data access (a) when the address?s lsb is 1, bus cycles will be generated in the order of byte-length bus cycle, halfword-length bus cycle, an d byte-length bus cycle. (b) when the address?s lower 2 bits are 10, a halfword-length bus cycle will be generated 2 times. user?s manual u14359ej5v1ud 132 chapter 5 memory access control function 5.1 sram, external rom, external i/o interface 5.1.1 features ? sram is accessed in a minimum of 2 states. ? up to 7 states of programmable data waits can be inserted by setting the dwc0 and dwc1 registers. ? data wait can be controlled via wait pin input. ? up to 3 idle states can be inserted after a read/write cycle by setting the bcc register. ? up to 3 address setup wait states can be inserted by setting the asc register. ? dma flyby transfer can be activated (sram external i/o, external i/o sram) chapter 5 memory access control function user?s manual u14359ej5v1ud 133 5.1.2 sram connection examples of connection to sram are shown below. figure 5-1. examples of connection to sram (1/2) (a) when data bus width is 8 bits a0 to a16 d1 to d8 1 mb sram (128 kwords 8 bits) cs oe we a1 to a17 d0 to d7 csn rd lwr d8 to d15 v850e/ma1 uwr a0 to a16 d1 to d8 1 mb sram (128 kwords 8 bits) cs oe we (b) when data bus width is 16 bits 2 mb sram (256 kwords 16 bits) a1 to a17 a0 to a16 v850e/ma1 d0 to d15 d1 to d16 csn cs lwr uwr uwr lbe lbe lbe ube ube rd oe we remark n = 0 to 7 chapter 5 memory access control function user?s manual u14359ej5v1ud 134 figure 5-1. examples of connection to sram (2/2) (c) mixture of sram (256 kwords 16 bits) and sdram (1 mword 16 bits) a0 to a16 d1 to d16 2 mb sram (256 kwords 16 bits) cs oe we lbe ube v850e/ma1 a0 to a11 a12, a13 dq0 to dq15 64 mb sdram (1 mword 16 bits 4 banks) cs ldqm udqm we cke clk ras cas a1 to a17, a21, a22 d0 to d15 csn rd ldqm/lwr udqm/uwr a1 to a12 a21 note , a22 we sdcke sdclk sdras/ube sdcas/lbe csm a1 to a17 note the address signals used depend on the sdram model. remark n = 0 to 7, m = 1, 3, 4, 6 (n m) chapter 5 memory access control function user?s manual u14359ej5v1ud 135 5.1.3 sram, external rom, external i/o access figure 5-2. sram, external rom, external i/o access timing (1/6) (a) when read t1 t2 address data wait (input) d0 to d15 (i/o) iowr (output) iord (output) note lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) lbe (output) ube (output) bcyst (output) a0 to a25 (output) clkout (output) data address tw t2 t1 note when the ioen bit of the bcp register is set to 1. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 136 figure 5-2. sram, external rom, external i/o access timing (2/6) (b) when read (address setup wait, idle state insertion) tasw t1 address data wait (input) d0 to d15 (i/o) iowr (output) iord (output) note lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) ti t2 lbe (output) ube (output) note when the ioen bit of the bcp register is set to 1. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 137 figure 5-2. sram, external rom, external i/o access timing (3/6) (c) when written t1 t2 address data wait (input) d0 to d15 (i/o) iowr (output) note iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) bcyst (output) a0 to a25 (output) clkout (output) data address tw t2 t1 csn/rasm (output) lbe (output) ube (output) note when the ioen bit of the bcp register is set to 1. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 138 figure 5-2. sram, external rom, external i/o access timing (4/6) (d) when written (address set up wait, idle state insertion) tasw t1 address data wait (input) d0 to d15 (i/o) iowr (output) note iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) bcyst (output) a0 to a25 (output) clkout (output) ti t2 csn/rasm (output) lbe (output) ube (output) note when the ioen bit of the bcp register is set to 1. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 139 figure 5-2. sram, external rom, external i/o access timing (5/6) (e) for read write operation t1 t2 address address data data wait (input) d0 to d15 (i/o) iowr (output) note lwr/lcas (output) iord (output) note uwr/ucas (output) we (output) oe (output) rd (output) bcyst (output) a0 to a25 (output) clkout (output) t2 t1 csn/rasm (output) lbe (output) ube (output) note when the ioen bit of the bcp register is set to 1. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 140 figure 5-2. sram, external rom, external i/o access timing (6/6) (f) for write read operation t1 t2 data wait (input) d0 to d15 (i/o) iowr (output) note lwr/lcas (output) iord (output) note uwr/ucas (output) we (output) oe (output) rd (output) bcyst (output) a0 to a25 (output) clkout (output) t2 t1 csn/rasm (output) lbe (output) ube (output) data address address note when the ioen bit of the bcp register is set to 1. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 141 5.2 page rom controller (romc) the page rom controller (romc) is provided for a ccessing rom (page rom) with a page access function. addresses are compared with the immediately preceding bus cycle and wait control fo r normal access (off-page) and page access (on-page) is executed. this controll er can handle page widths from 8 to 128 bytes. 5.2.1 features ? direct connection to 8-bit/16-bit page rom supported ? for 16-bit bus width: 4/8/16/32/64-word page access supported for 8-bit bus width: 8/16/32/6 4/128-word page access supported ? page rom is accessed in a minimum of 2 states. ? on-page judgment function ? addresses to be compared can be changed by setting the prc register. ? up to 7 states of programmable data waits can be inserted during an on-page cycle by setting the prc register. ? up to 7 states of programmable data waits can be inse rted during an off-page cycle by setting the dwc0 and dwc1 registers. ? waits can be controlled via wait pin input. ? dma flyby cycle can be activated (page rom external i/o) chapter 5 memory access control function user?s manual u14359ej5v1ud 142 5.2.2 page rom connection examples of connection to page rom are shown below. figure 5-3. examples of connection to page rom (a) when data bus width is 16 bits a0 to a19 o1 to o16 ce oe 16 mb page rom (1 mword 16 bits) a1 to a20 d0 to d15 csn rd v850e/ma1 (b) when data bus width is 8 bits a0 to a20 o1 to o8 ce oe 16 mb page rom (2 mwords 8 bits) a1 to a21 d0 to d7 csn rd d8 to d15 v850e/ma1 a0 to a20 o1 to o8 ce oe 16 mb page rom (2 mwords 8 bits) remark n = 0 to 7 chapter 5 memory access control function user?s manual u14359ej5v1ud 143 5.2.3 on-page/off-page judgment whether a page rom cycle is on-page or off-page is jud ged by latching the address of the previous cycle and comparing it with the addre ss of the current cycle. through the page rom configuration register (prc), acco rding to the configuration of the connected page rom and the number of continuously readable bits, one of the addresses (a3 to a6) is set as the masking address (no comparison is made). figure 5-4. on-page/off-page judgmen t during page rom connection (1/2) (a) in case of 16 mb (1 m 16 bits) page rom (4-word page access) a25 a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a25 a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a2 a1 a1 a0 a0 internal address latch (immediately preceding address) v850e/ma1 address output page rom address a19 off-page address on-page address continuous reading possible: 16-bit data bus width 4 words a6 a5 a4 a3 a2 ma6 0 ma5 0 ma4 0 ma3 0 prc register setting comparison chapter 5 memory access control function user?s manual u14359ej5v1ud 144 figure 5-4. on-page/off-page judgmen t during page rom connection (2/2) (b) in case of 16 mb (1 m 16 bits) page rom (8-word page access) a25 a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a25 a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a2 a1 a1 a0 a0 internal address latch (immediately preceding address) v850e/ma1 address output page rom address a19 off-page address on-page address continuous reading possible: 16-bit data bus width 8 words a6 a5 a4 a3 a2 ma6 0 ma5 0 ma4 0 ma3 1 prc register setting comparison ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (c) in case of 32 mb (2 m 16 bits) page rom (16-word page access) a25 a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a25 a24 a23 a22 a21 a20 a7 a6 a5 a4 a3 a2 a1 a1 a0 a0 internal address latch (immediately preceding address) v850e/ma1 address output page rom address a19 off-page address on-page address continuous reading possible: 16-bit data bus width 16 words a6 a5 a4 a3 a2 ma6 0 ma5 0 ma4 1 ma3 1 prc register setting comparison ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 5 memory access control function user?s manual u14359ej5v1ud 145 5.2.4 page rom configuration register (prc) this register is used to set the address comparison width and the number of wait states to be inserted in the on- page cycle. the masking address (no comparison is made) out of t he addresses (a3 to a6) corresponding to the configuration of the connected page rom and the number of bits that can be read continuously , as well as the number of waits corresponding to the internal system clock, are set. this register can be read/written in 16-bit units. caution write to the prc register after reset, an d then do not change the set value. also, do not access an external memory area other than the one for this initializat ion routine until the initial setting of the prc register is comple te. however, it is possible to access external memory areas whose initiali zation settings are complete. 15 0 prc address fffff49ah after reset 7000h 14 prw2 13 prw1 12 prw0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ma6 2 ma5 1 ma4 0 ma3 bit position bit name function page-rom on-page wait control sets the number of waits correspondi ng to the internal system clock. the number of waits set by these bits is in serted only for on-page access. for off-page access, the waits set by registers dwc0 and dwc1 are inserted. prw2 prw1 prw0 number of inserted wait cycles 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 14 to 12 prw2 to prw0 mask address each respective address (a6 to a3) correspondi ng to ma6 to ma3 is masked (by 1). the masked address is not subject to compar ison during on/off-page judgment, and is set according to the number of continuously readable bits. ma6 ma5 ma4 ma3 number of continuously readable bits 0 0 0 0 4 words 16 bits (8 words 8 bits) 0 0 0 1 8 words 16 bits (16 words 8 bits) 0 0 1 1 16 words 16 bits (32 words 8 bits) 0 1 1 1 32 words 16 bits (64 words 8 bits) 1 1 1 1 64 words 16 bits (128 words 8 bits) other than above setting prohibited 3 to 0 ma6 to ma3 chapter 5 memory access control function user?s manual u14359ej5v1ud 146 5.2.5 page rom access figure 5-5. page rom access timing (1/4) (a) when read (halfword/word access with 8-bit bus width or word access with 16-bit bus width) t1 tw off-page address data wait (input) d0 to d15 (i/o) d0 to d7 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) data note on-page address to1 to2 t2 note when accessing a word boundary with 8-bit bus width. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 147 figure 5-5. page rom access timing (2/4) (b) when read (byte access with 8-bit bus width or byte/half- word access with 16-bit bus width) t1 tw off-page address data wait (input) d0 to d15 (i/o) d0 to d7 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) data on-page address to1 to2 t2 remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 148 figure 5-5. page rom access timing (3/4) (c) when read (address setup wait, idle state insertion) (halfword/word access with 8- bit bus width or word access with 16-bit bus width) tasw t1 off-page address data wait (input) d0 to d15 (i/o) d0 to d7 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) data on-page address tasw to1 to2 ti t2 remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 149 figure 5-5. page rom access timing (4/4) (d) when read (address setup wait, idle state insertion) (byte access with 8-bit bus width or byte/halfword access with 16-bit bus width) tasw t1 off-page address data wait (input) d0 to d15 (i/o) d0 to d7 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) data on-page address tasw to1 to2 ti t2 remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 150 5.3 dram controller (edo dram) 5.3.1 features generates the ras, lcas, and ucas signals can be connected directly to edo dram. supports the ras hold mode. 4 types of dram can be assigned to 4 memory block spaces. supports 2cas type dram. row and column address multiplex widths can be changed. waits (0 to 3 waits) can be inserted at the following timings: row address precharge wait row address hold wait data access wait column address precharge wait supports cbr refresh and cbr self-refresh. chapter 5 memory access control function user?s manual u14359ej5v1ud 151 5.3.2 dram connection examples of connection to dram are shown below. figure 5-6. examples of connection to dram (a) when dram is 64 mb (4 m 16 bits) a0 to a11 i/o1 to i/o16 ras lcas ucas we oe 64 mb dram (4 mwords 16 bits) a1 to a12 d0 to d15 rasn lcas ucas we oe v850e/ma1 (b) when dram is 16 mb (2 m 8 bits) a0 to a11 i/o1 to i/o8 ras cas we oe 16 mb dram (2 mwords 8 bits) a1 to a12 d0 to d7 rasn lcas we oe d8 to d15 v850e/ma1 a0 to a11 i/o1 to i/o8 ras cas we oe 16 mb dram (2 mwords 8 bits) ucas remark n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 152 5.3.3 address mult iplex function depending on the value of the daw0n and daw1n bits in dram configuration register n (scrn), the row address and column address outputs in the dram cycle are multiplexed as shown in figure 5-7 (n = 1, 3, 4, 6). in figure 5-7, a0 to a25 show the addresses output from the cpu and a0 to a25 show the address pins of the v850e/ma1. for example, when daw1n and daw0n = 11, it indicates that a12 to a22 are output as row addresses and a1 to a11 are output as column addresses from the address pins (a1 to a11). figure 5-7. row address/column address output a15 a15 a14 a25 a13 a24 a25 to a18 address pin a25 to a18 row address (daw1n, daw0n = 11) a17 a17 a16 a16 a12 a23 a11 a22 a10 a21 a9 a20 a8 a19 a7 a18 a6 a17 a5 a16 a4 a15 a3 a14 a2 a13 a1 a12 a0 a11 a25 a24 a23 a25 to a18 row address (daw1n, daw0n = 10) a17 a16 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a24 a23 a22 a25 to a18 row address (daw1n, daw0n = 01) a17 a25 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a23 a22 a21 a25 to a18 row address (daw1n, daw0n = 00) a25 a24 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a15 a14 a13 a25 to a18 column address a17 a16 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 remark n = 1, 3, 4, 6 table 5-1 shows the relationship between the dram that can be connected and the address multiplex width. the dram space differs according to the dram that is connected, as shown in table 5-1. table 5-1. example of dram and address multiplex width dram capacity (bits) and configuration address multiplex width 256 k 1 m 4 m 16 m 64 m dram space note (bytes) 8 bits (daw1n, daw0n = 00) 64 k 4 ? ? ? ? 128 k ? 256 k 4 256 k 16 ? ? 512 k ? ? 512 k 8 ? ? 1 m 9 bits (daw1n, daw0n = 01) ? ? ? ? 4 m 16 8 m ? ? 1 m 4 1 m 16 ? 2 m ? ? ? 2 m 8 ? 4 m 10 bits (daw1n, daw0n = 10) ? ? ? ? 4 m 16 8 m 11 bits (daw1n, daw0n = 11) ? ? ? 4 m 4 ? 8 m note when the data bus width is 16 bits remark n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 153 5.3.4 dram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) these registers are used to set the type of dram to be con nected. scrn corresponds to csn (n = 1, 3, 4, 6). for example, to connect dram to cs1, set scr1. thes e registers can be read/written in 16-bit units. be sure to set bits 14 and 5 to 0. if they are set to 1, the oper ation is not guaranteed. cautions 1. if the object of access is a dram area, the wait set by registers dwc0 and dwc1 becomes invalid. in this case, waits are controlle d by registers scr1, scr3, scr4, and scr6. 2. write to the scr1, scr3, scr4, and scr6 re gisters after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initialization routine until the initial setting s of the scr1, scr3, scr4, and scr6 registers are complete. however, it is possible to access external me mory areas whose initialization settings are complete. (1/3) 15 pae11 scr1 address fffff4a4h after reset 3fc1h 14 0 13 rpc11 12 rpc01 11 rhc11 10 rhc01 9 dac11 8 dac01 7 cpc11 6 cpc01 5 0 4 rhd1 3 aso11 2 aso01 1 daw11 0 daw01 pae13 scr3 fffff4ach 3fc1h 0 rpc13 rpc03 rhc13 rhc03 dac13 dac03 cpc13 cpc03 0 rhd3 aso13 aso03 daw13daw03 pae14 scr4 fffff4b0h 3fc1h 0 rpc14 rpc04 rhc14 rhc04 dac14 dac04 cpc14 cpc04 0 rhd4 aso14 aso04 daw14daw04 pae16 scr6 fffff4b8h 3fc1h 0 rpc16 rpc06 rhc16 rhc06 dac16 dac06 cpc16 cpc06 0 rhd6 aso16 aso06 daw16daw06 bit position bit name function dram on-page access mode control sets the on-page access cycle. pae1n access mode 0 on-page access disabled 1 on-page access enabled 15 pae1n (n = 1, 3, 4, 6) row address pre-charge control specifies the number of wait states inserted as row address precharge time. rpc1n rpc0n number of wait states inserted 0 0 1 (at least 1 wait is always inserted) 0 1 1 1 0 2 1 1 3 13, 12 rpc1n, rpc0n (n = 1, 3, 4, 6) chapter 5 memory access control function user?s manual u14359ej5v1ud 154 (2/3) bit position bit name function row address hold wait control specifies the number of wait states inserted as row address hold time. rhc1n rhc0n number of wait states inserted 0 0 0 0 1 1 1 0 2 1 1 3 11, 10 rhc1n, rhc0n (n = 1, 3, 4, 6) data access programmable wait control specifies the number of wait states insert ed as data access time during dram access. dac1n dac0n number of wait states inserted 0 0 0 0 1 1 1 0 2 1 1 3 9, 8 dac1n, dac0n (n = 1, 3, 4, 6) column address pre-charge control specifies the number of wait states inserted as column address precharge time. cpc1n cpc0n number of wait states inserted 0 0 0 (at least 1 wait is always inserted during on-page write access) 0 1 1 1 0 2 1 1 3 7, 6 cpc1n, cpc0n (n = 1, 3, 4, 6) 4 rhdn (n = 1, 3, 4, 6) ras hold disable sets the ras hold mode. if access to dram during on-page operati on is not continuous and another space is accessed midway, the rasn signal is maintained in the active state (low level) during the time the other space is being accessed in the ras hold mode. in this way, if access continues in the same dram row address fo llowing access of the other space, on-page operation can be continued. 0: ras hold mode enabled 1: ras hold mode disabled chapter 5 memory access control function user?s manual u14359ej5v1ud 155 (3/3) bit position bit name function address shift width on-page control this sets the address shift width during on-page judgment. when the external data bus width is 8 bits: set aso1n, aso0n = 00b when the external data bus width is 16 bits: set aso1n, aso0n = 01b aso1n aso0n address shift width 0 0 0 (data bus width: 8 bits) 0 1 1 (data bus width: 16 bits) 1 0 setting prohibited 1 1 setting prohibited 3, 2 aso1n, aso0n (n = 1, 3, 4, 6 dram address multiplex width control this sets the address multiplex width (refer to 5.3.3 address multiplex function ). daw1n daw0n address multiplex width 0 0 8 bits 0 1 9 bits 1 0 10 bits 1 1 11 bits 1, 0 daw1n, daw0n (n = 1, 3, 4, 6) chapter 5 memory access control function user?s manual u14359ej5v1ud 156 5.3.5 dram access figure 5-8. edo dram access timing (1/5) (a) read timing (when no waits are inserted) trpw note 1 t1 row address data data data wait (input) d0 to d15 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) tb tb t2 te column address column address column address note 2 notes 1. trpw is always inserted for 1 or more cycles. 2. when a bus cycle accessing another cs space or a write cycle accessing the same cs space follows this read cycle. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 157 figure 5-8. edo dram access timing (2/5) (b) read timing (when trhw and tw are inserted) trpw note 1 t1 wait (input) d0 to d15 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) t2 tw trhw tb te tw row address column address column address data data note 2 notes 1. trpw is always insert ed for 1 or more cycles. 2. when a bus cycle accessing another cs space or a write cycle accessing the same cs space follows this read cycle. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 158 figure 5-8. edo dram access timing (3/5) (c) read timing (when two idle states are inserted) trpw note t1 wait (input) d0 to d15 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) t2 tw trhw tcpw note tw te ti ti t1 tb row address column address column address data data note trpw and tcpw are always inserted for 1 or more cycles. remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 159 figure 5-8. edo dram access timing (4/5) (d) write timing (when no waits are inserted) trpw note 1 t1 row address data wait (input) d0 to d15 (i/o) (during read to write) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) tcpw note 1 tb t2 tcpw note 1 te tb column address column address column address data data data data d0 to d15 (i/o) (during read to write) data data data note 2 notes 1. trpw and tcpw are always inserted for 1 or more cycles. 2. when a bus cycle accessing another cs space or a read cycle accessing the same cs space follows this write cycle. remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 160 figure 5-8. edo dram access timing (5/5) (e) write timing (when tr hw and tw are inserted) trpw note 1 t1 row address data wait (input) t2 tw trhw tcpw note 1 tw te tb d0 to d15 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) column address column address data note 2 notes 1. trpw and tcpw are always inserted for 1 or more cycles. 2. when a bus cycle accessing another cs space or a read cycle accessing the same cs space follows this write cycle. remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 161 5.3.6 refresh control function the v850e/ma1 can generate the cbr (cas-before-ras) re fresh cycle. the refresh cycle is set with refresh control registers 1, 3, 4, and 6 (rfs1, rfs3, rfs4, rfs6). the rfsn regist er corresponds to csn (n = 1, 3, 4, 6). for example, to connect dram to cs1, set rfs1. when another bus master occupies the external bus, the dram controller cannot occupy the external bus. in this case, the dram controller issues a refresh request to the bus master by changing the refrq signal to active (low level). during a refresh operation, the address bus retains t he state it was in just before the refresh cycle. (1) refresh control registers 1, 3, 4, 6 (rfs1, rfs3, rfs4, rfs6) these registers are used to enable or disable a refresh and set the refresh interval. the refresh interval is determined by the following calculation formula. refresh interval ( s) = refresh count clock (t rcy ) interval factor the refresh count clock and interval factor are determined by the renn bit and rin5n to rin0n bits, respectively, of the rfsn register. note that n corresponds to the register number (1, 3, 4, 6) of dram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6). these registers can be read/written in 16-bit units. caution write to the rfs1, rfs3, rfs4, and rfs6 registers after reset, and then do not change the set values. also, do not access an external memory area ot her than the one for this initialization routine until the initial settings of the rfs1, rfs3, rfs4, and rfs6 registers are complete. however, it is possible to access external me mory areas whose initialization settings are complete. chapter 5 memory access control function user?s manual u14359ej5v1ud 162 15 ren1 rfs1 address fffff4a6h after reset 0000h 14 0 13 0 12 0 11 0 10 0 9 rcc11 8 rcc01 7 0 6 0 5 rin51 4 rin41 3 rin31 2 rin21 1 rin11 0 rin01 ren3 rfs3 fffff4aeh 0000h 00000 rcc13 rcc03 00 rin53 rin43 rin33 rin23 rin13 rin03 ren4 rfs4 fffff4b2h 0000h 00000 rcc14 rcc04 00 rin54 rin44 rin34 rin24 rin14 rin04 ren6 rfs6 fffff4bah 0000h 00000 rcc16 rcc06 00 rin56 rin46 rin36 rin26 rin16 rin06 bit position bit name function 15 renn (n = 1, 3, 4, 6) refresh enable specifies whether cbr refresh is enabled or disabled. 0: refresh disabled 1: refresh enabled refresh count clock specifies the refresh count clock (t rcy ) rcc1n rcc0n refresh count clock (t rcy ) 0 0 32/f xx 0 1 128/f xx 1 0 256/f xx 1 1 setting prohibited 9, 8 rcc1n, rcc0n (n = 1, 3, 4, 6) refresh interval sets the interval factor of the interval timer for the generation of the refresh timing. rin5n rin4n rin3n rin2n rin1n rin0n interval factor 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : 1 1 1 1 1 1 64 5 to 0 rin5n to rin0n (n = 1, 3, 4, 6) remark f xx : internal system clock chapter 5 memory access control function user?s manual u14359ej5v1ud 163 table 5-2. interval factor setting examples interval factor value notes 1, 2 specified refresh interval value ( s) refresh count clock (t rcy ) f xx = 20 mhz f xx = 33 mhz f xx = 50 mhz 32/f xx 4 (6.4) 8 (7.8) 12 (7.7) 128/f xx 1 (6.4) 2 (7.8) 5 (7.7) 7.8 256/f xx ? 1 (7.8) 1 (5.1) 32/f xx 9 (14.4) 16 (15.5) 24 (15.4) 128/f xx 2 (12.8) 4 (15.5) 6 (15.4) 15.6 256/f xx 1 (12.8) 2 (15.5) 3 (15.4) 32/f xx 19 (30.4) 32 (31.0) 48 (30.7) 128/f xx 4 (25.6) 8 (31.0) 12 (30.7) 31.2 256/f xx 2 (25.6) 4 (31.0) 6 (30.7) 32/f xx 39 (62.4) 64 (62.1) ? 128/f xx 9 (57.6) 16 (62.1) 24 (61.4) 62.5 256/f xx 4 (51.2) 8 (62.1) 12 (61.4) 128/f xx 19 (121.6) 32 (124.1) 48 (122.9) 125 256/f xx 9 (115.2) 16 (124.1) 24 (122.9) 128/f xx 39 (249.6) 64 (248.2) ? 250 256/f xx 19 (243.2) 32 (248.2) 48 (245.8) notes 1. the interval factor is set by bits rin0n to rin5n of the rfsn register (n = 1, 3, 4, 6). 2. the values in parentheses are the calc ulated values for the refresh interval ( s). refresh interval ( s) = refresh count clock (t rcy ) interval factor remark f xx : internal system clock (2) refresh wait c ontrol register (rwc) this register specifies the nu mber of wait states insert ed during the refresh cycle. this register can be read/written in 8-bit units. caution write to the rwc register after reset, a nd then do not change the set value. also, do not access an external memory area other than the one for this initializat ion routine until the initial setting of the rwc register is comple te. however, it is possible to access external memory areas whose initiali zation settings are complete. chapter 5 memory access control function user?s manual u14359ej5v1ud 164 address fffff49eh 7 rrw1 rwc 6 rrw0 5 rcw2 4 rcw1 3 rcw0 2 srw2 1 srw1 0 srw0 after reset 00h bit position bit name function refresh ras wait control specifies the number of wait states inserted as hold time for the rasm signal's high level width during cbr refresh (m = 1, 3, 4, 6). rrw1 rrw0 number of inserted wait states 0 0 0 0 1 1 1 0 2 1 1 3 7, 6 rrw1, rrw0 refresh cycle wait control specifies the number of wait states inserted as hold time for the rasm signal's low level width during cbr refresh (m = 1, 3, 4, 6). rcw2 rcw1 rcw0 number of inserted wait states 0 0 0 1 (at least 1 wait is always inserted) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 5 to 3 rcw2 to rcw0 self-refresh release wait control specifies the number of wait states inserted as cbr self-refresh release time. srw2 srw1 srw0 number of inserted wait states 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 2 to 0 srw2 to srw0 chapter 5 memory access control function user?s manual u14359ej5v1ud 165 (3) refresh timing figure 5-9. cbr refresh timing t1 t2 trrw wait (input) d0 to d15 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) refrq (output) clkout (output) trcw t3 trcw note 1 t4 ti note 2 ti note 2 we (output) notes 1. the trcw cycle is always inserted for one or more clo cks, irrespective of the setting of bits rcw2 to rcw0 of the rwc register. 2. this idle state (ti) is independ ent of the bcc register setting. remark n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 166 5.3.7 self-refresh control function when transferring to the idle or software stop mode, or if the selfref signal becomes active, the dram controller generates the cbr self-refresh cycle. note that the rasn pulse width of dram must meet the specifications for dram to enable the self-refresh operation (n = 1, 3, 4, 6). cautions 1. when the transition to the self-refresh cycle is cause d by selfref signa l input, releasing the self-refresh cycle is only possible by inputti ng an inactive level to the selfref pin. 2. the internal rom and internal ram can be accessed even in th e self-refresh cycle. however, access to a peripheral i/o register or external device is held pending until the self- refresh cycle is cleared. to release the self-refresh cycle, us e one of the three methods below. (1) release by nmi input (a) in the case of self-refresh cycle in idle mode to release the self-refresh cycle, make the rasn, lcas, and ucas signals inactive (high level) immediately. (b) in the case of self-refresh cycle in software stop mode to release the self-refresh cycle, make the rasn, lcas, and ucas signals inactive (high level) after stabilizing oscillation. (2) release by intp1nm input (n = 0 to 3, m = 0 to 3) (a) in the case of self-refresh cycle in idle mode to release the self-refresh cycle, make the rasn, lcas, and ucas signals inactive (high level) immediately. (b) in the case of self-refresh cycle in software stop mode to release the self-refresh cycle, make the rasn, lcas, and ucas signals inactive (high level) after stabilizing oscillation. (3) release by reset input chapter 5 memory access control function user?s manual u14359ej5v1ud 167 figure 5-10. self-refresh timing (dram) trrw wait (input) d0 to d15 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) refrq (output) clkout (output) tsrw tsrw trcw note 2 note 1 we (output) notes 1. shown above is the case when the self-refresh cycle is started in the idle or software stop mode. if the self-refresh cycle is started by inputting t he active level of the selfref signal, clkout is output without going low. 2. the trcw cycle is always inserted for one or more clocks, irrespective of the setting of bits rcw2 to rcw0 of the rwc register. remarks 1. this timing is obtained when the bits of the rwc register have the following settings. rrw1, rrw0 = 01b: 1 wait (trrw) rcw2 to rcw0 = 001b: 1 wait (trcw) srw2 to srw0 = 001b: 1 wait (tsrw) ( double the number of wait stat es than the set value will be inserted) 2. n = 0 to 7, m = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 168 5.4 dram controller (sdram) 5.4.1 features ? burst length: 1 ? wrap type: sequential ? cas latency: 2 and 3 supported ? 4 types of sdram can be assigned to 4 memory blocks. ? row and column address multiplex widths can be changed. ? waits (0 to 3 waits) can be inserted between t he bank active command and the read/write command. ? supports cbr refresh and cbr self-refresh. 5.4.2 sdram connection an example of connection to sdram is shown below. figure 5-11. example of connection to sdram a0 to a11 a12, a13 dq0 to dq15 clk cke cs ras cas ldqm udqm we 64 mb sdram (1 mword 16 bits 4 banks) a1 to a12 a21, a22 note d0 to d15 sdclk sdcke csn sdras sdcas ldqm udqm we v850e/ma1 note the address signals to be used differ depending on the sdram product. remark n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 169 5.4.3 address multiplex function depending on the value of the saw0n and saw1n bits in sdram configuration regi ster n (scrn), the row address output in the sdram cycle is multiplexed as shown in figure 5-12 (a) (n = 1, 3, 4, 6). depending on the value of the sso0n and sso1n bits, t he column address output in the sdram cycle is multiplexed as shown in figure 5-12 (b) (n = 1, 3, 4, 6). in figures 5-12 (a) and (b), a0 to a25 indicate the addresses output from the cpu, and a0 to a25 indicate the address pins of the v850e/ma1. figure 5-12. row address/column address output (1/2) (a) row address output a15 a25 a14 a24 a13 a23 a25 to a18 address pin a25 to a18 row address (saw1n, saw0n = 10) a17 a17 a16 a16 a12 a22 a11 a21 a10 a20 a9 a19 a8 a18 a7 a17 a6 a16 a5 a15 a4 a14 a3 a13 a2 a12 a1 a11 a0 a10 a24 a23 a22 a25 to a18 row address (saw1n, saw0n = 01) a17 a25 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a23 a22 a21 a25 to a18 row address (saw1n, saw0n = 00) a25 a24 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 remark n = 1, 3, 4, 6 (b) column address output (using all bank precharge command) a15 a15 a14 a14 a13 a13 a25 to a18 address pin a25 to a18 column address (sso1n, sso0n = 00) a17 a17 a16 a16 a12 a12 a11 a11 a10 1 a9 a9 a8 a8 a7 a7 a6 a6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 a0 a15 a14 a13 a25 to a18 column address (sso1n, sso0n = 01) a17 a16 a12 1 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 remark n = 1, 3, 4, 6 (c) column address output (using register write command) a15 0 a14 0 a13 0 a25 to a18 address pin 0 column address (sso1n, sso0n = 00) a17 0 a16 0 a12 0 a11 0 a10 0 a9 0 a8 0 a7 0 a6 ltm2 a5 ltm1 a4 ltm0 a3 0 a2 0 a1 0 a0 0 000 0 column address (sso1n, sso0n = 01) 00 0 0 000 ltm2 ltm1 ltm0 00000 remark n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 170 figure 5-12. row address/column address output (2/2) (d) column address output (using read/write command) a15 a15 a14 a14 a13 a13 a25 to a18 address pin a25 to a18 column address (sso1n, sso0n = 00) a17 a17 a16 a16 a12 a12 a11 a11 a10 0 a9 a9 a8 a8 a7 a7 a6 a6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 a0 a15 a14 a13 a25 to a18 column address (sso1n, sso0n = 01) a17 a16 a12 0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 remark n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 171 (1) output of each address and connection of sdram the setting and physical address of sdram configurat ion register n (scrn), address output from the v850e/ma1, and connection of the v850e/ma1 with sdra m are explained for each data bus width (8 bits or 16 bits). (a) 8-bit data bus width here is an example of connecting 64 mb sdram (2m words x 8 bits x 4 banks) when the data bus width is 8 bits. ? setting of scrn register sso1n and sso0n bits = 00: data bus width = 8 bits raw1n and raw0n bits = 01: row address width = 12 bits saw1n and saw0n bits = 01: column address width = 9 bits ? physical address a22 and a21: bank address a20 to a9: row address a8 to a0: column address ? address output from v850e/ma1 a22 and a21: bank address a11 to a0: row address (12 bits), column address (9 bits) figure 5-13. row address and bank addres s output when active command is executed (8-bit data bus width) a9 row address bank address a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a17 a18 a19 a20 a21 a22 a23 a24 a25 figure 5-14. column address output when read/write command is executed (8-bit data bus width) a0 column address a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a1 a2 a3 a4 a5 a6 a7 a8 a9 0 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 ? connection of v850e/ma1 and sdram a22 and a21 (v850e/ma1) ba0 (a13) and ba1 (a12) (sdram) a11 to a0 (v850e/ma1) a11 to a0 (sdram) chapter 5 memory access control function user?s manual u14359ej5v1ud 172 (b) 16-bit data bus width here is an example of connecting 128 mb sdram (2m words x 16 bits x 4 banks) when the data bus width is 16 bits. ? setting of scrn register sso1n and sso0n bits = 01: data bus width = 16 bits raw1n and raw0n bits = 01: row address width = 12 bits saw1n and saw0n bits = 01: column address width = 9 bits ? physical address a23 and a22: bank address a21 to a10: row address a9 to a1: column address ? address output from v850e/ma1 a23 and a22: bank address a12 to a1: row address (12 bits), column address (9 bits) figure 5-15. row address and bank addres s output when active command is executed (16-bit data bus width) a9 row address bank address a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a17 a18 a19 a20 a21 a22 a23 a24 a25 figure 5-16. column address output when read/write command is executed (16-bit data bus width) a0 column address a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 0 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 ? connection of v850e/ma1 and sdram a23 and a22 (v850e/ma1) ba0 (a13) and ba1 (a12) (sdram) a12 to a1 (v850e/ma1) a11 to a0 (sdram) chapter 5 memory access control function user?s manual u14359ej5v1ud 173 (2) bank address output the v850e/ma1 precharges the bank to be accessed by using a bank precharge command when a row address is output immediately after the page is change d. after the bank is changed, the bank previously accessed is precharged when a column address is output . therefore, the bank is precharged both when a row address is output and when a column address is output. if the v850e/ma1 is connected with sdram as explained in 5.4.3 (1) (a) 8-bit data bus width , therefore, always connect pins that output a bank address of the v850e/ma1 (pins a22 and a21) to the b ank address pins of the sdram (a13 and a12). an example of outputting an address by the bank precharge command when the page is changed and when the bank is changed if the v850e/ma1 is connected with sdram as explained in 5.4.3 (1) (a) 8-bit data bus width is shown below. (a) when page is changed (8-bit data bus width) because the bank to be accessed is precharged, the physical address to be accessed (a25 to a9) is output from the a25 to a0 pins of the v850e/ma1. figure 5-17. address output by bank precharge comma nd when page is changed (8-bit data bus width) a9 row address bank address to be accessed a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a10 a11 a12 a13 a14 a15 a16 a17 a18 0 a20 a21 a22 a23 a24 a25 a17 a18 a19 a20 a21 a22 a23 a24 a25 (b) when bank is change d (8-bit data bus width) because the bank previously accessed is precharged, the physical address previously accessed (a25 to a9) is output from the a25 to a9 pins of the v850e/ma1. figure 5-18. address output by bank precharge comma nd when bank is changed (8-bit data bus width) a0 column address bank address previously accessed a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a1 a2 a3 a4 a5 a6 a7 a8 a9 0 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 the bit that determines the precharge mode (a10: 8-bit data bus width, a 11: 16-bit data bus width) outputs a high level when the all bank precharge co mmand is executed, and outputs a low level when another precharge command is executed. chapter 5 memory access control function user?s manual u14359ej5v1ud 174 5.4.4 sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) these registers specify the num ber of waits and the address multiplex width. scrn corresponds to csn (n = 1, 3, 4, 6). for example, to connect sdram to cs1, set scr1. these registers can be read/written in 16-bit units. cautions 1. the sdram read/write cycle is not gene rated prior to executing the power-on cycle. access sdram after waiting 20 clocks following a program write to the scr register. to write to the scr register again following access to sdram , clear the men bit of the bct0 and bct1 registers to 0, and then set it to 1 ag ain before performing access (n = 0 to 7). 2. do not execute continuous instructions to write to the scr register. be sure to insert another instruction between commands to write to the scr register. (1/2) 15 0 scr1 address fffff4a4h after reset 0000h 14 ltm21 13 ltm11 12 ltm01 11 0 10 0 9 0 8 0 7 bcw11 6 bcw01 5 sso11 4 sso01 3 raw11 2 raw01 1 saw11 0 saw01 0 scr3 fffff4ach 0000h ltm23 ltm13 ltm03 0000 bcw13 bcw03 sso13 sso03 raw13 raw03 saw13 saw03 0 scr4 fffff4b0h 0000h ltm24 ltm14 ltm04 0000 bcw14 bcw04 sso14 sso04 raw14 raw04 saw14 saw04 0 scr6 fffff4b8h 0000h ltm26 ltm16 ltm06 0000 bcw16 bcw06 sso16 sso06 raw16 raw06 saw16 saw06 bit position bit name function latency sets the cas latency value for reading. ltm2n ltm1n ltm0n latency 0 0 3 0 1 0 2 0 1 1 3 1 setting prohibited 14 to 12 ltm2n to ltm0n (n = 1, 3, 4, 6) bank active command wait control specifies the number of wait states inserted from the bank active command to a read/write command, or from the precharge command to the bank active command. bcw1n bcw0n number of wait states inserted 0 0 1 (at least 1 wait is always inserted) 0 1 1 1 0 2 1 1 3 7, 6 bcw1n, bcw0n (n = 1, 3, 4, 6) remark : don't care chapter 5 memory access control function user?s manual u14359ej5v1ud 175 (2/2) bit position bit name function sdram shift width on-page control specifies the address shift width during on-page judgment. when the external data bus width is 8 bits: set sso1n, sso0n = 00b when the external data bus width is 16 bits: set sso1n, sso0n = 01b sso1n sso0n address shift width 0 0 8 bits 0 1 16 bits 1 0 setting prohibited 1 1 setting prohibited 5, 4 sso1n, sso0n (n = 1 3, 4, 6) row address width control specifies the row address width. raw1n raw0n row address width 0 0 11 0 1 12 1 0 setting prohibited 1 1 setting prohibited 3, 2 raw1n, raw0n (n = 1, 3, 4, 6) caution memories with a row address width of 13 or above cannot be controlled. row address multiplex width control specifies the address multiplex width during sdram access. saw1n saw0n address multiplex width 0 0 8 0 1 9 1 0 10 1 1 setting prohibited 1, 0 saw1n, saw0n (n = 1, 3, 4, 6) chapter 5 memory access control function user?s manual u14359ej5v1ud 176 5.4.5 sdram access during power-on or a refresh operation, the all bank precharge command is always issued for sdram. when accessing sdram after that, therefore, the active command and read/write command are issued in that order (see <1> in figure 5-19). if a page change occurs following this, the prechar ge command, active command, and read/write command are issued in that order (see <2> in figure 5-19 ). if a bank change occurs, the active command and read/write command for the bank to be accessed next are issued in that order. following this read/write command, the precharge command for the bank that was accessed before the bank currently being accessed will be issued (see <3> in figure 5-19 ). figure 5-19. state transition of sdram access <1> <3> <2> all bank pre-charge command (power on/refresh) bank a active command bank a precharge command bank a active command bank a active command bank b active command bank b read/write command bank a read/write command bank a read/write command read/write command read/write command (on-page access) (page change) (bank change) (bank change) bank a precharge command chapter 5 memory access control function user?s manual u14359ej5v1ud 177 (1) sdram single read cycle the sdram single read cycle is a cycle for reading from sdram by executing a load instruction (ld) for the sdram area, by fetching an instruction, or by 2-cycle dma transfer. in the sdram single read cycle, the active command (act) and read command (rd) are issued for sdram in that order. during on-page access, however, on ly the read command is issued and the precharge command and active command are not issued. when a page change occurs in the same bank, the precharge command (pr) is issued before the active command. the timing to sample data is synchronized with rising of the udqm and ldqm signals. a one-state tw cycle is always inserted immediately befor e every read command, which is activated by the cpu. the number of idle states set by t he bus cycle control register (bcc) are inserted before the read cycle (no idle states are inserted, however, if bcn1 and bcn0 are 00) (n = 1, 3, 4, 6). the timing charts of the sdram single read cycle are shown below. caution when executing a write acces s to sram or external i/o afte r read accessing sdram, data conflict may occur depending on the sdram data output float delay time. in such a case, avoid data conflict by inserting an idle stat e in the sdram space via a setting in the bcc register. chapter 5 memory access control function user?s manual u14359ej5v1ud 178 figure 5-20. sdram single read cycle (1/3) (a) during off-page access (when latency = 2) tact act rd tw tread tlate tlate data address address address address column address row address address address bank address address row address sdclk (output) bcyst (output) sdcke (output) h command sdras (output) sdcas (output) csn (output) we (output) ldqm (output) udqm (output) note (output) bank address (output) a10 (output) a0 to a9 (output) d0 to d15 (i/o) off-page note addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 179 figure 5-20. sdram single read cycle (2/3) (b) during off-page access (whe n latency = 2, page change) tprec pre act rd tw tact tread tlate tlate data address address address address bank address bank address address address row address column address row address row address sdclk (output) bcyst (output) sdcke (output) h command sdras (output) sdcas (output) csn (output) we (output) ldqm (output) udqm (output) note (output) bank address (output) a10 (output) a0 to a9 (output) d0 to d15 (i/o) off-page address note addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 180 figure 5-20. sdram single read cycle (3/3) (c) during on-page access (when latency = 2) rd tw tread tlate tlate data address address column address address address sdclk (output) bcyst (output) sdcke (output) h command sdras (output) h sdcas (output) csn (output) we (output) ldqm (output) udqm (output) note (output) bank address (output) a10 (output) a0 to a9 (output) d0 to d15 (i/o) on-page note addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 4. the timing chart shown here is the timing w hen the previous cycle accessed another cs space or when the bus was in an idle stat e. if access to the same cs space continues, a tw state is not inserted (the bcyst signal becom es active in the tread state). chapter 5 memory access control function user?s manual u14359ej5v1ud 181 (2) sdram single write cycle the sdram single write cycle is a cycle for writing to sdram by executi ng a write instruction (st) for the sdram area or by 2-cycle dma transfer. in the sdram single write cycle, the active co mmand (act) and write command (wr) are issued for sdram in that order. during on-page access, however , only the write command is issued and the precharge command and active command are not issued. when a page change occurs in the same bank, the precharge command (pr) is issued before the active command. a one-state tw cycle is always inserted immediately befor e every write command, which is activated by the cpu. the timing charts of the sdram single write cycle are shown below. chapter 5 memory access control function user?s manual u14359ej5v1ud 182 figure 5-21. sdram single write cycle (1/3) (a) during off-page access tact off-page act wr tw twr twpre twe data address address sdclk (output) bcyst (output) sdcke (output) h command sdras (output) sdcas (output) csn (output) we (output) ldqm (output) udqm (output) note (output) address bank address bank address (output) address row address a10 (output) address column address row address a0 to a9 (output) d0 to d15 (i/o) address address note addresses other than the bank address, a10, and a0 to a9. remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 183 figure 5-21. sdram single write cycle (2/3) (b) during off-page access (page change) tprec pre act wr tw tact twr1 twr2 twr3 data address address column address row address aaddress address bank address address bank address address row address off-page sdclk (output) bcyst (output) sdcke (output) h command sdras (output) sdcas (output) csn (output) we (output) ldqm (output) udqm (output) note (output) bank address (output) a10 (output) a0 to a9 (output) d0 to d15 (i/o) address row address note addresses other than the bank address, a10, and a0 to a9. remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 184 figure 5-21. sdram single write cycle (3/3) (c) during on-page access wr tw twr twe twpre data on-page sdclk (output) bcyst (output) sdcke (output) h command sdras (output) h sdcas (output) csn (output) we (output) ldqm (output) udqm (output) address address note (output) column address a0 to a9 (output) a10 (output) address address bank address (output) d0 to d15 (i/o) note addresses other than the bank address, a10, and a0 to a9. remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. the timing chart shown here is the timing w hen the previous cycle accessed another cs space or when the bus is an idle state. if access to the same cs space continues, a tw state is not inserted (the bcyst signal becomes active in the twr1 state). chapter 5 memory access control function user?s manual u14359ej5v1ud 185 (3) sdram access timing control the sdram access timing can be controlled by sdram config uration register n (scrn) (n = 1, 3, 4, 6). for details, see 5.4.4 sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) . caution wait control by the wait pi n is not available during sdram access. (a) number of waits from bank active command to read/write command the number of wait states from bank active comm and issue to read/write command issue can be set by setting the bcw1n and bcw0n bits of the scrn register. bcw1n, bcw0n = 01b: 1 wait bcw1n, bcw0n = 10b: 2 waits bcw1n, bcw0n = 11b: 3 waits (b) number of waits from precharge command to bank active command the number of wait states from precharge command issue to bank active command issue can be set by setting the bcw1n and bcw0n bits of the scrn register. bcw1n, bcw0n = 01b: 1 wait bcw1n, bcw0n = 10b: 2 waits bcw1n, bcw0n = 11b: 3 waits (c) cas latency setting when read the cas latency during a read operation can be set by setting the ltm2n to lt m0n bits of the scrn register. ltm2n to ltm0n = 010b: latency = 2 ltm2n to ltm0n = 011b: latency = 3 (d) number of waits from refresh command to next command the number of wait states from refresh command i ssue to next command issue can be set by setting the bcw1n and bcw0n bits of the scrn register. the num ber of wait states becom es four times the value set by bcw1n and bcw0n. bcw1n, bcw0n = 01b: 4 waits bcw1n, bcw0n = 10b: 8 waits bcw1n, bcw0n = 11b: 12 waits chapter 5 memory access control function user?s manual u14359ej5v1ud 186 figure 5-22. sdram access timing (1/4) (a) read timing (16-bit bus width word a ccess, page change, bcw = 2, latency = 2) data data data data tw tbcw tact tbcw tread tact tlate tread tlate tread tread tlate tlate tbcw tw tprec add. add. add. bnk. add. bnk. add. bnk. row add. col. col. add. row add. sdclk (output) note (output) a11 (output) a0 to a10 (output) bcyst (output) bank address (output) sdras (output) sdcas (output) csn (output) rd (output) oe (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d15 (i/o) h bcw bcw bcw bank a read command bank a read command bank a read command (on-page) bank a read command (on-page) bank a precharge command (page change) bank a active command bank a active command add. add. add. row add. add. row add. add. col. col. note addresses other than the bank address, a11, and a0 to a10. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 4. add.: address bnk.: bank address col.: column address row: row address chapter 5 memory access control function user?s manual u14359ej5v1ud 187 figure 5-22. sdram access timing (2/4) (b) read timing (8-bit bus width word access, page cha nge, bcw = 2, latency = 2) data data data data data data data data ta tw tact tbcw tread tread tread tread tbcw tlate tlate tact tbcw tread tread tread tread tlate tlate tprec bcw bcw bcw add. add. row col. col. add. col. col. col. col. col. col. add. row add. add. add. add. add. add. add. add. add. add. sdclk (output) note (output) a10 (output) a0 to a9 (output) bcyst (output) bank address (output) sdras (output) sdcas (output) csn (output) rd (output) oe (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d7 (i/o) h bank a read command bank a read command bank a read command bank a read command bank a read command bank a read command bank a read command bank a read command (on-page) bank a precharge command bank a active command bank a active command (on-page) (page change) add. bnk. add. add. add. row bnk. bnk. add. add. row note addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 4. add.: address bnk.: bank address col.: column address row: row address chapter 5 memory access control function user?s manual u14359ej5v1ud 188 figure 5-22. sdram access timing (3/4) (c) write timing (16-bit bus width word a ccess, bank change, bcw = 1, latency = 2) sdclk (output) note (output) a11 (output) a0 to a10 (output) bcyst (output) bank address (output) sdras (output) sdcas (output) csn (output) rd (output) oe (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d15 (i/o) add. add. add. add. add. add. add. add. add. col. add. row col. row col. col. col. col. data data data data h tw tact twr twr twpre bcw bank a write twe tact tw twr twr bcw bank b write twpre twe tw tw twe twr twr twpre bank b write bank a write command bank a write command bank b write command bank a active command bank b active command bank b write command bank b write command bank b write command bank a precharge command add. bnk. add. bnk. bnk. add. add. add. add. add. add. row add. row add. data data when write-accessing the page that includes bank b, which was accessed by the previous write access. note addresses other than the bank address, a11, and a0 to a10. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 4. add.: address bnk.: bank address col.: column address row: row address chapter 5 memory access control function user?s manual u14359ej5v1ud 189 figure 5-22. sdram access timing (4/4) (d) write timing (8-bit bus width word access, bank cha nge, bcw = 1, latency = 2) sdclk (output) note (output) a10 (output) a0 to a9 (output) bcyst (output) bank address (output) sdras (output) sdcas (output) csn (output) rd (output) oe (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d7 (i/o) add. add. add. add. add. add. add. add. add. add. add. add. add. add. add. add. add. add. add. bnk. col. col. col. col. bnk. data data data data data data data data h data data data tw tact twr twr twr twr bcw bank a write twpre twe tw tact tw tact twr twr twr twr bcw bcw twpre twe tread tread tread tread tlate tlate bank b write bank a read bank a active command bank a write command bank a write command bank a write command bank a write command bank a precharge command bank b active command bank b write command bank b write command bank b write command bank b write command bank b precharge command bank a active command bank a read command bank a read command bank a read command bank a read command add. bnk. add. bnk. bnk. add. add. add. add. add. add. row add. row col. col. col. col. add. row col. col. col. col. add. row row add. add. row data note addresses other than the bank address, a10, and a0 to a9. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 4. add.: address bnk.: bank address col.: column address row: row address chapter 5 memory access control function user?s manual u14359ej5v1ud 190 5.4.6 refresh control function the v850e/ma1 can generate a refresh cycle. the refresh cycle is set with sdram refresh control registers 1, 3, 4, and 6 (rfs1, rfs3, rfs4, rfs6). t he rfsn register corresponds to csn (n = 1, 3, 4, 6). for example, to connect sdram to cs1, set rfs1. when another bus master occupies the external bus, the dram controller cannot occupy the external bus. in this case, the dram controller issues a refresh request to the bus master by changing the refrq signal to active (low level). during a refresh operation, the address bus retains t he state it was in just before the refresh cycle. (1) sdram refresh control registers 1, 3, 4, 6 (rfs1, rfs3, rfs4, rfs6) these registers are used to enable or disable a refresh and set the refresh interval. the refresh interval is determined by the following calculation formula. refresh interval ( s) = refresh count clock (t rcy ) interval factor the refresh count clock and interval factor are determined by the renn bit and rin5n to rin0n bits, respectively, of the rfsn register. note that n corresponds to the register number (1, 3, 4, 6) of sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6). these registers can be read/written in 16-bit units. cautions 1. write to the rfs1, rfs3, rfs4, and rf s6 registers after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initialization routine until the initial set tings of the rfs1, rfs3, rfs4, and rfs6 registers are complete. however, it is possible to access external memory areas whose initialization settings are complete. 2. immediately after the renn bit of the rfsn register is set (1), the refresh cycle may be executed for the sdram (n = 1, 3, 4, 6). this does not aff ect the refresh cycle occurring at this time nor the operations after the re fresh cycle is executed. the refresh cycles occurring thereafter will be execu ted normally according to th e set interval. however, set the rfsn register as shown below for applications which will have problems with this refresh cycle. <1> with the mea bit of the bctm register set (1), set the bta1 and bta0 bits to 01 (page rom connection) (m = 0, 1, a: a = 1, 3 when m = 0, a = 4, 6 when m = 1). <2> set the renn bit of the rfsn register (1) to enable refresh (n = 1, 3, 4, 6). <3> with the mea bit of the bctm register set (1), set the bta1 and bta0 bits to 11 (sdram connection) (m = 0, 1, a: a = 1, 3 when m = 0, a = 4, 6 when m = 1). <4> set the scrn register to init ialize the sdram (n = 1, 3, 4, 6). chapter 5 memory access control function user?s manual u14359ej5v1ud 191 15 ren1 rfs1 address fffff4a6h after reset 0000h 14 0 13 0 12 0 11 0 10 0 9 rcc11 8 rcc01 7 0 6 0 5 rin51 4 rin41 3 rin31 2 rin21 1 rin11 0 rin01 ren3 rfs3 fffff4aeh 0000h 00000 rcc13 rcc03 00 rin53 rin43 rin33 rin23 rin13 rin03 ren4 rfs4 fffff4b2h 0000h 00000 rcc14 rcc04 00 rin54 rin44 rin34 rin24 rin14 rin04 ren6 rfs6 fffff4bah 0000h 00000 rcc16 rcc06 00 rin56 rin46 rin36 rin26 rin16 rin06 bit position bit name function 15 renn (n = 1, 3, 4, 6) refresh enable specifies whether cbr refresh is enabled or disabled. 0: refresh disabled 1: refresh enabled refresh count clock specifies the refresh count clock (t rcy ). rcc1n rcc0n refresh count clock (t rcy ) 0 0 32/f xx 0 1 128/f xx 1 0 256/f xx 1 1 setting prohibited 9, 8 rcc1n, rcc0n (n = 1, 3, 4, 6) refresh interval sets the interval factor of the interval timer for the generation of the refresh timing. rin5n rin4n rin3n rin2n rin1n rin0n interval factor 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : 1 1 1 1 1 1 64 5 to 0 rin5n to rin0n (n = 1, 3, 4, 6) remark f xx : internal system clock chapter 5 memory access control function user?s manual u14359ej5v1ud 192 table 5-3. example of interval factor settings interval factor value notes 1, 2 specified refresh interval value ( s) refresh count clock (t rcy ) f xx = 20 mhz f xx = 33 mhz f xx = 50 mhz 32/f xx 9 (14.4) 16 (15.5) 24 (15.4) 128/f xx 2 (12.8) 4 (15.5) 6 (15.4) 15.6 256/f xx 1 (12.8) 2 (15.5) 3 (15.4) notes 1. the interval factor is set by bits rin0n to rin5n of the rfsn register (n = 1, 3, 4, 6). 2. the values in parentheses are the calc ulated values for the refresh interval ( s). refresh interval ( s) = refresh count clock (t rcy ) interval factor remark f xx : internal system clock the v850e/ma1 can automatica lly generate an auto-refresh cycle and a self-refresh cycle. chapter 5 memory access control function user?s manual u14359ej5v1ud 193 (2) auto-refresh cycle in the auto-refresh cycle, the auto-refresh command (r ef) is issued four clocks after the precharge command for all banks (pall) is issued. figure 5-23. auto-refresh cycle trefw pall ref tabpw trefw trefw tref h h address auto-refresh cycle sdclk (output) bcyst (output) sdcke (output) h h command sdras (output) sdcas (output) csn (output) we (output) ldqm (output) udqm (output) address (output) a10 (output) d0 to d15 (i/o) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 194 (3) refresh timing figure 5-24. cbr refresh timing (sdram) d0 to d15 (i/o) we (output) oe (output) rd (output) sdcas (output) sdras (output) csn (output) bcyst (output) a0 to a9, a11 to a23 (output) a10 (output) sdclk (output) allpre tw tw tref tbcw tbcw tw tbcw tbcw tbcw tbcw tbcw tbcw ti ti sdcke (output) ldqm (output) udqm (output) all-bank precharge command refresh command h h h bcw 4clk remarks 1. the number of wait states set by the bc w1n and bcw0n bits of the scrn register 4 clocks will be inserted in the bcw 4 clk period. 2. n = 1, 3, 4, 6 3. the broken lines indicate the high-impedance state. chapter 5 memory access control function user?s manual u14359ej5v1ud 195 5.4.7 self-refresh control function in the case of transition to the idle or software stop mode, or if the selfref signal becomes active, the dram controller generates the cbr self-refr esh cycle (the system enters a state in which not only sdram, but also all dram is self-refreshed). note that the sdras pulse width of sdram must meet the specifications for sdram to enter the self-refresh operation. cautions 1. when the transition to the self-refresh cycle is cause d by selfref signa l input, releasing the self-refresh cycle is only possible by inputti ng an inactive level to the selfref pin. 2. the internal rom and internal ram can be accessed even in th e self-refresh cycle. however, access to an on-chip pe ripheral i/o register or extern al device is held pending until the self-refresh cycle is cleared. to release the self-refresh cycle, us e one of the three methods below. (1) release by nmi input (a) in the case of self-refresh cycle in idle mode to release the self-refresh cycle, make the s dras, sdcas, ldqm, and udqm signals inactive immediately. (b) in the case of self-refresh cycle in software stop mode to release the self-refresh cycle, make the sdr as, sdcas, ldqm, and udqm signals inactive after stabilizing oscillation. (2) release by intp0n0 and intp0n1 inputs (n = 0 to 3) (a) in the case of self-refresh cycle in idle mode to release the self-refresh cycle, make the s dras, sdcas, ldqm, and udqm signals inactive immediately. (b) in the case of self-refresh cycle in software stop mode to release the self-refresh cycle, make the sdr as, sdcas, ldqm, and udqm signals inactive after stabilizing oscillation. (3) release by reset input chapter 5 memory access control function user?s manual u14359ej5v1ud 196 figure 5-25. self-refresh timing (sdram) d0 to d15 (i/o) we (output) oe (output) rd (output) sdcas (output) sdras (output) csn (output) bcyst (output) a0 to a9, a11 to a23 (output) a10 (output) sdclk (output) tw tw nop tw tref tw tw ti ti tw tw tdcw tdcw tdcw tdcw sdcke (output) ldqm (output) udqm (output) all-bank precharge command refresh command nop command h h bcw 4clk note note shown above is the case when the self-refresh cycle is started in the idle or software stop mode. if the self-refresh cycle is started by inputting the ac tive level of the selfref signal, sdclk is output without going low. remarks 1. the number of wait states set by the bc w1n and bcw0n bits of the scrn register 4 clocks will be inserted in the bcw 4 clk period. 2. n = 1, 3, 4, 6 3. the broken lines indicate the high-impedance state. chapter 5 memory access control function user?s manual u14359ej5v1ud 197 5.4.8 sdram initialization sequence be sure to initialize sdram when applying power. (1) set the registers of sdram (other t han sdram configuration register n (scrn)) ? bus cycle type configuration r egisters 0 and 1 (bct0 and bct1) ? bus cycle control register (bcc) ? sdram refresh control registers 1, 3, 4, 6 (rfs1, rfs3, rfs4, rfs6) (2) set sdram configuration register s 1, 3, 4, 6 (scr1, scr3, scr4, scr6). when writing data to these registers, the following commands are issu ed for sdram in the order shown below. ? all bank precharge command ? refresh command (8 times) ? command that is used to set a mode register figures 5-26 and 5-27 show examples of the sdram mode register setting timing. caution when using the sdclk and sdcke signals, it is necessary to set the sdclk output mode and the sdcke output mode for these signals by setting the pmccd register. in this case, however, these settings must not be executed at the same time. be sure to set the sdcke output mode after se tting the sdclk output mode (refer to 14.3.14 (2) (b) port cd mode control register (pmccd)). chapter 5 memory access control function user?s manual u14359ej5v1ud 198 figure 5-26. sdram mode register setting cycle trefw pall ref mrs tabpw trefw trefw tref md md h h mode register setting cycle refresh command (ref) (generated 8 times) sdclk (output) bcyst (output) sdcke (output) h h command sdras (output) sdcas (output) csn (output) we (output) ldqm (output) udqm (output) address (output) a10 (output) d0 to d15 (i/o) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 chapter 5 memory access control function user?s manual u14359ej5v1ud 199 figure 5-27. sdram register write operation timing alpre tw tw tw tref tw tw tref tw tw tw regw tw tw tw tw tw tw d0 to d15 (i/o) we (output) oe (output) rd (output) sdcas (output) sdras (output) csn (output) bcyst (output) a0 to a9 (output) a10 (output) bank address (output) note (output) sdclk (output) sdcke (output) h ldqm (output) udqm (output) scrn register write all-bank precharge command refresh command (1st time) register write command refresh command (2nd time) refresh end (1st time) refresh end (8th time) sdram access enabled refresh (7 times) note addresses other than the bank address, a10, and a0 to a9. remarks 1. n = 1, 3, 4, 6 2. the broken lines indicates the high-impedance state. user?s manual u14359ej5v1ud 200 chapter 6 dma functions (dma controller) the v850e/ma1 includes a direct memory access (dma) controller (dmac) that ex ecutes and controls dma transfer. the dmac controls data transfer between memory and i/o, or among memories, based on dma requests issued by the on-chip peripheral i/o (such as se rial interface, real-time pulse unit, and a/d converter), dmarq0 to dmarq3 pins, or software triggers (memory refers to internal ram or external memory). 6.1 features 4 independent dma channels transfer unit: 8/16 bits maximum transfer count: 65,536 (2 16 ) two types of transfer flyby (1-cycle) transfer 2-cycle transfer three transfer modes single transfer mode single-step transfer mode block transfer mode transfer requests request by interrupts from on-chip peripheral i/o (suc h as serial interface, real-time pulse unit, a/d converter) requests via dmarq0 to dmarq3 pin input requests by software trigger transfer objects memory ? i/o memory ? memory dma transfer end output signals (tc0 to tc3) next address setting function chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 201 6.2 configuration tcn cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850e/ma1 bus interface external bus external ram external rom external i/o dma source address register (dsanh/dsanl) dma transfer count register (dbcn) dma channel control register (dchcn) dma terminal count output control register (dtoc) dma destination address register (ddanh/ddanl) dmarqn dmaakn dma addressing control register (dadcn) dma disable status register (ddis) dma trigger factor register (dtfrn) dma restart register (drst) remark n = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 202 6.3 control registers 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) these registers are used to set the dma source address (28 bits) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, dsanh and dsanl. also, since these registers are configured as 2-stage fifo buffer registers consisting of a master register and a slave register, a new transfer source address for dma transf er can be specified during dma transfer. (refer to 6.9 next address setting function .) in this case, th e newly set value of the dsan register is transferred to the slave register and becomes valid only when dma transfer has been completed normally and the tcn bit of the dchcn register is set to 1, or when the initn bit of t he dchcn register is set to 1 (n = 0 to 3). when flyby transfer is specified with the ttyp bit of dma addressing control register n (dadcn), the external memory addresses are set by the dsan register, regardless of the transfer direction. at this time, the setting of dma destination address register n (ddan) is ignored (n = 0 to 3). (1) dma source address registers 0h to 3h (dsa0h to dsa3h) these registers can be read/written in 16-bit units. be sure to clear bits 14 to 12 to 0. if they are set to 1, the oper ation is not guaranteed. cautions 1. when setting an addr ess of an on-chip peripheral i/o regi ster for the source address, be sure to specify an addr ess between ffff000h and fffffffh . an address of the on- chip peripheral i/o register image (3fff 000h to 3ffffffh) must not be specified. 2. do not set the dsanh regi ster while dma is suspended. 15 ir dsa0h address fffff082h after reset undefined 14 0 13 0 12 0 11 sa27 10 sa26 9 sa25 8 sa24 7 sa23 6 sa22 5 sa21 4 sa20 3 sa19 2 sa18 1 sa17 0 sa16 ir dsa1h fffff08ah undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 ir dsa2h fffff092h undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 ir dsa3h fffff09ah undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 bit position bit name function 15 ir internal ram select specifies the dma source address. 0: external memory, on-chip peripheral i/o 1: internal ram 11 to 0 sa27 to sa16 source address sets the dma source address (a27 to a16). du ring dma transfer, it stores the next dma transfer source address. during flyby transf er, it stores an external memory address. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 203 (2) dma source address registers 0l to 3l (dsa0l to dsa3l) these registers can be read/written in 16-bit units. 15 sa15 dsa0l address fffff080h after reset undefined 14 sa14 13 sa13 12 sa12 11 sa11 10 sa10 9 sa9 8 sa8 7 sa7 6 sa6 5 sa5 4 sa4 3 sa3 2 sa2 1 sa1 0 sa0 sa15 dsa1l fffff088h undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa15 dsa2l fffff090h undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa15 dsa3l fffff098h undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 bit position bit name function 15 to 0 sa15 to sa0 source address sets the dma source address (a15 to a0). during dma transfer, it stores the next dma transfer source address. during flyby transf er, it stores an external memory address. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 204 6.3.2 dma destination address regi sters 0 to 3 (dda0 to dda3) these registers are used to set the dm a destination address (28 bits) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, ddanh and ddanl. also, since these registers are configured as 2-stage fifo buffer registers consisting of a master register and a slave register, a new transfer destination address for dma tr ansfer can be specified during dma transfer. (refer to 6.9 next address setting function .) in this case, the newly set value of the ddan register is transferred to the slave register and becomes valid only when dma transfer has been completed normally and the tcn bit of the dchcn register is set to 1, or when the initn bit of the dchcn register is set to 1 (n = 0 to 3). when flyby transfer is specified with bit ttyp of dma addre ssing control register n (dadcn), regardless of the transfer direction, the setting of dma destination addre ss register n (ddan) is ignored (n = 0 to 3). (1) dma destination address register s 0h to 3h (dda0h to dda3h) these registers can be read/written in 16-bit units. be sure to clear bits 14 to 12 to 0. if they are set to 1, the oper ation is not guaranteed. cautions 1. when setting an address of an on- chip peripheral i/o regist er for the destination address, be sure to specify an addres s between ffff000h and fffffffh. an address of the on-chip peripheral i/o register image (3fff000h to 3ffffffh) must not be specified. 2. do not set the ddanh regist er while dma is suspended. 15 ir dda0h address fffff086h after reset undefined 14 0 13 0 12 0 11 da27 10 da26 9 da25 8 da24 7 da23 6 da22 5 da21 4 da20 3 da19 2 da18 1 da17 0 da16 ir dda1h fffff08eh undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 ir dda2h fffff096h undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 ir dda3h fffff09eh undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 bit position bit name function 15 ir internal ram select specifies the dma destination address. 0: external memory, on-chip peripheral i/o 1: internal ram 11 to 0 da27 to da16 destination address sets the dma destination address (a27 to a16). during dma transfer, it stores the next dma transfer destination address. this setting is ignored during flyby transfer. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 205 (2) dma destination address regist ers 0l to 3l (dda0l to dda3l) these registers can be read/written in 16-bit units. 15 da15 dda0l address fffff084h after reset undefined 14 da14 13 da13 12 da12 11 da11 10 da10 9 da9 8 da8 7 da7 6 da6 5 da5 4 da4 3 da3 2 da2 1 da1 0 da0 da15 dda1l fffff08ch undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 da15 dda2l fffff094h undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 da15 dda3l fffff09ch undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 bit position bit name function 15 to 0 da15 to da0 destination address sets the dma destination address (a15 to a0). during dma transfer, it stores the next dma transfer destination address. this setting is ignored during flyby transfer. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 206 6.3.3 dma byte count registers 0 to 3 (dbc0 to dbc3) these 16-bit registers are used to set the byte transfer c ount for dma channel n (n = 0 to 3). they store the remaining transfer count during dma transfer. also, since these registers are configured as 2-stage fifo buffer registers consisting of a master register and a slave register, a new dma byte transfer count for dma tran sfer can be specified during dma transfer. (refer to 6.9 next address setting function .) in this case, the newly set value of th e dbcn register is transferred to the slave register and becomes valid only when dma transfer has been completed normally and the tcn bit of the dchcn register is set to 1, or when the initn bit of t he dchcn register is set to 1 (n = 0 to 3). these registers are decremented by 1 for each tr ansfer, and transfer ends when a borrow occurs. these registers can be read/written in 16-bit units. cautions 1. if the transfer type is flyby transfer or if data is transfer red to the internal ram in two cycles, do not set the transfer count to two (set value of dbcn register = 0001h). if dma transfer must be executed twice, be sure to set the transfer count to on e (set value of dbcn register = 0000h) and execute dma transfer twice. 2. do not set the dbcn register while dma transfer is suspended. remark if the dbcn register is read during dma transfe r after a terminal count has occurred without the register being overwritten, the value set immedi ately before the dma transfer will be read out (0000h will not be read, even if dma transfer has ended). 15 bc15 dbc0 address fffff0c0h after reset undefined 14 bc14 13 bc13 12 bc12 11 bc11 10 bc10 9 bc9 8 bc8 7 bc7 6 bc6 5 bc5 4 bc4 3 bc3 2 bc2 1 bc1 0 bc0 bc15 dbc1 fffff0c2h undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bc15 dbc2 fffff0c4h undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bc15 dbc3 fffff0c6h undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bit position bit name function byte count sets the byte transfer count and stores the remaining byte transfer count during dma transfer. dbcn (n = 0 to 3) states 0000h byte transfer count 1 or remaining byte transfer count 0001h byte transfer count 2 or remaining byte transfer count : : ffffh byte transfer count 65,536 (2 16 ) or remaining byte transfer count 15 to 0 bc15 to bc0 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 207 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) these 16-bit registers are used to co ntrol the dma transfer mode for dma channel n (n = 0 to 3). these registers cannot be accessed during dma operation. when flyby transfer is specified by t he ttyp bit of the dadcn register, the co unt direction of the external memory addresses is set by the sad1 and sad0 bits, regardless of the transfer direction. at this time, the settings of the dda1 and dda0 bits are ignored. they can be read/written in 16-bit units. be sure to clear bits 13 to 8 to 0. if they are set to 1, the operat ion is not guaranteed. cautions 1. the ds1 and ds0 bits are used to set how many bits of data are to be transferred. when 8-bit data is set (ds1 and ds0 bits = 00) , the lower bytes of the data bus (d0 to d7) are not always used. if the transfer data size is set to 16 bits, transfer is always started from an address with the lowest bit of the address aligned to ?0?. in th is case, transfer cannot be started from an odd address. 2. set the dadcn register when the target channels is in one of the following periods (the operation is not guaranteed if the regi ster is set at any other time). ? period from system reset to the generati on of the first dma transfer request ? period from completion of dma transfer (after terminal count) to the ge neration of the next dma transfer request ? period from forced termination of dma transf er (after the initn bit of the dchcn register was set to 1) to the generation of the next dma transfer request (1/2) 15 ds1 dadc0 address fffff0d0h after reset 0000h 14 ds0 13 0 12 0 11 0 10 0 9 0 8 0 7 sad1 6 sad0 5 dad1 4 dad0 3 tm1 2 tm0 1 ttyp 0 tdir ds1 dadc1 fffff0d2h 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 ttyp tdir ds1 dadc2 fffff0d4h 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 ttyp tdir ds1 dadc3 fffff0d6h 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 ttyp tdir bit position bit name function data size sets the transfer data size for dma transfer. ds1 ds0 transfer data size 0 0 8 bits 0 1 16 bits 1 0 setting prohibited 1 1 setting prohibited 15, 14 ds1, ds0 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 208 (2/2) bit position bit name function 7, 6 sad1, sad0 source address count direction sets the count direction of the source address for dma channel n (n = 0 to 3). sad1 sad0 count direction 0 0 increment 0 1 decrement 1 0 fixed 1 1 setting prohibited 5, 4 dad1, dad0 destination address count direction sets the count direction of the destinat ion address for dma channel n (n = 0 to 3). dad1 dad0 count direction 0 0 increment 0 1 decrement 1 0 fixed 1 1 setting prohibited transfer mode sets the transfer mode during dma transfer. tm1 tm0 transfer mode 0 0 single transfer mode 0 1 single-step transfer mode 1 0 setting prohibited 1 1 block transfer mode 3, 2 tm1, tm0 1 ttyp transfer type sets the dma transfer type. 0: 2-cycle transfer 1: flyby transfer 0 tdir transfer direction sets the transfer direction during transfer between i/o and memory. the setting is valid during flyby transfer only and ignored during 2-cycle transfer. 0: memory i/o (read) 1: i/o memory (write) chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 209 6.3.5 dma channel control regist ers 0 to 3 (dchc0 to dchc3) these 8-bit registers are used to c ontrol the dma transfer operating mode for dma channel n (n = 0 to 3). these registers can be read/written in 8-bit or 1-bit units . (however, bit 7 is read only and bits 2 and 1 are write only. if bits 2 and 1 are read, the read value is always 0.) be sure to clear bits 6 to 4 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. if transfer has been completed with th e mlen bit set to 1 and if the next transfer request is made by dma transfer (hardware dma) th at is started by dmarqn pin input or an interrupt from the on-chip peripheral i/o, the next transfer is executed with the tcn bit set to 1 (not automatically cleared to 0). 2. set the mlen bit when the target channel is in on e of the following periods (the operation is not guaranteed if the bit is set at any other time). ? period from system reset to the generati on of the first dma transfer request ? period from completion of dma transfer (a fter terminal count) to the generation of the next dma transfer request ? period from forced termination of dma tr ansfer (after the initn bit of the dchcn register was set to 1) to the genera tion of the next dma transfer request 3. if dma transfer is forcibly terminated in the last transfer cycle with the mlen bit set to 1, the operation is performed in the same manne r as when transfer is completed (the tcn bit is set to 1 and the tcn signal is output). (the enn bit is cleared to 0 upon forced termination, regardless of th e value of the mlen bit.) in this case, the enn bit must be set to 1 and the tcn bit must be read (cleared to 0) when the next dma transfer request is made. 4. upon completion of dma transfer (duri ng terminal count), each bit is updated with the enn bit cleared to 0 and then the tcn bit set to 1. if the statuses of the tcn bit and enn bit are polled and if the dchcn register is read while each bit is updated, therefore, a value indicating the status ?transfer not comp leted and prohibited? (tcn bit = 0 and enn bit = 0) may be read (this is not abnormal). 5. do not set the enn and stgn bits while dma is suspended. if they are set while dma is suspe nded, the operation is not guaranteed. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 210 address fffff0e0h <7> tc0 dchc0 6 0 5 0 4 0 <3> mle0 <2> init0 <1> stg0 <0> e00 after reset 00h fffff0e2h tc1 dchc1 0 0 0 mle1 init1 stg1 e11 00h fffff0e4h tc2 dchc2 0 0 0 mle2 init2 stg2 e22 00h fffff0e6h tc3 dchc3 0 0 0 mle3 init3 stg3 e33 00h bit position bit name function 7 tcn (n = 0 to 3) terminal count this status bit indicates whether dma transf er through dma channel n is complete or not. this bit is read-only. it is set to 1 at t he last dma transfer and cleared (to 0) when it is read. 0: dma transfer is not complete. 1: dma transfer is complete. 3 mlen (n = 0 to 3) multi link enable bit if this bit is set to 1 when dma transfer is complete (at terminal count output), the enn bit is not cleared to 0 and the dma transfer enable state is retained. if the next dma transfer startup factor is input from the dmarqn pin or is an interrupt from the on-chip peripheral i/o (hardware dma), the dma transfer request is acknowledged even if the tcn bit is not read. if the next dma transfer startup factor is input by setting the stgn bit to 1 (software dma), the dma transfer request is acknowledged if the tcn bit is read and cleared to 0. if this bit is cleared to 0 when dma transfer is complete (at terminal count output), the enn bit is cleared to 0 and the dma transfer disabl e state is entered. at the next dma request, the enn bit must be set to 1 and the tcn bit read. 2 initn (n = 0 to 3) initialize if this bit is set to 1 during dma transfer or while dma transfer is suspended, dma transfer is forcibly terminated (refer to 6.13.1 restriction related to dma transfer forcible termination ). 1 stgn (n = 0 to 3) software trigger if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. 0 enn (n = 0 to 3) enable specifies whether dma transfer through dma chan nel n is to be enabled or disabled. this bit is cleared to 0 when dma transfer ends. it is also cleared to 0 when dma transfer is forcibly suspended or terminated by setti ng the initn bit to 1 or by nmi input. 0: dma transfer disabled 1: dma transfer enabled caution if the enn bit is set to 1, do not set it until dma transfer has been completed the number of times set by the dbcn register or dma transfer is forcibly terminated by the initn bit. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 211 6.3.6 dma disable status register (ddis) this register holds the contents of the enn bit of the dchcn register during forcible suspension by nmi input (n = 0 to 3). this register is read-only in 8-bit units. be sure to clear bits 4 to 7 to 0. if they are set to 1, the operation is not guaranteed. address fffff0f0h 7 0 ddis 6 0 5 0 4 0 3 ch3 2 ch2 1 ch1 0 ch0 after reset 00h bit position bit name function 3 to 0 ch3 to ch0 nmi interruption status reflects the contents of the enn bit of the dchcn register during forcible suspension by nmi input. the contents of this register ar e held until the next forcible suspension by nmi input or until the system is reset. 6.3.7 dma restart register (drst) the enn bit of the drst register and t he enn bit of the dchcn register are linked to each other (n = 0 to 3). this register can be read/written in 8-bit units. be sure to clear bits 4 to 7 to 0. if they are set to 1, the operation is not guaranteed. address fffff0f2h 7 0 drst 6 0 5 0 4 0 3 en3 2 en2 1 en1 0 en0 after reset 00h bit position bit name function 3 to 0 en3 to en0 restart enable specifies whether dma transfer through dma channel n is to be enabled or disabled. this bit is cleared to 0 when dma transfer is completed in accordance with the terminal count output. it is also cleared to 0 when dma transfer is fo rcibly terminated by setting the initn bit of the dchcn register to 1 or by nmi input. 0: dma transfer disabled 1: dma transfer enabled chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 212 6.3.8 dma terminal count output control register (dtoc) the dma terminal count output control register (dtoc) is an 8-bit register that contro ls the terminal count output from each dma channel. terminal count signals from each dma channel can be brought together and output from the tc0 pin. this register can be read/written in 8- or 1-bit units. address fffff8a0h 7 0 dtoc 6 0 5 0 4 0 <3> tco3 <2> tco2 <1> tco1 <0> tco0 after reset 01h bit position bit name function 3 to 0 tco3 to tco0 terminal count output indicates the state of the tc0 pin. 0: channel n terminal count signal not output from tc0 pin (n = 0 to 3). 1: channel n terminal count signal output from tc0 pin (n = 0 to 3). the following shows an example of the case when the dtoc register is set to 03h. tc0 (output) tc2 (output) dma0 cpu dma0 dma1 dma1 cpu dma2 dma2 dma channel 2 terminal count dma channel 1 terminal count dma channel 0 terminal count chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 213 6.3.9 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) these 8-bit registers are used to control the dma transfe r start trigger through interrupt requests from on-chip peripheral i/o. the interrupt requests set by these register s serve as dma transfer startup factors. these registers can be read/written in 8-bit units. howe ver, only bit 7 (dfn) can be read/written in 1-bit units. be sure to clear bit 6 to 0. if the it is set to 1, the operation is not guaranteed. cautions 1. to change the setti ng of the dtfrn register, be su re to stop the dma operation. 2. an interrupt request input in the standby mode (idle or software stop mode) cannot be a dma transfer start factor. (1/2) address fffff810h <7> df0 dtfr0 6 0 5 ifc05 4 ifc04 3 ifc03 2 ifc02 1 ifc01 0 ifc00 after reset 00h fffff812h df1 dtfr1 0 ifc15 ifc14 ifc13 ifc12 ifc11 ifc10 00h fffff814h df2 dtfr2 0 ifc25 ifc24 ifc23 ifc22 ifc21 ifc20 00h fffff816h df3 dtfr3 0 ifc35 ifc34 ifc33 ifc32 ifc31 ifc30 00h bit position bit name function 7 dfn dma request flag this is a dma transfer request flag. only 0 can be written to this flag. 0: dma transfer not requested 1: dma transfer requested if the interrupt specified as the dma transfer st artup trigger occurs and it is necessary to clear the dma transfer request while dma trans fer is disabled (including when it is aborted by nmi or forcibly terminated by software) , stop the operation of the source causing the interrupt, and then clear the dfn bit to 0 (for example, disable reception in the case of serial reception). if it is clear that the interrupt will not occur until dma transfer is resumed next, it is not necessary to stop the operat ion of the source causing the interrupt. interrupt factor code this code is used to set the interrupt source s serving as dma transfer startup factors. ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request from on-chip peripheral i/o disabled 0 0 0 0 0 1 intp000/intm000 0 0 0 0 1 0 intp001/intm001 0 0 0 0 1 1 intp010/intm010 0 0 0 1 0 0 intp011/intm011 0 0 0 1 0 1 intp020/intm020 0 0 0 1 1 0 intp021/intm021 5 to 0 ifcn5 to ifcn0 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 214 (2/2) bit position bit name function ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 1 1 1 intp030/intm030 0 0 1 0 0 0 intp031/intm031 0 0 1 0 0 1 intp100 0 0 1 0 1 0 intp101 0 0 1 0 1 1 intp102 0 0 1 1 0 0 intp103 0 0 1 1 0 1 intp110 0 0 1 1 1 0 intp111 0 0 1 1 1 1 intp112 0 1 0 0 0 0 intp113 0 1 0 0 0 1 intp120 0 1 0 0 1 0 intp121 0 1 0 0 1 1 intp122 0 1 0 1 0 0 intp123 0 1 0 1 0 1 intp130 0 1 0 1 1 0 intp131 0 1 0 1 1 1 intp132 0 1 1 0 0 0 intp133 0 1 1 0 0 1 intcmd0 0 1 1 0 1 0 intcmd1 0 1 1 0 1 1 intcmd2 0 1 1 1 0 0 intcmd3 0 1 1 1 0 1 intcsi0 0 1 1 1 1 0 intsr0 0 1 1 1 1 1 intst0 1 0 0 0 0 0 intcsi1 1 0 0 0 0 1 intsr1 1 0 0 0 1 0 intst1 1 0 0 0 1 1 intcsi2 1 0 0 1 0 0 intsr2 1 0 0 1 0 1 intst2 1 0 0 1 1 0 intad other than above setting prohibited 5 to 0 ifcn5 to ifcn0 remark n = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 215 the relationship between the dmarqn signa l and the interrupt source that serv es as a dma transfer trigger is as follows (n = 0 to 3). dmarqn ifcn0 to ifcn5 internal dma request signal interrupt source selector caution if a dmarqn pin is specified as the dma transfer start factor, clea r the dtfrn register to 00h. if an interrupt request is specified as the dma tr ansfer start factor, mask the dmarqn signal input on the port side (pmc0 register, etc.). in this case, an interrupt request will be generated with the start of dma transfer. to prevent an interrupt request from being genera ted, mask the interrupt by setting the interrupt request c ontrol register. dma transfer st arts even if an interrupt is masked. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 216 6.4 dma bus states 6.4.1 types of bus states the dmac bus states consis t of the following 13 states. (1) ti state the ti state is an idle state, duri ng which no access request is issued. the dmarq0 to dmarq3 signals are sampled at the rising edge of the clkout signal. (2) t0 state dma transfer ready state (state in which a dma transfe r request has been issued and the bus mastership is acquired for the first dma transfer). (3) t1r state the bus enters the t1r state at the beginning of a read operati on in the 2-cycle transfer mode. address driving starts. after entering the t1r st ate, the bus invariably enters the t2r state. (4) t1ri state the t1ri state is a state in whic h the bus waits for the acknowledge signal corresponding to an external memory read request. after entering the last t1ri state, t he bus invariably enters the t2r state. (5) t2r state the t2r state corresponds to the last state of a read operation in the 2-cycle transfer mode, or to a wait state. in the last t2r state, read data is sampled. after entering the last t2r state, the bus invariably enters the t1w state. (6) t2ri state state in which the bus is ready for dma transfer to on-chip peripheral i/o or inte rnal ram (state in which the bus mastership is acquired for dma transfer to on-chip peripheral i/o or internal ram). after entering the last t2ri state, t he bus invariably enters the t1w state. (7) t1w state the bus enters the t1w state at the beginning of a write operatio n in the 2-cycle transfer mode. address driving starts. after entering the t1w st ate, the bus invariably enters the t2w state. (8) t1wi state state in which the bus waits for the acknowledge signal corresponding to an external memory write request. after entering the last t1wi state, t he bus invariably enters the t2w state. (9) t2w state the t2w state corresponds to the last state of a write operation in the 2-cycle transfer mode, or to a wait state. in the last t2w state, the writ e strobe signal is made inactive. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 217 (10) t1fh state the basic flyby transfer state, this state corresponds to the tr ansfer execution cycle. after entering the t1fh state, the bus enters the t2fh state. (11) t1fhi state the t1fhi state corresponds to the la st state of a flyby transfer, durin g which the end of transfer is waited for. after entering the t1fhi state, the bus is released and enters the te state. (12) t2fh state the t2fh state is the state during which it is judged whether flyby transfer is to be continued or not. if the next transfer is executed in the block transfer mode, the bus enters the t1fh state after the t2fh state. under other conditions, the bus enters t he t1fhi state when a wait is issued. if no wait is issued, the bus is released and enters the te state. (13) te state the te state corresponds to dma transfer completion. va rious internal signals are initialized. after entering the te state, the bus invari ably enters the ti state. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 218 6.4.2 dmac bus cycle state transition except for the block transfer mode, each time the processi ng for a dma transfer is completed, the bus mastership is released. figure 6-1. dmac bus cycle state transition (a) 2-cycle transfer (b) flyby transfer ti t0 t1r t1ri t2r t1w t2w te ti t2ri t1wi ti t0 t1fh t2fh te ti t1fhi chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 219 6.5 transfer modes 6.5.1 single transfer mode in single transfer mode, the dmac releases the bus at eac h byte/halfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. if other dma transf er request with the lower priority occurs one clock after single transfer has been completed, however, this request does not take precedence even if the previous dma transfer request signal with the higher priority remains active. dma transfer with the lower priority newly request is executed after the cpu bus has been released. figures 6-2 to 6-5 show examples of single transfer. figure 6-2. single transfer example 1 cpu dmarq3 (input) cpu dma3 cpu dma3 cpu dma3 cpu cpu cpu cpu cpu cpu dma3 cpu dma3 cpu cpu cpu dma channel 3 terminal count note note note note note the bus is always released. figure 6-3 shows an example of a single transfer in which a higher priority dma request is issued. dma channels 0 to 2 are in the block transfer mode and channel 3 is in the single transfer mode. figure 6-3. single transfer example 2 cpu cpu cpu dma3 cpu dma0 dma0 cpu dma1 dma1 cpu dma2 dma2 cpu dma3 cpu dma3 dmarq3 (input) dmarq2 (input) dmarq1 (input) dmarq0 (input) dma channel 3 terminal count dma channel 0 terminal count dma channel 2 terminal count note note note note dma channel 1 terminal count note the bus is always released. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 220 figure 6-4 is an example of single transfer where a dma tr ansfer request with the lower priority is issued one clock after single transfer has been completed. dma channels 0 and 3 are used for single transfer. if two dma transfer request signals are asserted active at the same time, two dma transfer operations are alternately executed. figure 6-4. single transfer example 3 cpu cpu cpu dma0 dma0 cpu dma0 cpu dma0 cpu dma0 cpu cpu cpu dma0 cpu dma3 cpu dma3 dma channel 3 terminal count dma channel 0 terminal count dmarq3 (input) dmarq0 (input) note note note note note note note note the bus is always released. figure 6-5 is an example of single transfer where two or more dma transfer requests with the lower priority are issued one clock after single transfer has been completed. dma channels 0, 2, and 3 are used for single transfer. if three or more dma transfer request signals are asserted ac tive at the same time, two dma transfer operations are alternately executed, always starting fr om the one with the highest priority. figure 6-5. single transfer example 4 cpu dma3 cpu dma3 cpu dma2 cpu dma2 cpu dma2 cpu dma2 cpu dma3 cpu cpu cpu dma3 cpu dma0 cpu dma0 dma channel 0 terminal count dma channel 2 terminal count dma channel 3 terminal count dmarq2 (input) dmarq3 (input) dmarq0 (input) note note note note note note note note note note the bus is always released. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 221 6.5.2 single-step transfer mode in single-step transfer mode, the dmac releases the bus at each byte/halfword transfer. if there is a subsequent dma transfer request signal (dmarq0 to dmarq3), transfe r is performed again. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. the following shows an example of a single-step transfer. figure 6-7 shows an example of single-step transfer made in which a higher priority dma request is issued. dma channels 0 and 1 are in t he single-step transfer mode. figure 6-6. single-step transfer example 1 cpu cpu cpu dma1 cpu dma1 cpu dma1 cpu dma1 cpu cpu cpu cpu cpu cpu cpu dma channel 1 terminal count dmarq1 (input) note note note note the bus is always released. figure 6-7. single-step transfer example 2 cpu cpu cpu dma1 cpu dma1 cpu dma0 cpu dma0 cpu dma0 cpu dma1 cpu dma1 cpu dma channel 0 terminal count dma channel 1 terminal count dmarq1 (input) dmarq0 (input) note note note note note note note the bus is always released. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 222 6.5.3 block transfer mode in the block transfer mode, once transfer starts, the dm ac continues the transfer oper ation without releasing the bus until a terminal count occurs. no other dma requests are acknowledged during block transfer. after the block transfer ends and the dmac releases t he bus, another dma transfer can be acknowledged. the bus cycle of the cpu is not inserted during block transfer, but bus hold and refresh cycles are inserted in between dma transfer operations. the following shows an example of block transfer in which a higher priority dma request is issued. dma channels 2 and 3 are in the block transfer mode. figure 6-8. block transfer example cpu cpu cpu dma3 dma3 dma3 dma3 dma3 dma3 dma3 dma3 cpu dma2 dma2 dma2 dma2 dma2 dma channel 3 terminal count the bus is always released. dmarq3 (input) dmarq2 (input) chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 223 6.6 transfer types 6.6.1 2-cycle transfer in 2-cycle transfer, data transfer is performed in two cycles, a read cycle (source to dmac) and a write cycle (dmac to destination). in the first cycle, the source address is output and readin g is performed from the source to the dmac. in the second cycle, the destination address is output and writi ng is performed from the dmac to the destination. caution an idle cycle of 1 cl ock is always inserted between the read cycle and write cycle. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 224 figure 6-9. timing of access to sram, external rom, and external i/o during 2-cycle dma transfer (1/2) (a) sram external i/o (bcc register se tting for sram: bcn1, bcn0 = 00b) (bcc register setting for external i/o: bcn1, bcn0 = 00b) t1 t2 ti note t2 t1 a0 to a25 (output) d0 to d15 (i/o) dmarqx (input) clkout (output) bcyst (output) csn/rasm (output) of sram area csn/rasm (output) of external i/o area oe (output) rd (output) iord (output) iowr (output) wait (input) we (output) dmaakx (output) tcx (output) lbe (output) ube (output) lwr/lcas (output) uwr/ucas (output) address address data data note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 225 figure 6-9. timing of access to sram, external rom, and external i/o during 2-cycle dma transfer (2/2) (b) sram external i/o (bcc register se tting for sram: bcn1, bcn0 = 11b) (bcc register setting for external i/o: bcn1, bcn0 = 00b) t1 t2 a0 to a25 (output) d0 to d15 (i/o) dmarqx (input) clkout (output) bcyst (output) csn/rasm (output) of sram area csn/rasm (output) of external i/o area oe (output) rd (output) iord (output) iowr (output) wait (input) we (output) dmaakx (output) tcx (output) lbe (output) ube (output) lwr/lcas (output) uwr/ucas (output) ti note 2 ti note 1 ti note 1 ti note 1 t1 t2 address address data data notes 1. this idle state (ti) is inserted by means of a bcc register setting. 2. this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 226 figure 6-10. timing of 2-cycle dma transfer (external i/o sram) (a) single-step transfer mode ti ti ti ti ti note 1 to t1r t1 t2r t2 t1w t1 t2w t2 t1r t1 t2r tw t2r t2 ti note 1 t2w tw t1w t1 t2w t2 ti ti ti to csn (output) of sram area d0 to d15 (i/o) a0 to a25 (output) internal dma request signal dmarqx (input) clkout (output) bcyst (output) tcx (output) csm (output) of external i/o area oe (output) rd (output) iord (output) note 2 iowr (output) note 2 wait (input) we (output) data data h h dmaakx (output) lwr/lcas (output) uwr/ucas (output) address address address address data data notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. when the ioen bit of the bcp register is set to 1. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 0 to 7, x = 0 to 3 (n m) chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 227 figure 6-11. timing of 2-cycle dma transfer (sram edo dram) (1/3) (a) single transfer mode clkout (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma request signal bcyst (output) lcas (output) ucas (output) rasm (output) of dram area csn (output) of other area csn (output) of sram area rd (output) oe (output) we (output) lbe (output) ube (output) d0 to d15 (i/o) address row col. col. data ti ti ti ti to t1r t1w t2w t2w t2r ti ti t1 t2 t1 ti ti t1 ti t2 to t2 t1 t2 trpw note 2 note 2 t1w tcpw note 3 note 4 t2w tb t2 t1 t2 te tw ti tw data data data address te ti t1 t1r t1 t2r t2 data data data data note 1 note 1 notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. trpw and tcpw are always inserted for one or more cycles. 3. when a bus cycle accessing another cs space or a read cycle accessing the same cs space follows this write cycle. 4. in the case of the ras hold mode remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 228 figure 6-11. timing of 2-cycle dma transfer (sram edo dram) (2/3) (b) single-step transfer mode clkout (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma request singal bcyst (output) lcas (output) ucas (output) rd (output) oe (output) we (output) lbe (output) ube (output) d0 to d15 (i/o) address col. data ti ti ti ti to t1r t1w t2w t2w t2r ti ti t1 t2 t1 ti t1 ti t2 ti t2 t1 t2 trpw t1w tcpw note 3 note 4 t2w tb t2 t1 t2 te data data data address te ti t1 t1r t1 t2r t2 data data data data rasm (output) of dram area csn (output) of other area csn (output) of sram area note 2 note 2 note 1 note 1 row col. notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. trpw and tcpw are always inserted for one or more cycles. 3. when a bus cycle accessing another cs space or a read cycle accessing the same cs space follows this write cycle. 4. in the case of the ras hold mode remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 229 figure 6-11. timing of 2-cycle dma transfer (sram edo dram) (3/3) (c) block transfer mode clkout (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma request signal bcyst (output) lcas (output) ucas (output) rd (output) oe (output) we (output) lbe (output) ube (output) d0 to d15 (i/o) address data ti ti ti ti to t1r t1w t2w t2w t2r ti ti t1 t2 t1 t1 t2 trpw t1w tcpw note 3 note 4 t2w tb t2 t1 t2 te data data data address te t1r t1 t2r t2 data data note 2 note 2 rasm (output) of dram area csn (output) of other area csn (output) of sram area note 1 note 1 row col. col. notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. trpw and tcpw are always inserted for one or more cycles. 3. when a bus cycle accessing another cs space or a read cycle accessing the same cs space follows this write cycle. 4. in the case of the ras hold mode remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 230 figure 6-12. timing of 2-cycl e dma transfer (edo dram sram) (1/3) (a) single transfer mode clkout (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma request signal bcyst (output) lcas/lwr (output) ucas/uwr (output) rd (output) oe (output) we (output) lbe (output) ube (output) d0 to d15 (i/o) address data ti ti ti ti to t1r t2r t2r t1 t2 t1 t1w ti t1 t2w t2 to t2 ti t2 t2 trpw note 2 t1 t2 te tw ti tw data data data data address te ti t1 ti t1 t1r tb t2w t2 t1w t1 data data data rasm (output) of dram area csn (output) of other area csn (output) of sram area note 1 row col. col. notes 1. trpw is always inserted for one or more cycles. 2. in the case of the ras hold mode remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 231 figure 6-12. timing of 2-cycl e dma transfer (edo dram sram) (2/3) (b) single-step transfer mode clkout (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma request signal bcyst (output) lcas/lwr (output) ucas/uwr (output) rd (output) oe (output) we (output) lbe (output) ube (output) d0 to d15 (i/o) address data ti ti ti ti to t1r t2r t2r t1 t2 t1 t1w t1 t2w t2 ti t2 ti t2 t2 trpw note 2 t1 t2 te data data data data address te ti t1 ti t1 t1r tb t2w t2 t1w t1 data data data rasm (output) of dram area csn (output) of other area csn (output) of sram area note 1 row col. col. notes 1. trpw is always inserted for one or more cycles. 2. in the case of the ras hold mode remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 232 figure 6-12. timing of 2-cycl e dma transfer (edo dram sram) (3/3) (c) block transfer mode clkout (output) dmarqx (input) dmaakx (output) tcx (output) address (output) input dma request signal bcyst (output) lcas/lwr (output) ucas/uwr (output) rd (output) oe (output) we (output) lbe (output) ube (output) d0 to d15 (i/o) address data ti ti ti ti to t1r t2r t2r t1 t2 t1 t1w t1 t2w t2 t2 trpw note 3 t1 t2 te data data data data address te ti t1r tb t2w t2 t1w t1 data rasm (output) of dram area csn (output) of other area csn (output) of sram area note 1 row col. col. note 2 notes 1. trpw is always inserted for one or more cycles. 2. this idle state (ti) is independ ent of the bcc register setting. 3. in the case of the ras hold mode remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 233 figure 6-13. timing of 2-cycle dma transfer (sram sdram) (1/3) (a) single transfer mode sdclk (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma output signal bcyst (output) sdras (output) sdcas (output) rd (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d15 (i/o) address col. col. data h ti ti ti ti to t1r t1w t2w t2w t2r ti ti t1 t2 t1 ti ti t1 ti t2 to t2 t1 t2 tw t1w tw t2 tact twr t2w twr twe tw ti tw twpre data data data address t2w t2w twe twpre t2w t2w ti t1 t1r t1 t2r t2 data data data data csn (output) of other area csn (output) of sram area csn (output) of sdram area row note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 234 figure 6-13. timing of 2-cycle dma transfer (sram sdram) (2/3) (b) single-step transfer mode sdclk (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma request signal bcyst (output) sdras (output) sdcas (output) rd (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d15 (i/o) address col. col. data h ti ti ti ti to t1r t1w t2w t2w t2r ti ti t1 t2 t1 ti t1 ti t2 ti t2 t1 t2 tw t1w tw t2 tact twr t2w twr twe twpre data data data address t2w t2w twe twpre t2w t2w ti t1 t1r t1 t2r t2 data data data data csn (output) of other area csn (output) of sram area csn (output) of sdram area row note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 235 figure 6-13. timing of 2-cycle dma transfer (sram sdram) (3/3) (c) block transfer mode sdclk (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma request signal bcyst (output) sdras (output) sdcas (output) rd (output) we (output) ldqm (output) udqm (output) sdcke (output) d0 to d15 (i/o) address col. col. data h ti ti ti ti to t1r t1w t2w t2w t2r ti ti ti t1 t2 t1 t1 t2 tw t1w tw t2 tact twr t2w twr twe twpre data data data address t2w t2w twe twpre t2w t2w t1r t1 t2r t2 data data csn (output) of sdram area csn (output) of other area csn (output) of sram area row note note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 236 figure 6-14. timing of 2-cycle dma transfer (sdram sram) (1/3) (a) single transfer mode sdclk (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma request signal bcyst (output) sdras (output) sdcas (output) rd (output) we (output) ldqm/lwr (output) udqm/uwr (output) sdcke (output) d0 to d15 (i/o) address col. col. h ti ti ti ti to t1r t2r ti ti t1 t2 t1 ti ti t1 t1 ti t2 t2 to t2 t2 tw t1w tw tact tw ti tw data data address t1w tread t2r tlate t2r tlate t2r tread t2w tlate t2w tlate t2w t2w t1r t2r ti t1 t2 t1 data data data data data data csn (output) of other area csn (output) of sram area csn (output) of sdram area row note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 237 figure 6-14. timing of 2-cycle dma transfer (sdram sram) (2/3) (b) single-step transfer mode sdclk (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma request signal bcyst (output) sdras (output) sdcas (output) rd (outpur) we (output) sdcke (output) d0 to d15 (i/o) address col. col. h ti ti ti ti to t1r t2r ti ti t1 t2 t1 ti t1 t1 ti t2 t2 ti t2 t2 tw t1w tw tact data data address t1w tread t2r tlate t2r tlate t2r tread t2w tlate t2w tlate t2w t2w t1r t2r ti t1 t2 t1 data data data data data data csn (output) of other area csn (output) of sram area csn (output) of sdram area ldqm/lwr (output) udqm/uwr (output) row note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 238 figure 6-14. timing of 2-cycle dma transfer (sdram sram) (3/3) (c) block transfer mode sdclk (output) dmarqx (input) dmaakx (output) tcx (output) address (output) internal dma request signal bcyst (output) sdras (output) sdcas (output) rd (output) we (output) sdcke (output) d0 to d15 (i/o) address col. col. h ti ti ti ti to t1r t2r ti ti ti t1 t2 t1 t1 t2 t2 tw t1w tw tact data data address t1w tread t2r tlate t2r tlate t2r tread t2w tlate t2w tlate t2w t2w t1r t2r t2 t1 data data data data csn (output) of other area csn (output) of sram area csn (output) of sdram area ldqm/lwr (output) udqm/uwr (output) row note note note note this idle state (ti) is independ ent of the bcc register setting. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, x = 0 to 3 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 239 6.6.2 flyby transfer since data is transferred in 1 cycle during a flyby transfer, a memory address is always ou tput irrespective whether it is a source address or a destinati on address, and read/write signals of the memory and peripheral i/o become active at the same time. theref ore, the external i/o is selected by the dmaak0 to dmaak3 signals. to perform a normal access to the external i/o by means other than dma transfer, externally and the csm and dmaakx signals (m = 0 to 7, x = 0 to 3), and connect the result ant signal to the chip select signal of the external i/o. a circuit example of a normal access, other than dma transfer, to external i/o is shown below. figure 6-15. circuit example when flyby transfer is performed between external i/o and sram ax to axx d0 to d7 oe we csn sram ax to axx d8 to d15 oe we csn sram external i/o d0 to d15 rd wr cs ax to axx d0 to d15 rd lwr csn uwr v850e/ma1 iord csm iowr dmaakx remark n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 240 figure 6-16. timing of flyby transfer (dram external i/o) (1/3) (a) block transfer mode to ti ti ti ti t1fh note trpw t2fh t1 t1fh tf te tf te t2 t1fh tb t1fh tw a0 to a25 (output) d0 to d15 (i/o) dmarqx (input) clkout (output) bcyst (output) rasm (output) of dram area csn (output) of external i/o area oe (output) rd (output) iord (output) iowr (output) wait (input) we (output) internal dma request signal dmaakx (output) tcx (output) lwr/lcas (output) uwr/ucas (output) col. col. row data data h h h h note trpw is always inserted for one or more cycles. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 (n m) 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 241 figure 6-16. timing of flyby transfer (dram external i/o) (2/3) (b) single transfer mode ti ti ti ti to t2fh t1 t1fh t2 t2fh t1 t2fh t2 t1fh trpw ti ti ti ti te tf ti to ti t1fh trpw note note tf te csn (output) of external i/o area d0 to d15 (i/o) a0 to a25 (output) internal dma request signal dmarqx (input) clkout (output) bcyst (output) tcx (output) rasm (output) of dram area oe (output) rd (output) iord (output) iowr (output) wait (input) we (output) data dmaakx (output) lwr/lcas (output) uwr/ucas (output) data row col. row col. note trpw is always inserted for one or more cycles. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 (n m) 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 242 figure 6-16. timing of flyby transfer (dram external i/o) (3/3) (c) single-step transfer mode ti ti ti ti to t2fh t1 t1fh t2 t1fh tb ti ti ti te tf to t1fh trpw note ti tf ti te csn (output) of external i/o area d0 to d15 (i/o) a0 to a25 (output) internal dma request signal dmarqx (input) clkout (output) bcyst (output) tcx (output) rasm (output) of dram area oe (output) rd (output) iord (output) iowr (output) wait (input) we (output) dmaakx (output) lwr/lcas (output) uwr/ucas (output) data col. row col. data note trpw is always inserted for one or more cycles. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 (n m) 4. col.: column address row: row address chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 243 figure 6-17. timing of access to sram, external rom, and external i/o during dma flyby transfer (1/2) (a) sram external i/o tasw t1 address data wait (input) d0 to d15 (i/o) iowr (output) iord (output) lwr/lcas/ldqm (output) uwr/ucas/udqm (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) tf ti t2 when tasw and ti are inserted t1 t2 tf tw dmaakx (output) address data lbe (output) ube (output) remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 244 figure 6-17. timing of access to sram, external rom, and external i/o during dma flyby transfer (2/2) (b) external i/o sram tasw t1 address data wait (input) d0 to d15 (i/o) iowr (output) iord (output) note lwr/lcas/ldqm (output) uwr/ucas/udqm (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) tf t1 t2 when tasw is inserted tw tf t2 dmaakx (output) address data lbe (output) ube (output) note during dma flyby transfer, the rise timing of this read cycle is diffe rent from that of other transfer operations. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 245 figure 6-18. page rom access ti ming during dma flyby transfer (a) page rom external i/o t1 t2 address data wait (input) d0 to d15 (i/o) iowr (output) iord (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) ti t1 tf tw tf t2 dmaakx (output) address data h h h h h when ti is inserted remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 246 figure 6-19. dram access timing du ring dma flyby transfer (1/4) (a) dram external i/o (when no wait is inserted) trpw note 1 t1 column address row address data wait (input) d0 to d15 (i/o) iowr (output) iord note 2 (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) tf te t2 tb te tf dmaakx (output) column address data note 4 note 4 note 4 note 4 note 3 notes 1. trpw is always inserted for one or more cycles. 2. during dma flyby transfer, the rise timing of this read cycle is different from that of other transfer operations. 3. when a bus cycle accessing another cs space or a write cycle accessing the same cs space follows this cycle. 4. the rise timing of this write cycle is differe nt from that of a norma l edo dram write cycle. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 247 figure 6-19. dram access timing du ring dma flyby transfer (2/4) (b) dram external i/o (when trhw and tw are inserted) trpw note 1 t1 column address row address data wait (input) d0 to d15 (i/o) iowr (output) iord note 2 (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) t2 tw trhw t3 tcpw note 1 te to1 tw te to2 dmaakx (output) column address data note 3 note 4 note 4 note 4 note 4 notes 1. trpw and tcpw are always inserted for one or more cycles. 2. during dma flyby transfer, the rise timing of this read cycle is different from that of other transfer operations. 3. when a bus cycle accessing another cs space or a write cycle accessing the same cs space follows this cycle. 4. the rise timing of this write cycle is differe nt from that of a norma l edo dram write cycle. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 248 figure 6-19. dram access timing du ring dma flyby transfer (3/4) (c) external i/o dram (when no waits are inserted) trpw note 1 t1 column address row address data wait (input) d0 to d15 (i/o) iowr (output) iord note 2 (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) te tcpw note 1 t2 tb te dmaakx (output) column address data note 4 note 4 note 4 note 4 note 3 notes 1. trpw and tcpw are always inserted for one or more cycles. 2. during dma flyby transfer, the rise timing of this read cycle is different from that of other transfer operations. 3. when a bus cycle accessing another cs space or a write cycle accessing the same cs space follows this cycle. 4. the rise timing of this write cycle is differe nt from that of a norma l edo dram write cycle. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 249 figure 6-19. dram access timing du ring dma flyby transfer (4/4) (d) external i/o dram (when trhw an d tw are inserted) trpw note 1 t1 column address row address data wait (input) d0 to d15 (i/o) iowr (output) lwr/lcas (output) uwr/ucas (output) we (output) oe (output) rd (output) csn/rasm (output) bcyst (output) a0 to a25 (output) clkout (output) t2 tw trhw te tb tcpw note 1 te tw dmaakx (output) column address data iord note 2 (output) note 4 note 4 note 4 note 4 note 3 notes 1. trpw and tcpw are always inserted for one or more cycles. 2. during dma flyby transfer, the rise timing of this read cycle is different from that of other transfer operations. 3. when a bus cycle accessing another cs space or a write cycle accessing the same cs space follows this cycle. 4. the rise timing of this write cycle is differe nt from that of a norma l edo dram write cycle. remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 250 6.7 transfer targets 6.7.1 transfer type and transfer targets table 6-1 lists the relationships between tr ansfer type and transfer targets. the mark ? ? means ?transfer possible?, and the mark ? ? ? means ?transfer impossible?. table 6-1. relationship between tr ansfer type and transfer targets destination 2-cycle transfer flyby transfer internal rom on-chip peripheral i/o external i/o internal ram external memory internal rom on-chip peripheral i/o external i/o internal ram external memory on-chip peripheral i/o ? ? ? ? ? ? external i/o ? ? ? ? ? note internal ram ? ? ? ? ? ? ? external memory ? ? ? note ? ? source internal rom ? ? ? ? ? ? ? ? ? note in the case of flyby transfer, dat a cannot be transferred to/from sdram. cautions 1. the operation is not guaranteed for comb inations of transfer dest ination and source marked with ? ? ? in table 6-1. 2. in the case of flyby transfer, make the da ta bus width the same for the source and destination. 3. addresses between 3fff000h and 3ffffffh ca nnot be specified for the source and destination address of dma transfer. be sure to specify an address between ffff000h and fffffffh. remark 1. during 2-cycle dma transfer, if the data bus width of the transfer source and that of the transfer destination are different, the operation becomes as follows. if the object of the dma transfer is an on-chip peripheral i/o register (transfer source/transfer destination), be sure to specify the sa me transfer size as the register size. for example, in the case of dma transfer to an 8-bit register, be sure to specify byte (8-bit) transfer. <16-bit transfer> ? transfer from a 16-bit bus to an 8-bit bus a read cycle (16 bits) is generated and then a writ e cycle (8 bits) is generated twice consecutively. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated twice consecut ively and then a write cycle (16 bits) is generated. data is written in the order from lo wer bits to higher bits to the trans fer destination in the case of little endian and in reverse order in the case of big endian. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 251 <8-bit transfer> ? transfer from 16-bit bus to 8-bit bus a read cycle (the higher 8 bits go into a high-i mpedance state) is generated and then a write cycle (8 bits) is generated. ? transfer from 8-bit bus to 16-bit bus a read cycle (8 bits) is generated and then a wr ite cycle is generated (the higher 8 bits go into a high-impedance state). data is written in the order from lower bits to higher bits to the transfer destination in the case of little endian and in reverse order in the case of big endian. remark 2. transfer between the little endian area and the big endian area is possible. 6.7.2 external bus cycles during dma transfer the external bus cycles during dma transfer are shown below. table 6-2. external bus cycles during dma transfer transfer type transfer object external bus cycle on-chip peripheral i/o, internal ram none ? external i/o yes sram cycle 2-cycle transfer external memory yes memory acce ss cycle set by the bct register flyby transfer between external memory and external i/o yes dma flyby transfer cycle accessing memory that is set as external memory by the bct register 6.8 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 these priorities are valid in the ti state only. in the block transfer mode , the channel used for transfer is never switched. in the single-step transfer mode, if a higher priority dma tr ansfer request is issued while the bus is released (in the ti state), the higher priority dma transfer request is acknowledged. caution do not start two or more dma channels with the same factor. if two or more dma channels are started with the same factor, the dma channel with the lower priority may be accepted before the dma channel with the higher priority. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 252 6.9 next address setting function the dma source address registers (dsanh, dsanl), dm a destination address registers (ddanh, ddanl), and dma transfer count register (dbcn) are 2-stage fifo buffer registers consisting of a master register and a slave register (n = 0 to 3). when the terminal count is issued, these registers ar e automatically rewritten wit h the value that was set immediately before. therefore, during dma transfer, transfe r is automatically started when a new dma transfer setting is made for these registers and the enn bit of the dchcn register, a nd mlen bit is set to 1 (however, the dma transfer end interrupt may be issued even if dma transfer is automatically started). figure 6-20 shows the configurat ion of the buffer register. figure 6-20. buffer register configuration data read data write master register slave register address/ count controller internal bus the actual dma transfer is executed in accor dance with the contents of the slave register. the set values that are reflected in the master register and slave register differ as follows, depending on the timing (period) of setting the registers. (1) period from system reset to the genera tion of the first dma transfer request the set value is reflected in both t he master register and slave register. (2) during dma transfer (period from the gene ration to the end of dma transfer request) the set value is reflected only in the master register and not in the slave re gister (the slave register holds the set value for the next dma transfer). however, the contents of the master register are automatically overwritten to the slave register after completion of dma transfer. if the value of each regist er is read during this period, the value of the slave register is read. (3) period from the end of dma transfer to the beginning of the next dma transfer the set value is reflected in both t he master register and slave register. remark ?the end of dma transfer? means either of the following. ? completion of dma transfer (terminal count) ? forced termination of dma transfer (setting t he initn bit of the dchcn register to 1) chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 253 if the setting of a new dma transfer is made using th e dsanh, dsanl, ddanl, and dbcn registers during dma transfer, the values of the registers are aut omatically updated after completion of transfer note . note before setting a new dma transfer, confirm the start of the preceding dma transfer. if the setting of the new dma transfer is made befor e the start of the preced ing dma transfer, the new set value is overwritten to both the master register and slave register, and dma transfer according to the preceding set value cannot be executed. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 254 6.10 dma transfer start factors there are 3 types of dma transfer start factors, as shown below. cautions 1. do not use two or more start factors ((1) to (3)) in combin ation for the same channel (if two or more start factors are generated at the same ti me, only one of them is valid, but the valid start factor cannot be identified). the operation is not guarant eed if two or more start fact ors are used in combination. 2. if dma transfer is started via request fr om software and if the software does not correctly detect whether the expected dma transfer operation has been completed through manipulation (setting to 1) of the stgn bit of the dchcn register, it cannot be guaranteed whether the next (second) manipulation of the st gn bit corresponds to the start of ?the next dma transfer expected by software? (n = 0 to 3). for example, suppose single transfer is starte d by manipulating the stgn bit. even if the stgn bit is manipulated next (the second time) without checking by software whether the single transfer has actually b een executed, the next (second) dma transfer is not always executed. this is because the stgn bit may be manipulated th e second time before the first dma transfer is started or completed because , for example, dma transfer with a higher priority had already been started when the stgn bit was manipulated for the first time. it is therefore necessary to manipulate the stgn bit next time (the second time) after checking whether dma transfer started by the fi rst manipulation of th e stgn bit has been completed. completion of dma transfer can be checked in th e following ways. ? detecting the acknowledge signal (dmaakn) or terminal count signal (tcn) by using a peripheral port or interrupt ? checking the contents of the dbcn register chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 255 (1) request from an external pin (dmarqn) requests from the dmarqn pin are sampled each time the clkout signal rises (n = 0 to 3). hold the request from dmarqn pin until the corresponding dmaakn si gnal becomes active. if a state whereby the enn bit of the dchcn register = 1 and the tcn bit = 0 is set, the dmarqn signal in the ti state becomes valid. if the dmarqn signal set by th e dtfrn register becomes acti ve in the ti state, it changes to the t0 state and dma transfer is started. (2) request from software if the stgn, enn, and tcn bits of t he dchcn register are set as follows, dma transfer starts (n = 0 to 3). ? stgn bit = 1 ? enn bit = 1 ? tcn bit = 0 (3) request from on-chip peripheral i/o if, when the enn and tcn bits of the dchcn register are set as shown below, an interrupt request is issued from the on-chip peripheral i/o that is set in the dtfrn register, dma transfer starts (n = 0 to 3). ? enn bit = 1 ? tcn bit = 0 remark since the dmarqn signal is level-sampled and no t edge-detected, to enable edge detection of a dma request, set an external interrupt request for the dma start trigger instead of using the dmarqn signal (n = 0 to 3). chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 256 6.11 terminal count output upon dma transfer end the terminal count signal (tcn) becomes active for one cl ock during the last dma transfer cycle (n = 3 to 0). the tcn signal becomes active in the clock following the clock in which the bcyst signal becomes active during the last dma transfer cycle. figure 6-21. terminal count signal (tcn) timing example (1) cpu cpu dman dman dman cpu cpu dmarqn (input) tcn (output) dma channel n terminal count remark n = 0 to 3 the tcn signal becomes active for one clock at the beginni ng of the write cycle of t he last dma transfer when 2- cycle transfer is executed. when flyby transfer is executed, the tcn signal becomes active for one clo ck at the beginning of the last dma transfer cycle. figure 6-22. terminal count signal (tcn) timing example (2) (1) 2-cycle transfer read cycle 2-cycle transfer (last) write cycle clkout (output) tcn (output) (2) flyby transfer flyby transfer cycle (last) clkout (output) tcn (output) remark n = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 257 6.12 forcible suspension dma transfer can be forcibly suspended by nmi input during dma transfer. at such a time, the dmac resets the enn bit of the dc hcn register of all channels to 0 and the dma transfer disabled state is entered. an nmi request can then be ac knowledged after the dma transfer that was being executed when the nmi was input is complete (n = 0 to 3). forcibly terminate and initialize dma by us ing the initn bit of the dchcn register. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 258 6.13 forcible termination dma transfer can be forcibly terminated by the initn bi t of the dchcn register, in addition to the forcible suspension operation by means of nmi input (n = 0 to 3). an example of forcible termination by the initn bit of the dchcn register is illustrated below (n = 0 to 3). figure 6-23. example of forcible termination of dma transfer (a) block transfer through dma channel 3 is st arted during block transfer through dma channel 2 cpu cpu cpu cpu dma2 dma2 dma2 dma2 dma2 cpu dma3 dma3 dma3 dma3 cpu cpu cpu dmarq2 (input) dmarq3 (input) dma channel 3 transfer start dma channel 3 terminal count forcible termination of dma channel 2 transfer, bus released dsa2, dda2, dbc2, dadc2, dchc2 register set dchc2 (init2 bit = 1) register set dsa3, dda3, dbc3, dadc3, dchc3 register set e22 bit = 1 tc2 bit = 0 e22 bit 0 tc2 bit = 0 e33 bit = 1 tc3 bit = 0 e33 bit 0 tc3 bit 1 (b) when transfer is aborted dur ing dma channel 1 block transfer, and transfer under another condition is executed cpu cpu cpu cpu dma1 dma1 dma1 dma1 dma1 dma1 cpu cpu cpu cpu dma1 dma1 dma1 cpu dmarq1 (input) forcible termination of dma channel 1 transfer, bus released dma channel 1 terminal count dsa1, dda1, dbc1, dadc1, dchc1 register set dadc1, dchc1 register set dchc1 (init1 bit = 1) register set dsa1, dda1, dbc1 register set e11 bit = 1 tc1 bit = 0 e11 bit 0 tc1 bit = 0 e11 bit 1 tc1 bit = 0 e11 bit 0 tc1 bit 1 remark the values of the dsan, ddan, and dbcn regi sters (n = 0 to 3) are retained even when dma transfer is forcibly stopped, because these regist ers are fifo-format buffer registers. the next transfer condition can be set to these registers even while dma transfer is in progress. on the other hand, the setting of the dadcn and dchcn register s is invalid during dma transfer because these registers are not buffer registers (see 6.9 next address setting function , 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) , and 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) ). chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 259 6.13.1 restriction related to dm a transfer forcible termination when terminating a dma transfer by setting the initn bi t of the dchcn register, the transfer may not be terminated, but just suspended, even though the initn bit is se t to 1. as a result, when the dma transfer of a channel that should have been terminated is resumed, the dm a transfer will terminate after an unexpected number of transfers are completed and a dma transfer completion interrupt may occur (n = 0 to 3). [preventive measures] this problem can be avoided by implement ing any of the following workarounds. (1) stop all transfers from dma channels temporarily the following measure is effective if the program does not assume that th e tcn bit of the dchcn register is 1 except for the following workaround processing. (since the tcn bit of the dchcn register is cleared to 0 when it is read, execution of procedur e (ii) under step <5> clears this bit.) <1> disable interrupts (di state). <2> read the dma restart register (drst) and transfe r the enn bit of each channel to a general-purpose register (value a). <3> write 00h to the dma restart register (drst) twice note . by executing this twice, the dma transfer is definitely stopped before proceeding to <4>. <4> set the initn bit of the dchcn register of the channel to be forcibly terminated to 1. <5> perform the following operations for value a read in step <2> (value b). (i) clear the bit of the channel to be forcibly terminated to 0 (ii) if the tcn of the dchcn register and enn bit of the drst register of a channel that is not terminated forcibly are 1 (and makes 1), clear the bits of the channel to 0. <6> write value b in <5> to the drst register. <7> enable interrupts (ei state). note execute this three times if the transfer target (tr ansfer source or transfer destination) is the internal ram. caution be sure to execute step <5> to prevent the enn bit of the drst register from being set illegally for channels that ar e terminated normally during the period of steps <2> and <3>. remark n = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 260 (2) repeat setting the initn bit of the dchcn register until forcible termination of dma transfer is completed normally the procedure is shown below. <1> copy the initial transfer count of the channel to be forcibly terminated to a general-purpose register. <2> set the initn bit of the dchcn register of the channel to be forcibly terminated to 1. <3> read the value of dma transfer count register n (d bcn) of the channel to be forcibly terminated, and compare that value with the value copied in step <1>. if the two values do not match, repeat steps <2> and <3>. cautions 1. if the dbcn register is read in step <3>, and if dma transfer is stopped due to trouble, the remaining number of transfers will be read . if dma transfer has been forcibly terminated correctly, the initial number of transfers will be read. 2. with this procedure, it may take some ti me for the channel in question to be forcibly terminated in an application in which dma tran sfer of a channel other than that to be forcibly terminated is frequently executed. remark n = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 261 6.14 times related to dma transfer the overhead before and after dma transfer and minimum ex ecution internal system clock for dma transfer are shown below. in the case of external memory access, t he time depends on the type of external memory connected. table 6-3. number of minimum execution internal system clocks in dma cycle dma cycle number of minimum exec ution internal system clocks <1> time to respond to dma re quest 4 internal system clocks note 1 external memory access differs depending on the memory connected internal ram access 2 in ternal system clocks note 2 <2> memory access peripheral i/o register access 4 internal system clocks + number of wait cycles specified by vswc register notes 1. if an external interrupt (intpn) is specified as a fact or of starting dma transfer, noise elimination time is added (n = 000, 001, 010, 011, 020, 021, 030, 031, 100 to 103, 110 to 113, 120 to 123, or 130 to 133). 2. two clocks are required for the dma cycle. the minimum execution internal syst em clock in the dma cycle in each transfer mode is as follows. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note + transfer destination memory access (<2>) block transfer: dma response time (<1>) + (transfer source memory access (<2>) + 1 note + transfer destination memory access (<2>)) number of transfers note one internal system clock is always inserted bet ween the read cycle and writ e cycle of dma transfer. 6.15 response time for dma transfer request 6.15.1 example of respon se time for dma request caution the wait time under the fo llowing conditi ons is excluded. ? occurrence of other dma transfer with higher priority ? external bus hold chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 262 (1) example 1 condition instruction fetch from an exte rnal memory in 8-bit data bus width response time tinst 4 + tref dmaakn (output) d0 to d15 (i/o) dmarqn (input) dma cycle refresh fetch (1/4) fetch (2/4) fetch (3/4) fetch (4/4) remark n = 0 to 3 (2) example 2 condition word data access with an exte rnal memory in 8-bit data bus width response time tdata 4 + tref dmaakn (output) d0 to d15 (i/o) dmarqn (input) dma cycle refresh data (1/4) data (2/4) data (3/4) data (4/4) remark n = 0 to 3 (3) example 3 condition instruction fetch from an exte rnal memory in 8-bit data bus width execution of a bit manipulation in struction (set1, clr1, or not1) response time tinst 8 + tdata 2 + tref dmaakn (output) d0 to d15 (i/o) dmarqn (input) dma cycle refresh data write data read fetch (32 bits) note fetch (32 bits) note note the actual cycle is as follows. fetch (4/4) fetch (3/4) fetch (2/4) fetch (1/4) remarks 1. tinst: number of clocks per bus cycle during inst ruction fetch tdata: number of clocks per bus cycle dur ing data access tref: number of clocks per refresh cycle 2. n = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 263 6.15.2 maximum response time for dma transfer request the response time for a dma transfer request becom es the longest under the following conditions. caution the wait time under the fo llowing conditi ons is excluded. ? occurrence of other dma transfer with higher priority ? external bus hold condition instruction fetch from external memory with 8-bit data bus width execution of bit manipulation inst ruction (set1, clr1, or not1) instruction next to bit manipulation instructi on is branch instruction (jr, jarl, bcond, jmp) either dma transfer source or destination is internal ram response time tinst 16 + tdata 2 + tref 4 dmaakn (output) d0 to d15 (i/o) dmarqn (input) data read fetch (32 bits) note 1, 2 fetch (32 bits) note 1, 2 dma cycle refresh note 3 fetch (32 bits) note 1, 2 fetch (32 bits) note 1, 2 data write notes 1. the actual cycle is as follows. fetch (4/4) fetch (3/4) fetch (2/4) fetch (1/4) 2. 8-bit bus width: eight bus cycles 16-bit bus width: four bus cycles 3. refresh occurs as many times as the number of drams connected (up to four). remarks 1. tinst: number of clocks per bus cycle during inst ruction fetch tdata: number of clocks per bus cycle dur ing data access tref: number of clocks per refresh cycle 2. n = 0 to 3 chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 264 6.16 cautions (1) memory boundary the transfer operation is not guarant eed if the source or the destination address exceeds the area of dma objects (external memory, internal ram, or on-chip peripheral i/o) during dma transfer. (2) transfer of misaligned data dma transfer of 16-bit bus width misaligned data is not su pported. if the source or the destination address is set to an odd address, the lsb of the address is forcibly handled as "0". (3) bus arbitration for cpu when an external device is targeted for dma transfe r, the cpu can access the internal rom and internal ram (if they are not subject to dma transfer). when dma transfer is executed betw een the on-chip per ipheral i/o and internal ram, the cpu can access the internal rom. (4) holding dmarqn signal be sure to keep the dmarqn signal active until the dmaakn signal becomes active (n = 0 to 3). (5) dmaakn signal output when the transfer object is internal ram, the dmaakn signal is not output during a dma cycle for internal ram (for example, if 2-cycle transfer is performed fr om internal ram to an external memory, the dmaakn signal is output only during a dma writ e cycle for the external memory). if the transfer object is the on-chip peripheral i/o, the dmaakn signal is output even in the dma cycle executed on the on- chip peripheral i/o. (6) dma start factors do not start two or more dma channels with the same factor. if two or more dma channels are started with the same factor, the dma channel with the lower prio rity may be accepted before the dma channel with the higher priority. (7) program execution and dma transfer with internal ram do not execute dma transfer to/from the internal ram a nd an instruction in the internal ram simultaneously. (8) restrictions related to automatic clearing of tcn bit of dchcn register the tcn bit of the dchcn register is automatically cleared to 0 when it is read. when dma transfer is executed to transfer data to or from the internal ram when two or more dma transfer channels are simultaneously used, the tcn bit may not be cleared even if it is read after completion of dma transfer (n = 0 to 3). caution this restriction does not apply if one of the following conditions is satisfied. ? only one channel of dma transfer is used. ? dma is not executed to transfer da ta to or from the internal ram. [preventive measures] to read the tcn bit of the dchcn regi ster of the dma channel that is us ed to transfer data to or from the internal ram, be sure to read the tcn bit three times in a row. this can accurately clear the tcn bit to 0. chapter 6 dma functions (dma controller) user?s manual u14359ej5v1ud 265 (9) read values of dsan and ddan registers if the values of the dsan and ddan registers are read during dma transfer, the values in the middle of being updated may be read (n = 0 to 3). for example, if the dsanh register and the dsanl regist er are read in that order when the value of the dma transfer source address (dsa n register) is ?0000ffffh? an d the counting direction is incremental (when the sadn1 and sadn0 bits of the dadcn register = 00), t he value of the dsanl register differs as follows depending on whether dma transfer is executed immedi ately after the dsanh register has been read. (a) if dma transfer does not occur while the dsan register is being read <1> reading dsanh register: dsanh = 0000h <2> reading dsanl register: dsanl = ffffh (b) if dma transfer occurs while the dsan register is being read <1> reading dsanh register: dsanh = 0000h <2> occurrence of dma transfer <3> incrementing dsan register : dsan = 00010000h <4> reading dsanl register: dsanl = 0000h 6.16.1 suspension factors dma transfer is suspended if the following factors are issued. ? bus hold ? refresh cycle if the factor that is suspending dma transfer is no longer valid, dma transfer promptly restarts. 6.17 dma transfer end when dma transfer ends and the tcn bit of the dchcn register is set to 1, a dma transfer end interrupt (intdman) is issued to the interrupt controller (intc) (n = 0 to 3). user?s manual u14359ej5v1ud 266 chapter 7 interrupt/exception processing function the v850e/ma1 has an on-chip interrupt controller (intc) that can process a total of 50 interrupt request sources. an interrupt is an event that occu rs independently of program execution, and an except ion is an event whose occurrence is dependent on program execution. the v850e/ma1 can process interrupt requests from t he on-chip peripheral hardwar e and external sources. moreover, exception processing can be st arted by the trap instruction (softwar e exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 7.1 features { interrupts non-maskable interrupts: 1 source caution p20 is fixed to nmi input. if the p20 bit of the p2 register is read, th e level of the nmi pin is read, regardless of the values of the pm2 and pmc2 registers. set the valid edge of the nmi pin by using ext ernal interrupt mode regi ster 0 (intm0) (default value: rising edge detection). maskable interrupts: 49 sources 8 levels of programmable priorities (maskable interrupts) multiple interrupt control according to priority masks can be specified for each maskable interrupt request. noise elimination, edge detection, and valid edge specification for ex ternal interrupt request signals. { exceptions software exceptions: 32 sources exception traps: 2 sources (illegal opcode exception and debug trap) interrupt/exception sources ar e listed in table 7-1. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 267 table 7-1. interrupt/exception source list (1/2) interrupt/exception source type classification name controlling register generating source generating unit default priority exception code handler address restored pc reset interrupt reset ? reset input ? ? 0000h 00000000h undefined non-maskable interrupt nmi0 ? nmi input ? ? 0010h 00000010h nextpc exception trap0n note ? trap instruction ? ? 004nh note 00000040h nextpc software exception exception trap1n note ? trap instruction ? ? 005nh note 00000050h nextpc exception trap exception ilgop/ dbg0 ? illegal opcode/ dbtrap instruction ? ? 0060h 00000060h nextpc interrupt intov00 ovic00 timer 00 ov erflow rpu 0 0080h 00000080h nextpc interrupt intov01 ovic01 timer 01 ov erflow rpu 1 0090h 00000090h nextpc interrupt intov02 ovic02 timer 02 ov erflow rpu 2 00a0h 000000a0h nextpc interrupt intov03 ovic03 timer 03 ov erflow rpu 3 00b0h 000000b0h nextpc interrupt intp000/ intm000 p00ic0 match of intp000 pin/ccc00 pin/rpu 4 00c0h 000000c0h nextpc interrupt intp001/ intm001 p00ic1 match of intp001 pin/ccc01 pin/rpu 5 00d0h 000000d0h nextpc interrupt intp010/ intm010 p01ic0 match of intp010 pin/ccc10 pin/rpu 6 00e0h 000000e0h nextpc interrupt intp011/ intm011 p01ic1 match of intp011 pin/ccc11 pin/rpu 7 00f0h 000000f0h nextpc interrupt intp020/ intm020 p02ic0 match of intp020 pin/ccc20 pin/rpu 8 0100h 00000100h nextpc interrupt intp021/ intm021 p02ic1 match of intp021 pin/ccc21 pin/rpu 9 0110h 00000110h nextpc interrupt intp030/ intm030 p03ic0 match of intp030 pin/ccc30 pin/rpu 10 0120h 00000120h nextpc interrupt intp031/ intm031 p03ic1 match of intp031 pin/ccc31 pin/rpu 11 0130h 00000130h nextpc interrupt intp100 p10ic0 intp100 pin pin 12 0140h 00000140h nextpc interrupt intp101 p10ic1 intp101 pin pin 13 0150h 00000150h nextpc interrupt intp102 p10ic2 intp102 pin pin 14 0160h 00000160h nextpc interrupt intp103 p10ic3 intp103 pin pin 15 0170h 00000170h nextpc interrupt intp110 p11ic0 intp110 pin pin 16 0180h 00000180h nextpc interrupt intp111 p11ic1 intp111 pin pin 17 0190h 00000190h nextpc interrupt intp112 p11ic2 intp112 pin pin 18 01a0h 000001a0h nextpc interrupt intp113 p11ic3 intp113 pin pin 19 01b0h 000001b0h nextpc interrupt intp120 p12ic0 intp120 pin pin 20 01c0h 000001c0h nextpc interrupt intp121 p12ic1 intp121 pin pin 21 01d0h 000001d0h nextpc interrupt intp122 p12ic2 intp122 pin pin 22 01e0h 000001e0h nextpc interrupt intp123 p12ic3 intp123 pi n pin 23 01f0h 000001f0h nextpc interrupt intp130 p13ic0 intp130 pin pin 24 0200h 00000200h nextpc interrupt intp131 p13ic1 intp131 pin pin 25 0210h 00000210h nextpc interrupt intp132 p13ic2 intp132 pin pin 26 0220h 00000220h nextpc interrupt intp133 p13ic3 intp133 pin pin 27 0230h 00000230h nextpc interrupt intcmd0 cmicd0 cmd0 matc h signal rpu 28 0240h 00000240h nextpc maskable interrupt intcmd1 cmicd1 cmd1 matc h signal rpu 29 0250h 00000250h nextpc chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 268 table 7-1. interrupt/exception source list (2/2) interrupt/exception source type classification name controlling register generating source generating unit default priority exception code handler address restored pc interrupt intcmd2 cmicd2 cmd2 matc h signal rpu 30 0260h 00000260h nextpc interrupt intcmd3 cmicd3 cmd3 matc h signal rpu 31 0270h 00000270h nextpc interrupt intdma0 dmaic0 end of dma0 transfer dma 32 0280h 00000280h nextpc interrupt intdma1 dmaic1 end of dma1 transfer dma 33 0290h 00000290h nextpc interrupt intdma2 dmaic2 end of dma2 transfer dma 34 02a0h 000002a0h nextpc interrupt intdma3 dmaic3 end of dma3 transfer dma 35 02b0h 000002b0h nextpc interrupt intcsi0 csiic0 csi0 transmission/ reception completion sio 36 02c0h 000002c0h nextpc interrupt intser0 seic0 uart0 recepti on error sio 37 02d0h 000002d0h nextpc interrupt intsr0 sric0 uart0 reception completion sio 38 02e0h 000002e0h nextpc interrupt intst0 stic0 uart0 transmission completion sio 39 02f0h 000002f0h nextpc interrupt intcsi1 csiic1 csi1 transmission/ reception completion sio 40 0300h 00000300h nextpc interrupt intser1 seic1 uart1 recepti on error sio 41 0310h 00000310h nextpc interrupt intsr1 sric1 uart1 reception completion sio 42 0320h 00000320h nextpc interrupt intst1 stic1 uart1 transmission completion sio 43 0330h 00000330h nextpc interrupt intcsi2 csiic2 csi2 transmission/ reception completion sio 44 0340h 00000340h nextpc interrupt intser2 seic2 uart2 recepti on error sio 45 0350h 00000350h nextpc interrupt intsr2 sric2 uart2 reception completion sio 46 0360h 00000360h nextpc interrupt intst2 stic2 uart2 transmission completion sio 47 0370h 00000370h nextpc maskable interrupt intad adic end of a/d c onversion adc 48 0380h 00000380h nextpc note n = 0 to fh remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, t he value of the pc saved when an interrupt is acknowledged during divide instruction (div, divh, divu, divhu) execution is the value of the pc of the current instruction (div, divh, divu, divhu). nextpc: the pc value that starts the processing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 269 7.2 non-maskable interrupts a non-maskable interrupt request is acknowledged unconditi onally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupts. a non-maskable interrupt request is input from the nmi pi n. when the valid edge specif ied by bit 0 (esn0) of external interrupt mode register 0 (intm0) is detected at the nmi pin, the interrupt occurs. while the service program of the non-maskable interrupt is being execut ed, the acknowledgem ent of another non- maskable interrupt request is held pending. the pending nmi is acknowledged after the original service program of the non-maskable interrupt under execution has been terminated (by the reti instructi on). note that if two or more nmi requests are input during the exec ution of the service program for an nmi, the number of nmis that will be acknowledged after reti instru ction execution is only one. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 270 7.2.1 operation if a non-maskable interrupt is generated, the cpu performs the following proce ssing, and transfers control to the handler routine: <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes exception code 0010h to the higher halfword (fecc) of ecr. <4> sets the np and id bits of the psw and clears the ep bit. <5> sets the handler address (00000010h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non-mask able interrupt is shown in figure 7-1. figure 7-1. servicing configurat ion of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h 1 0 1 00000010h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 271 figure 7-2. acknowledging non -maskable interrupt request (a) if a new nmi request is generated while an nmi ser vice program is being executed main routine nmi request nmi request (psw.np = 1) nmi request is held pending regardless of the value of the np bit of psw. pending nmi request serviced (b) if a new nmi request is generated twice while an nmi service program is being executed main routine nmi request nmi request held pending because nmi service program is being serviced only one nmi request is acknowledged even though two nmi requests are generated nmi request held pending because nmi service program is being serviced chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 272 7.2.2 restore execution is restored from the non-maskable inte rrupt servicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. <1> restores the values of the pc and the psw from fepc and fepsw, res pectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. <2> transfers control back to the address of the restored pc and psw. figure 7-3 illustrates how the reti instruction is processed. figure 7-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the psw.ep bit and psw.np bit ar e changed by the ldsr instruction during non- maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 273 7.2.3 non-maskable interrupt status flag (np) the np flag is a status flag that i ndicates that non-maskable interrupt (nmi ) servicing is under execution. this flag is set when an nmi interrupt has been acknowl edged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 7 np nmi pending indicates whether nmi interrupt servicing is in progress. 0: no nmi interrupt servicing 1: nmi interrupt currently being serviced 7.2.4 noise elimination nmi pin noise is eliminated with analog delay. the delay ti me is 60 to 300 ns. a signal input that changes within the delay time is not internally acknowledged. 7.2.5 edge detection function (1) external interrupt m ode register 0 (intm0) external interrupt mode register 0 (intm0) is a register that spec ifies the valid edge of a non-maskable interrupt (nmi). the nmi valid edge can be specified to be either t he rising edge or the falling edge by the esn0 bit. this register can be read/written in 8-bit or 1-bit units. address fffff880h 7 0 intm0 6 0 5 0 4 0 3 0 2 0 1 0 <0> esn0 after reset 00h bit position bit name function 0 esn0 edge select nmi specifies the nmi pin?s valid edge. 0: falling edge 1: rising edge chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 274 7.3 maskable interrupts maskable interrupt requests can be ma sked by interrupt control register s. the v850e/ma1 has 49 maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight le vels of priorities can be spec ified by using the interrupt control registers (programmable priority control). when an interrupt request has been ackno wledged, the acknowledgement of other maskable interrupt requests is disabled and the interrupt disabled (di) status is set. when the ei instruction is ex ecuted in an interrupt service routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a hi gher priority than the interrupt request in progress (specified by the interrupt control register). note that only in terrupts with a higher priority will have th is capability; interrupts with the same priority level cannot be nested. however, if multiple interrupts are exec uted, the following processing is necessary. <1> save eipc and eipsw in memory or a general-purpos e register before executi ng the ei instruction. <2> execute the di instruct ion before executing the reti instruction, then reset ei pc and eipsw with the values saved in <1>. 7.3.1 operation if a maskable interrupt occurs by int input, the cpu perfo rms the following processing, and transfers control to a handler routine: <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the id bit of the psw and clears the ep bit. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the servicing configurati on of a maskable interrupt is shown in figure 7-4. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 275 figure 7-4. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc accepted yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address note for the ispr register, see 7.3.6 in-service prio rity register (ispr) . the int input masked by the interrupt controllers and the int input that o ccurs while another interrupt is being serviced (when psw.np = 1 or psw.id = 1) are held pending internally by the interrupt controller. in such case, if the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 as set by the reti and ldsr instructions, input of the pending int starts the new ma skable interrupt servicing. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 276 7.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is execut ed, the cpu performs the following steps , and transfers control to the address of the restored pc. <1> restores the values of the pc and the psw from eipc and eipsw bec ause the ep bit of the psw is 0 and the np bit of the psw is 0. <2> transfers control to the address of the restored pc and psw. figure 7-5 illustrates the processi ng of the reti instruction. figure 7-5. reti instruction processing note for the ispr register, see 7.3.6 in-service prio rity register (ispr) . caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 277 7.3.3 priorities of maskable interrupts the v850e/ma1 provides multiple inte rrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority leve l control: control based on the default priority leve ls, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn ) of the interrupt control register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupts ar e serviced in order depending on the priority level allocated to each interrupt request type (default priority level) befor ehand. for more information, refer to table 7-1 interrupt/exception source list . the programmable priority control cu stomizes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is a cknowledged, the id flag of psw is automat ically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing t he ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ). chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 278 figure 7-6. example of processing in which anot her interrupt request is issued while an interrupt is bei ng serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 279 figure 7-6. example of processing in which anot her interrupt request is issued while an interrupt is bei ng serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 280 figure 7-7. example of servicing inte rrupt requests simult aneously generated default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. nmi request caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remark a to c in the figure are the temporary names of in terrupt requests shown for the sake of explanation. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 281 7.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each in terrupt request (maskable inte rrupt) and sets the control conditions for each maskable interrupt request. this register can be read/written in 8-bit or 1-bit units. caution read the xxifn bit of the xxicn register in the interrupt disable d (di) state. otherwise if the timing of interrupt acknowledgeme nt and bit reading conflict, normal values may not be read. address fffff110h to ffff170h <7> xxifn xxicn <6> xxmkn 5 0 4 0 3 0 2 xxprn2 1 xxprn1 0 xxprn0 after reset 47h bit position bit name function 7 xxifn interrupt request flag this is an interrupt request flag. 0: interrupt request not issued 1: interrupt request issued the flag xxlfn is reset automatically by the hardware if an interrupt request is acknowledged. 6 xxmkn mask flag this is an interrupt mask flag. 0: interrupt servicing enabled 1: interrupt servicing disabled (pending) priority 8 levels of priority order ar e specified for each interrupt. xxprn2 xxprn1 xxprn0 interrupt priority specification bit 0 0 0 specifies level 0 (highest). 0 0 1 specifies level 1. 0 1 0 specifies level 2. 0 1 1 specifies level 3. 1 0 0 specifies level 4. 1 0 1 specifies level 5. 1 1 0 specifies level 6. 1 1 1 specifies level 7 (lowest). 2 to 0 xxprn2 to xxprn0 remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ). the addresses and bits of the interrupt control registers are as follows: chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 282 table 7-2. address and bits of interrupt control register (1/2) bit address register <7> <6> 5 4 3 2 1 0 fffff110h ovic00 ovif00 ovmk00 0 0 0 ovpr002 ovpr001 ovpr000 fffff112h ovic01 ovif01 ovmk01 0 0 0 ovpr012 ovpr011 ovpr010 fffff114h ovic02 ovif02 ovmk02 0 0 0 ovpr022 ovpr021 ovpr020 fffff116h ovic03 ovif03 ovmk03 0 0 0 ovpr032 ovpr031 ovpr030 fffff118h p00ic0 p00if0 p00mk0 0 0 0 p00pr02 p00pr01 p00pr00 fffff11ah p00ic1 p00if1 p00mk1 0 0 0 p00pr12 p00pr11 p00pr10 fffff11ch p01ic0 p01if0 p01mk0 0 0 0 p01pr02 p01pr01 p01pr00 fffff11eh p01ic1 p01if1 p01mk1 0 0 0 p01pr12 p01pr11 p01pr10 fffff120h p02ic0 p02if0 p02mk0 0 0 0 p02pr02 p02pr01 p02pr00 fffff122h p02ic1 p02if1 p02mk1 0 0 0 p02pr12 p02pr11 p02pr10 fffff124h p03ic0 p03if0 p03mk0 0 0 0 p03pr02 p03pr01 p03pr00 fffff126h p03ic1 p03if1 p03mk1 0 0 0 p03pr12 p03pr11 p03pr10 fffff128h p10ic0 p10if0 p10mk0 0 0 0 p10pr02 p10pr01 p10pr00 fffff12ah p10ic1 p10if1 p10mk1 0 0 0 p10pr12 p10pr11 p10pr10 fffff12ch p10ic2 p10if2 p10mk2 0 0 0 p10pr22 p10pr21 p10pr20 fffff12eh p10ic3 p10if3 p10mk3 0 0 0 p10pr32 p10pr31 p10pr30 fffff130h p11ic0 p11if0 p11mk0 0 0 0 p11pr02 p11pr01 p11pr00 fffff132h p11ic1 p11if1 p11mk1 0 0 0 p11pr12 p11pr11 p11pr10 fffff134h p11ic2 p11if2 p11mk2 0 0 0 p11pr22 p11pr21 p11pr20 fffff136h p11ic3 p11if3 p11mk3 0 0 0 p11pr32 p11pr31 p11pr30 fffff138h p12ic0 p12if0 p12mk0 0 0 0 p12pr02 p12pr01 p12pr00 fffff13ah p12ic1 p12if1 p12mk1 0 0 0 p12pr12 p12pr11 p12pr10 fffff13ch p12ic2 p12if2 p12mk2 0 0 0 p12pr22 p12pr21 p12pr20 fffff13eh p12ic3 p12if3 p12mk3 0 0 0 p12pr32 p12pr31 p12pr30 fffff140h p13ic0 p13if0 p13mk0 0 0 0 p13pr02 p13pr01 p13pr00 fffff142h p13ic1 p13if1 p13mk1 0 0 0 p13pr12 p13pr11 p13pr10 fffff144h p13ic2 p13if2 p13mk2 0 0 0 p13pr22 p13pr21 p13pr20 fffff146h p13ic3 p13if3 p13mk3 0 0 0 p13pr32 p13pr31 p13pr30 fffff148h cmicd0 cmif0 cmmk0 0 0 0 cmpr02 cmpr01 cmpr00 fffff14ah cmicd1 cmif1 cmmk1 0 0 0 cmpr12 cmpr11 cmpr10 fffff14ch cmicd2 cmif2 cmmk2 0 0 0 cmpr22 cmpr21 cmpr20 fffff14eh cmicd3 cmif3 cmmk3 0 0 0 cmpr32 cmpr31 cmpr30 fffff150h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff152h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff154h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff156h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff158h csiic0 csiif0 csimk0 0 0 0 csipr02 csipr01 csipr00 chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 283 table 7-2. address and bits of interrupt control register (2/2) bit address register <7> <6> 5 4 3 2 1 0 fffff15ah seic0 seif0 semk0 0 0 0 sepr02 sepr01 sepr00 fffff15ch sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff15eh stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff160h csiic1 csiif1 csimk1 0 0 0 csipr12 csipr11 csipr10 fffff162h seic1 seif1 semk1 0 0 0 sepr12 sepr11 sepr10 fffff164h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff166h stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff168h csiic2 csiif2 csimk2 0 0 0 csipr22 csipr21 csipr20 fffff16ah seic2 seif2 semk2 0 0 0 sepr22 sepr21 sepr20 fffff16ch sric2 srif2 srmk2 0 0 0 srpr22 srpr21 srpr20 fffff16eh stic2 stif2 stmk2 0 0 0 stpr22 stpr21 stpr20 fffff170h adic adif admk 0 0 0 adpr2 adpr1 adpr0 chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 284 7.3.5 interrupt mask register s 0 to 3 (imr0 to imr3) these registers set the interrupt mask state for the maskable interrupts. t he xxmkn bit of the imr0 to imr3 registers is equivalent to the xxm kn bit of the xxicn register. the imrm register (m = 0 to 3) can be read/written in 16-bit units. if the higher 8 bits of the imrm regist er are used as an imrmh register and t he lower 8 bits as an imrml register, these registers can be read/writt en in 8-bit or 1-bit units. bits 15 to 1 of the imr3 register (bits 7 to 0 of the imr3h register and bits 7 to 1 of the imr3l register) are fixed to 1. if these bits are not 1, the operation c annot be guaranteed. caution the device file defines the xxmkn bit of th e xxicn register as a reser ved word. if a bit is manipulated using the name of xxmkn, the contents of the xxicn register , instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten). address fffff100h 15 p10mk3 imr0 14 p10mk2 13 p10mk1 12 p10mk0 11 p03mk1 10 p03mk0 9 p02mk1 8 p02mk0 7 p01mk1 6 p01mk0 5 p00mk1 4 p00mk0 3 ovmk3 2 ovmk2 1 ovmk1 0 ovmk0 after reset ffffh address fffff102h 15 cmmk3 imr1 14 cmmk2 13 cmmk1 12 cmmk0 11 p13mk3 10 p13mk2 9 p13mk1 8 p13mk0 7 p12mk3 6 p12mk2 5 p12mk1 4 p12mk0 3 p11mk3 2 p11mk2 1 p11mk1 0 p11mk0 after reset ffffh address fffff104h 15 stmk2 imr2 14 srmk2 13 semk2 12 csimk2 11 stmk1 10 srmk1 9 semk1 8 csimk1 7 stmk0 6 srmk0 5 semk0 4 csimk0 3 dmamk3 2 dmamk2 1 dmamk1 0 dmamk0 after reset ffffh address fffff106h 15 1 imr3 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 admk after reset ffffh bit position bit name function 15 to 0 (imr0 to 2), 0 (imr3) xxmkn mask flag interrupt mask flag 0: interrupt servicing enabled 1: interrupt servicing disabled (pending) remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ) chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 285 7.3.6 in-service priori ty register (ispr) this register holds the priority leve l of the maskable interrupt currently a cknowledged. when an interrupt request is acknowledged, the bit of this register co rresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the inte rrupt request having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only in 8-bit or 1-bit units. caution in the interrupt enabled (ei) state, if an interrupt is acknowle dged during the reading of the ispr register, the value of the ispr register may be read after the bit is set (1) by this interrupt acknowledgement. to read the value of the ispr register properly before interrupt acknowledgement, read it in the interrupt disabled (di) state. address fffff1fah <7> ispr7 ispr <6> ispr6 <5> ispr5 <4> ispr4 <3> ispr3 <2> ispr2 <1> ispr1 <0> ispr0 after reset 00h bit position bit name function 7 to 0 ispr7 to ispr0 in-service priority flag indicates priority of interrupt currently acknowledged 0: interrupt request with priority n not acknowledged 1: interrupt request with priority n acknowledged remark n = 0 to 7 (priority level) chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 286 7.3.7 maskable interrupt status flag (id) the id flag is bit 5 of the psw and c ontrols the maskable interr upt?s operating state, and st ores control information regarding enabling or disabling of interrupt requests. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 5 id interrupt disable indicates whether maskable interrupt servicing is enabled or disabled. 0: maskable interrupt request acknowledgement enabled 1: maskable interrupt request acknowledgement disabled (pending) this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupt requests and exc eptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request generated during t he acknowledgement disabled period (id = 1) is acknowledged when the xxifn bit of xxicn is set to 1, and the id flag is reset to 0. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 287 7.3.8 noise elimination the noise of the intpn, intpm, and ti000 to ti030 pins is eliminated wit h analog delay (n = 000, 001, 010, 011, 020, 021, 030, 031, m = 103 to 100, 113 to 110, 123 to 120, and 133 to 130). the delay time is about 60 to 220 ns. a signal input that changes within the delay time is not internally acknowledged. 7.3.9 interrupt trigger mode selection the valid edge of pins intp0n0, intp0n1, intp1nm, ad trg, and ti0n0 can be selected by program. moreover, a level trigger can be selected for the intp1nm pin (n = 0 to 3, m = 0 to 3). the edge that can be selected as the valid edge is one of the following. ? rising edge ? falling edge ? both the rising and falling edges when the intp0n0, intp0n1, intp1nm, adtrg, and ti0n0 pins are edge-detected, they become interrupt sources and capture trigger, a/d trigger, and timer exte rnal count inputs (n = 0 to 3, m = 0 to 3). the valid edge is specified by external interrupt mode registers 1 to 4 (i ntm1 to intm4) and valid edge select registers (sesc0 to sesc3). the level tr igger is specified by external interr upt mode registers 1 to 4 (intm1 to intm4). (1) external interrupt mode registers 1 to 4 (intm1 to intm4) these registers specify t he trigger mode for external interrupt requests (intp100 to intp103, intp110 to intp113, intp120 to intp122, intp123/adtrg, intp130 to intp133), input via external pins. the correspondence between each register and t he external interrupt requests that register controls is shown below. ? intm1: intp100 to intp103 ? intm2: intp110 to intp113 ? intm3: intp120 to intp122, intp123/adtrg ? intm4: intp130 to intp133 intp123 is the alternate function pin of the a/d converter external trigger input (adtrg). therefore, when intp123/adtrg is set to the external trigger mode by the trg0 to trg2 bits of the a/d converter mode register (adm), the es1231 and es1230 bi ts specify the valid edge of the ex ternal trigger input (adtrg). the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). these registers can be read/ written in 8-bit units. caution before setting the intp1nm or adtrg pi n in the trigger mode, set the pmcn register. if the pmcx register is set after the intm 1 to intm4 registers have been set, an illegal interrupt may occur depending on the timing of se tting the pmcn register (n = 0 to 3, m = 0 to 3, x = 0, 2, or 3). chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 288 address fffff882h 7 es1031 intm1 6 es1030 5 es1021 4 es1020 3 es1011 2 es1010 1 es1001 0 76543210 76543210 76543210 es1000 after reset 00h address fffff884h intm2 after reset 00h address fffff886h intm3 after reset 00h address fffff888h intm4 after reset 00h es1331 es1330 es1321 es1320 es1311 es1310 es1301 es1300 es1131 es1130 es1121 es1120 es1111 es1110 es1101 es1100 es1231 es1230 es1221 es1220 es1211 es1210 es1201 es1200 intp103 intp102 intp101 intp100 intp113 intp112 intp111 intp110 intp123/adtrg intp122 intp121 intp120 intp133 intp132 intp131 intp130 bit position bit name function edge select specifies the valid edge of the intp1nm and adtrg pins. es1nm1 es1nm0 operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2, 3 1 1 both rising and falling edges 7 to 0 es1nm1, es1nm0 (n = 0 to 3, m = 0 to 3) notes 1. the level of the intp1nm pin is sampled at the interval of the system clock divided by two, and the p1nifm bit is latched as an interrupt request when a low level is detected. therefore, even if the p1nifm bit of the interrupt cont rol register (p1nicm) is automat ically cleared to 0 when the cpu acknowledges an interrupt, the p1nifm bit is i mmediately set to 1, and an interrupt is generated continuously. to avoid this, forcibly clear the p1ni fm bit to 0 after making the intp1nm pin inactive for an external device in the interrupt serv ice routine (n = 0 to 3, m = 0 to 3). 2. when a lower priority level-detection interrupt r equest (intp1nm) occurs while another interrupt is being serviced and this newly generated level-detecti on interrupt request becomes inactive before the current interrupt service is complete, this new interrupt request (intp1nm) is held pending. to avoid acknowledging this intp1nm interrupt request, clear the p1nifm bit of the interrupt control register (n = 0 to 3, m = 0 to 3). 3. when this pin is used as the adtrg pin, do not select this setting (level detection). chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 289 (2) valid edge select register s c0 to c3 (sesc0 to sesc3) these registers specify the valid edge for external interrupt requests (intp000, intp001, intp010, intp011, intp020, intp021, intp030, intp031, ti000 to ti030) , input via external pins. the correspondence between each register and the external interrupt requests that regist er controls is shown below. ? sesc0: ti000, intp000, intp001 ? sesc1: ti010, intp010, intp011 ? sesc2: ti020, intp020, intp021 ? sesc3: ti030, intp030, intp031 the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). these registers can be read/ written in 8-bit units. cautions 1. when using the intp0n0/ti0n0 or intp 0n1 pin as intp0n0, intp0n 1, be sure to preset the tmccaen bit of timer mode control regist er cn0 (tmccn0) to 1 (n = 0 to 3). 2. before setting the ti0n0, intp0n1, or in tp0n0 pin in the trigger mode, set the pmcx register. if the pmcx register is set after the sesc0 to sesc3 registers have been set, an illegal interrupt may occur depending on the timing of se tting the pmcx register (n = 0 to 3, x = 0, 1, 2, or 5). chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 290 address fffff609h 7 tes01 sesc0 6 tes00 5 0 4 0 3 ies0011 2 ies0010 1 es0001 0 76543210 76543210 76543210 ies0000 after reset 00h address fffff619h sesc1 after reset 00h address fffff629h sesc2 after reset 00h address fffff639h sesc3 after reset 00h tes31 tes30 0 0 ies0311 ies0310 ies0301 ies0300 tes11 tes10 0 0 ies0111 ies0110 ies0101 ies0100 tes21 tes20 0 0 ies0211 ies0210 ies0201 ies0200 ti000 intp001 intp000 ti010 intp011 intp010 ti020 intp021 intp020 ti030 intp031 intp030 bit position bit name function 7, 6 tesn1, tesn0 (n = 0 to 3) edge select specifies the valid edge of the intpn and ti000 to ti030 pins. xesn1 xesn0 operation 0 0 falling edge 3, 2 iesn1, iesn0 (n = 001, 011, 021, 031) 0 1 rising edge 1 0 rfu (reserved) 1 1 both rising and falling edges 1, 0 iesn1, iesn0 (n = 000, 010, 020, 030) chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 291 7.4 software exception a software exception is generated when the cpu ex ecutes the trap instru ction, and can always be acknowledged. 7.4.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfe rs control to the handler routine: <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the ep and id bits of the psw. <5> sets the handler address (00000040h or 00000050h) corre sponding to the software exception to the pc, and transfers control. figure 7-8 illustrates the processi ng of a software exception. figure 7-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 00h to 1fh) the handler address is determined by the trap instruction?s operand (vector). if the vector is 00h to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 292 7.4.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instru ction, the cpu carries out the following pr ocessing and shifts control to the restored pc?s address. <1> loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. <2> transfers control to the address of the restored pc and psw. figure 7-9 illustrates the processi ng of the reti instruction. figure 7-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is n ecessary to set psw.ep back to 1 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 293 7.4.3 exception status flag (ep) the ep flag is bit 6 of the psw, and is a st atus flag used to indicate that except ion processing is in progress. it is set when an exception occurs. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 6 ep exception pending shows that exception processing is in progress. 0: exception processing not in progress. 1: exception processing in progress. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 294 7.5 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instructi on takes place. in the v850e/ma1, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 7.5.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an in struction applicable to this illegal instruction is executed. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution since it is possible to assign this instru ction to an illegal opcode in the future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the follo wing processing, and transfers control to the handler routine: <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep, and id bits of the psw. <4> sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. figure 7-10 illustrates the proce ssing of the exception trap. chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 295 figure 7-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore recovery from an exception trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 7-11 illustrates the restore pr ocessing from an exception trap. figure 7-11. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 296 7.5.2 debug trap the debug trap is an exception that can be acknowledged every time and is generated by exec ution of the dbtrap instruction. when the debug trap is generat ed, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep and id bits of the psw. <4> sets the handler address (00000060h) corresponding to the debug trap to the pc and transfers control. figure 7-12 illustrates the pr ocessing of the debug trap. figure 7-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h debug monitor routine processing cpu processing chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 297 (2) restore recovery from a debug trap is carried out by the dbret in struction. by executi ng the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 7-13 illustrates the restor e processing from a debug trap. figure 7-13. restore processing from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 298 7.6 multiple interrupt servicing control multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is acknowledged and serviced first. if there is an interrupt request with a lower priority leve l than the interrupt request cu rrently being serviced, that interrupt request is held pending. multiple interrupt servicing control of maskable interr upts is executed when interrupt s are enabled (id = 0). thus, to execute multiple interrupts, it is necessary to set t he interrupt enabled state (id = 0) even for an interrupt service routine. if maskable interrupts are enabled or a software excepti on is generated in a maskable interrupt or software exception service program, it is necessary to save eipc and eipsw. this is accomplished by the following procedure. (1) acknowledgement of maskable interrupts in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (inte rrupt acknowledgement enabled) ... ... maskable interrupt acknowledgement ... ... ? di instruction (interr upt acknowledgement disabled) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 299 (2) generation of exception in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ... ? trap instruction exception such as trap instruction acknowledged. ... ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction the priority order for multiple interr upt servicing control has 8 levels, fr om 0 to 7 for each maskable interrupt request (0 is the highest priority), but it can be set as desired via software. the priority order is set using the xxprn0 to xxprn2 bits of the interr upt control request register (xxlcn), provided for each maskable interrupt request. after system reset, an interrupt request is masked by the xxmkn bit and the priority order is set to level 7 by the xxprn0 to xxprn2 bits. the priority order of maskable interrupts is as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been sus pended as a result of multiple servic ing control is resumed after the servicing of the higher priority interrupt has been co mpleted and the reti instru ction has been executed. a pending interrupt request is acknowledged after the cu rrent interrupt servici ng has been completed and the reti instruction has been executed. caution in a non-maskable interrupt service routin e (time until the reti instruction is executed), maskable interrupts are susp ended and not acknowledged. remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ) chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 300 7.7 interrupt latency time the v850e/ma1 interrupt latency time (from interrupt request generation to start of interrupt servicing) is described below. figure 7-14. pipeline operation at inte rrupt request acknowledgement (outline) if if id ex df wb ifx ifx idx if if id ex int1 int2 int3 int4 internal clock instruction 1 instruction 2 interrupt acknowledgement operation instruction (start instruction of interrupt service routine) interrupt request 4 system clocks interleave access note note for interleave access, refer to 8.1.2 2-clock branch in v850e1 user?s manual architecture (u14559e) . remark int1 to int4: interrupt acknowledgement processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt latency time (internal system clock) external interrupt internal interrupt intp0nm intp1nm condition minimum 4 7 + analog delay time 4 + analog delay time maximum 7 note 10 + analog delay time 7 + analog delay time the following cases are exceptions. ? in idle/software stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to on-chip peripheral i/o register note when ld instruction is executed to the internal rom (during align access) remark n = 0 to 3, m = 0, 1 chapter 7 interruption/exception processing function user?s manual u14359ej5v1ud 301 7.8 periods in which interrupts are not acknowledged an interrupt is acknowledged while an instruction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruct ion (interrupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the command register (prcmd) ? the load, store, or bit manipulation in structions for the following registers. ? interrupt-related registers: interrupt control register (xxicn), interrupt mask registers 0 to 3 (imr0 to imr3), in-service priority register (ispr), power-save control register (psc) ? csi-related registers: clocked serial interface clock selection registers 0 to 2 (csic0 to csic2), clocked serial interface mode registers 0 to 2 (csim0 to csim2), serial i/o shift registers 0 to 2 (sio0 to sio2), receive-only serial i/o shift regist ers 0 to 2 (sioe0 to sioe2), clocked serial interface transmit buffer registers 0 to 2 (sotb0 to sotb2) remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ) user?s manual u14359ej5v1ud 302 chapter 8 prescaler unit (prs) the prescaler divides the internal system clock and supplies the divided clock to internal peripheral units. the divided clock differs depending on the unit. for the timer units and a/d converter, a 2-division clock is input. for other units, the input clock is sele cted using that unit?s control register. the cpu operates with the internal system clock. user?s manual u14359ej5v1ud 303 chapter 9 clock generation function the clock generator (cg) generates and controls t he internal system clock (f xx ) that is supplied to each internal unit, such as the cpu. 9.1 features ? multiplication function using phase locked loop (pll) synthesizer ? clock sources ? oscillation by connecting a resonator ? external clock ? power-save control ? halt mode ? idle mode ? software stop mode ? internal system clock output function 9.2 configuration x1 x2 clock generator (cg) cksel (f x ) cpu, on-chip peripheral i/o time base counter (tbc) clkout remark f x : external resonator or external clock frequency chapter 9 clock generation function user?s manual u14359ej5v1ud 304 9.3 input clock selection the clock generator consists of an oscillator and a pll synthesizer. for example, connecting a 5.0 mhz crystal resonator or ceramic resonator to pins x1 and x2 enables a 50 mhz internal system clock (f xx ) to be generated when multiplied by 10. also, an external clock can be input directly to the oscillat or. in this case, the clock signal should be input only to the x1 pin (the x2 pin should be left open). two basic operation modes are provided for the clock g enerator. these are pll mode and direct mode. the operation mode is selected by the cksel pin. the input to this pin is latched on reset. cksel operating mode 0 pll mode 1 direct mode caution the input level for the cksel pin must be fixed. if it is switched during operation, malfunction may occur. 9.3.1 direct mode in direct mode, an external clock with twice the frequency of the internal system clock is input. the maximum frequency that can be input in direct mode is 50 mhz. t he v850e/ma1 is mainly used in application systems in which it is operated at relatively low frequencies. caution in direct mode, an external clock must be input (an external resonator should not be connected). chapter 9 clock generation function user?s manual u14359ej5v1ud 305 9.3.2 pll mode in pll mode, an external resonator is connected or an external clock is input and multiplied by the pll synthesizer. the multiplied pll output is divided by the divisi on ratio specified by the clock control register (ckc) to generate a system clock that is 10, 5, 2.5, or 1 times the frequency of the ex ternal resonator or external clock (f x ). after reset, an internal system clock (f xx ) that is the same frequency as the internal clock frequency (f x ) (1 f x ) is generated. when a frequency that is 10 times the input clock frequency (f x ) (10 f x ) is generated, a system with low noise and low power consumption can be realized because a frequency of up to 50 mhz is obtained based on a 5 mhz external resonator or external clock. in pll mode, if the clock supply from an external resonator or external clock source stops, operation of the internal system clock (f xx ) based on the free-running frequency of the clock generator?s internal voltage controlled oscillator (vco) continues. however, do not devise an application method expecting to use this free-running frequency. example: clock when pll mode (f xx = 10 f x ) is used system clock frequency (f xx ) external resonator or external clock frequency (f x ) 50.000 mhz 5.0000 mhz 40.000 mhz 4.0000 mhz caution when in pll mode, only an f x (4 to 5 mhz) value for which 10 f x does not exceed the system clock maximum frequency (50 mhz) can be used for the oscillati on frequency or external clock frequency. however, if any of 5 f x , 2.5 f x , or 1 f x is used, a frequency of 4 to 6.6 mhz can be used. remark if the v850e/ma1 does not need to be operated at high frequency, when pll mode is selected a power consumption can be reduced by loweri ng the system clock frequency using software (f xx = 5 f x , f xx = 2.5 f x , or f xx = 1 f x ). 9.3.3 peripheral command register (phcmd) this is an 8-bit register that is used to set protection for writing to registers that can significantly affect the system so that the application system is not halted unexpectedly due to an inadvertent program loop. this register is write- only in 8-bit units (when it is read, undefined data is read out). writing to the first specific register (ckc or flpmc regist er) is only valid after first writing to the phcmd register. because of this, the register value can be overwritten on ly with the specified sequence, preventing an illegal write operation from being performed. 7 6 5 4 3 2 1 0 address after reset phcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 fffff800h undefined bit position bit name function 7 to 0 reg7 to reg0 registration code (arbitrary 8-bit data) the specific registers targeted are as follows. ? clock control register (ckc) ? flash programming mode control register (flpmc) the generation of an illegal store oper ation can be checked with the prerr bit of the peripheral status register (phs). chapter 9 clock generation function user?s manual u14359ej5v1ud 306 9.3.4 clock control register (ckc) the clock control register is an 8-bit register that controls the internal system clock (f xx ) in pll mode. it can be written to only by a specific sequence combination so that it cannot easily be overwritten by mistake due to an inadvertent program loop. this register can be read or written in 8-bit units. caution do not change bits ckdi v2 to ckdiv0 in direct mode. 7 6 5 4 3 2 1 0 address after reset ckc 0 0 tbcs cesel 0 ckdiv2 ckdiv1 ckdiv0 fffff822h 00h bit position bit name function 5 tbcs time base count select selects the time base counter clock. 0: f x /2 8 1: f x /2 9 for details, see 9.6.2 time base counter (tbc) . 4 cesel crystal/external select specifies the functions of the x1 and x2 pins. 0: a resonator is connected to the x1 and x2 pins 1: an external clock is connected to the x1 pin when cesel = 1, the oscillator feedback loop is disconnected to prevent current leak in software stop mode. clock divide sets the internal system clock (f xx ) when pll mode is used. ckdiv2 ckdiv1 ckdiv0 internal system clock (f xx ) 0 0 0 f x 0 0 1 2.5 f x 0 1 1 5 f x 1 1 1 10 f x other than above setting prohibited 2 to 0 ckdiv2 to ckdiv0 to change the internal system clock freque ncy in the middle of an operation, be sure to set it to f x first, and then change the frequency as desired. example clock generator settings ckc register operation mode cksel pin ckdiv2 ckdiv0 ckdiv0 input clock (f x ) internal system clock (f xx ) direct mode high-level input 0 0 0 16 mhz 8 mhz 0 0 0 5 mhz 5 mhz 0 0 1 5 mhz 12.5 mhz 0 1 1 5 mhz 25 mhz pll mode low-level input 1 1 1 5 mhz 50 mhz other than above setting pr ohibited setting prohibited chapter 9 clock generation function user?s manual u14359ej5v1ud 307 set data in the clock control regist er (ckc) in the following sequence. <1> disable interrupts (set the np bit of psw to 1) <2> prepare data in any one of the general-purpose registers to set in the specific register. <3> write data to the peripheral command register (phcmd) <4> set the clock control register (c kc) (with the following instruction). ? store instruction (st/sst instruction) <5> assert the nop instructions (5 instructions (<5> to <9>)) <10> release the interrupt disabled state (set the np bit of psw to 0). [sample coding] <1> ldsr rx, 5 <2> mov 0x07, r10 <3> st.b r10, phcmd [r0] <4> st.b r10, ckc [r0] <5> nop <6> nop <7> nop <8> nop <9> nop <10> ldsr ry, 5 remark rx: value written to psw ry: value returned to psw no special sequence is required to read the specific register. cautions 1. if an interrupt is acknowledged between the issuance of data to the phcmd (<3>) and writing to the specific register immediately after (<4>), the write operation to the specific register is not performed and a protection erro r (the prerr bit of the phs register = 1) may occur. therefore, set the np bit of the psw to 1 (<1>) to disable interrupt acknowledgement. also disable interrupt acknowle dgement when selecting a bit ma nipulation instruction for the specific register setting. 2. although the data written to the phcmd re gister is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the phcmd register (<3>). the same method should be applied when using a ge neral-purpose register for addressing. 3. be sure to terminate all dma transfers prior to the execution of the above sequence. chapter 9 clock generation function user?s manual u14359ej5v1ud 308 9.3.5 peripheral status register (phs) if a write operation to the protection-targeted internal r egisters is not performed in the correct sequence, including access to the command register, writing is not performed and a protection error is generated, setting the status flag (prerr) to 1. this flag is a cumulati ve flag. after checking the prerr flag , it is cleared to 0 by an instruction. this register can be read or written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 <0> address after reset phs 0 0 0 0 0 0 0 prerr fffff802h 00h bit position bit name function 0 prerr protection error 0: protection error has not occurred 1: protection error occurred the operating conditions of the prerr flag are as follows. set conditions: <1> if the operation of t he relevant store instruction for the on-chip peripheral i/o is not a write operation for the phcmd register, but the peri pheral specific register is written to. <2> if the first store instruction operation after the write operation to the phcmd register is for memory other than the specific registers and on-chip peripheral i/o. reset conditions: <1> if the prerr flag of the phs register is set to 0. <2> if the system is reset chapter 9 clock generation function user?s manual u14359ej5v1ud 309 9.4 pll lockup the lockup time (frequency stabilization time) is the time from when the power is turned on or software stop mode is released until the phase locks at the prescribed frequen cy. the state until this stabilization occurs is called the unlocked state, and the stabilized state is called the locked state. (1) lock register (lockr) the lock register (lockr) has a lock flag that re flects the stabilized stat e of the pll frequency. this register is read-only in 8-bit or 1-bit units. caution if the phase is locked, the lo ck flag is cleared to 0. if it is unlocked later because of a standby status, the lock flag is set to 1. if the phase is unlocked by a cause other than the standby status, however, the lock flag is not affected (lock = 0). 7 6 5 4 3 2 1 <0> address after reset lockr 0 0 0 0 0 0 0 lock fffff824h 0000000xb bit position bit name function 0 lock lock status flag this is a read-only flag that indicates the p ll lock state. this flag holds the value 0 as long as a lockup state is maintained and is not initialized by a system reset. 0: indicates that the pll is locked. 1: indicates that the pll is not locked (unlock state). if the clock stops, the power fails, or some other factor operates to cause an unlock state to occur, for control processing that depends on software execution speed, such as real-time processing, be sure to judge the lock flag by software immediately after operation begi ns so that processing does not begin until after the clock stabilizes. on the other hand, static processing such as the setting of internal hardware or the initialization of register data or memory data can be executed witho ut waiting for the lock flag to be reset. the relationship between the oscillation stabilization time (the time from w hen the resonator starts to oscillate until the input waveform stabilizes) when a resonator is used, and the pll lockup time (the time until frequency stabilizes) is shown below. oscillation stabilization time < pll lockup time. chapter 9 clock generation function user?s manual u14359ej5v1ud 310 9.5 power-save control 9.5.1 overview the power-save function has the following three modes. (1) halt mode in this mode, the clock generator (oscillator and pl l synthesizer) continues to operate, but the cpu?s operation clock stops. since the supply of clocks to on-chip peripheral functions other than the cpu continues, operation continues. the power consumption of the overall system can be reduced by intermittent operation using a combination of the ha lt mode and the normal operation mode. the system is switched to halt mode by a specific instruct ion (the halt instruction). (2) idle mode in this mode, the clock generator (oscillator and pll synthesizer) continues to oper ate, but the supply of internal system clocks is stopped, which causes the overall system to stop. when the system is released from idle mode, it can be switched to normal operation mode quickly because the oscillator?s oscillation stabilizat ion time does not need to be secured. the system is switched to idle mode by a psmr register setting. idle mode is located midway between software stop mode and halt mode in relation to the clock stabilization time and power consumption. it is used fo r situations in which a low-power-consumption mode is to be used and the clock stabilization time is to be eliminated after the mode is released. (3) software stop mode in this mode, the overall system is stopped by stopping the cl ock generator (oscillator and pll synthesizer). the system enters an ultra-low-power-consumption state in which only leakage current is lost. the system is switched to software st op mode by a psmr register setting. (a) pll mode the system is switched to software stop mode by setting the register us ing software. the pll synthesizer?s clock output is stopped at the same time the oscillator is stopped. after software stop mode is released, the oscillator?s oscillation stabiliz ation time must be secured until the system clock stabilizes. also, pll lockup time may be required depending on the program. when a resonator or external clock is connected, following the release of the software stop mode, execution of the program is started after the count time of the time base counter has elapsed. (b) direct mode to stop the clock, set the x1 pin to low level. after the release of software stop mode, execution of the program is started after the count time of the time base counter has elapsed. chapter 9 clock generation function user?s manual u14359ej5v1ud 311 figure 9-1 shows the operati on of the clock generator in normal operation mode, halt mode, idle mode, and software stop mode. an effective low power consumption system can be r ealized by combining these modes and switching modes according to the required use. figure 9-1. power-save mode state transition diagram normal operation mode software stop mode set stop mode idle mode set idle mode release according to reset, nmi, or maskable interrupt note set halt mode release according to reset, nmi, or maskable interrupt halt mode release according to reset, nmi, or maskable interrupt note note intp1nn (n = 0 to 3) when level detection is specified for the intp1nn pin, software stop mode and idle mode cannot be released. table 9-1. clock generator oper ation using power-save control clock source power-save mode oscillator pll synthesizer clock supply to peripheral i/o clock supply to cpu normal operation halt mode ? idle mode ? ? oscillation with resonator software stop mode ? ? ? ? normal operation ? halt mode ? ? idle mode ? ? ? pll mode external clock software stop mode ? ? ? ? normal operation ? ? halt mode ? ? ? idle mode ? ? ? ? direct mode external clock software stop mode ? ? ? ? remark : operating ? : stopped chapter 9 clock generation function user?s manual u14359ej5v1ud 312 9.5.2 control registers (1) power-save mode register (psmr) this is an 8-bit register that controls power-save m ode. it is effective only when the stb bit of the psc register is set to 1. writing to the psmr register is exec uted by the store instruction (st/sst instruction) and a bit manipulation instruction (set1/clr1 /not1 instruction). this register can be read or written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 <0> address after reset psmr 0 0 0 0 0 0 0 psm fffff820h 00h bit position bit name function 0 psm power save mode specifies idle mode or software stop mode. 0: switches the system to idle mode 1: switches the system to software stop mode (2) command register (prcmd) this is an 8-bit register that is used to set protection for write operations to regi sters that can significantly affect the system so that the applic ation system is not halted unexpecte dly due to an inadvertent program loop. writing to the first specific register (power-save control register (psc)) is only valid after first writing to the prcmd register. because of this, the register value can be overwritten only by the specified sequence, preventing an illegal write o peration from being performed. this register is write-only in 8-bit units . when it is read, undefined data is read out. 7 6 5 4 3 2 1 0 address after reset prcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 fffff1fch undefined bit position bit name function 7 to 0 reg7 to reg0 registration code (arbitrary 8-bit data) the specific register targeted is t he power-save control register (psc). chapter 9 clock generation function user?s manual u14359ej5v1ud 313 (3) power-save control register (psc) this is an 8-bit register that contro ls the power-save function. this regi ster, which is one of the specific registers, is valid only when accessed in a specific sequence dur ing a write operation. this register can be read or written in 8-bit or 1-bi t units. if bit 7 or 6 is set to 1, operation cannot be guaranteed. caution it is impossible to set the stb bit and the nmim or intm bit at the same time. be sure to set the stb bit after setting the nmim or intm bit. 7 6 <5> <4> 3 2 <1> 0 address after reset psc 0 0 nmim intm 0 0 stb 0 fffff1feh 00h bit position bit name function 5 nmim nmi mode this is the enable/disable setting bit fo r standby mode release using the valid edge input of nmi. 0: release by nmi enabled 1: release by nmi disabled 4 intm int mode this is the enable/disable setting for st andby mode release using an unmasked maskable interrupt (intp1nn) (n = 0 to 3). 0: release by maskable interrupt enabled 1: release by maskable interrupt disabled 1 stb standby mode indicates the standby mode status. if 1 is written to this bit, the system enter s idle or software stop mode (set by the psm bit of the psmr register). when standby mode is released, this bit is automatically reset to 0. 0: standby mode is released 1: standby mode is in effect chapter 9 clock generation function user?s manual u14359ej5v1ud 314 set data in the power-save control regist er (psc) in the following sequence. <1> set the power-save mode register (psm r) (with the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <2> prepare data in any one of the general-purpose registers to set to the specific register. <3> write data to the command register (prcmd). <4> set the power-save control register (psc) (with the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> assert the nop instructions (5 instructions (<5> to <9>). sample coding <1> st.b r11, psmr [r0] ; set psmr register <2> mov 0x02, r10 <3> st.b r10, prcmd [r0] ; write prcmd register <4> st.b r10, psc [r0] ; set psc register <5> nop ; dummy instruction <6> nop ; dummy instruction <7> nop ; dummy instruction <8> nop ; dummy instruction <9> nop ; dummy instruction (next instruction) ; execution routine after software stop mode and idle mode release no special sequence is required to read the specific register. cautions 1. a store instruction for the command regi ster does not acknowledge in terrupts. this coding is made on assumption that <3> and <4> above are executed by the program with consecutive store instructions. if another instruction is set between <3> and <4>, the above sequence may become ineffecti ve when the interrupt is ackno wledged by that instruction, and a malfunction of the program may result. 2. although the data written to the prcmd re gister is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the prcmd register (<3>). the same method should be applied when using a ge neral-purpose register for addressing. 3. at least 5 nop instructions must be inserted after executi ng a store instruction to the psc register to set software stop or idle mode. 4. be sure to terminate all dma transfers prior to the execution of the above sequence. chapter 9 clock generation function user?s manual u14359ej5v1ud 315 9.5.3 halt mode (1) setting and operation status in halt mode, the clock generator (oscillator and pll synthesizer) continues to o perate, but the operation clock of the cpu is stopped. since the supply of clocks to on-chip peri pheral i/o units other than the cpu continues, operation continues. the power consumption of the overall sys tem can be reduced by setting the system to halt mode while the cpu is idle. the system is switched to halt mode by the halt instruction. although program execution stops in ha lt mode, the contents of all regist ers, internal ram, and ports are maintained in the state they were in immediately before halt mode began. also, operation continues for all on-chip peripheral i/o units (other than ports) that do not depend on cpu instructio n processing. table 9-2 shows the status of each hardware unit in halt mode. caution if the halt instruction is executed while an interrupt is being held pending, the halt mode is set once but it is immediately rele ased by the pending interrupt request. table 9-2. operation status in halt mode function operation status clock generator operating internal system clock operating cpu stopped ports maintained on-chip peripheral i/o (e xcluding ports) operating internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are maintained in the state they were in immediately before halt mode began. d0 to d15 a0 to a25 rd, we, oe, bcyst uwr, lwr, iord, iowr ldqm, udqm cs0 to cs7 lcas, ucas ras1, ras3, ras4, ras6 sdras sdcas refrq hldak hldrq wait selfref sdcke operating sdclk clkout clock output chapter 9 clock generation function user?s manual u14359ej5v1ud 316 (2) release of halt mode halt mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, or reset pin input. (a) release according to a non-maskable interr upt request or an unmasked maskable interrupt request halt mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority. however, if the system is set to halt mode during an interrupt servicing routine, operation will differ as follows. (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being serviced, halt m ode is released, but the newly ge nerated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt reques t that is currently being servic ed, halt mode is released and the newly generated interrupt request is acknowledged. table 9-3. operation after halt mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction (b) release according to reset pin input this is the same as a normal reset operation. chapter 9 clock generation function user?s manual u14359ej5v1ud 317 9.5.4 idle mode (1) setting and operation status in idle mode, the clock generator (oscillator and pll sy nthesizer) continues to oper ate, but the supply of internal system clocks is stopped which c auses the overall system to stop. when idle mode is released, the system can be s witched to normal operation mode quickly because the oscillator's oscillation stabilization time or the pll lockup time does not need to be secured. the system is switched to idle mode by setting the psc or psmr register using a store instruction (st or sst instruction) or a bit manipulation instruct ion (set1, clr1, or not1 instruction) (see 9.5.2 control registers ). in idle mode, program execution is stopped, and the contents of all regi sters, internal ram, and ports are maintained in the state they were in immediately be fore execution stopped. the operation of on-chip peripheral i/o units (excluding ports) also is stopped. table 9-4 shows the status of each hardware unit in idle mode. chapter 9 clock generation function user?s manual u14359ej5v1ud 318 table 9-4. operation status in idle mode function operation status clock generator operating internal system clock stopped cpu stopped ports maintained on-chip peripheral i/o (excluding ports) stopped internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are maintained in the state they were in immediately before idle mode began. d0 to d15 a0 to a25 high impedance rd, we, oe, bcyst uwr, lwr, iord, iowr ldqm, udqm cs0 to cs7 high-level output lcas, ucas ras1, ras3, ras4, ras6 sdras sdcas refrq operating hldak high-level output hldrq wait selfref input (no sampling) sdcke sdclk clkout low-level output chapter 9 clock generation function user?s manual u14359ej5v1ud 319 (2) release of idle mode idle mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (intp1nm), or reset pin input (n = 0 to 3, m = 0 to 3). (a) release according to a non-maskable interr upt request or an unmasked maskable interrupt request idle mode can be released by an interrupt request only when it has been set with the intm and nmim bits of the psc register cleared to 0. the idle mode cannot be released if it is specified that the level of the intp1nm pin is detected. idle mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request (intp1nn) regardless of the priority. howe ver, if the system is set to idle mode during a maskable interrupt servicing routine, operat ion will differ as follows (n = 0 to 3). (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being serviced, idle mode is released, but the newly generated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt reques t that is currently being servic ed, idle mode is released and the newly generated interrupt request is acknowledged. table 9-5. operation after idle mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction if the system is set to idle mode during an nmi se rvicing routine, idle mode is released, but the interrupt is not acknowledged (interrupt is held pending). interrupt servicing that is started when idle mode is released by nmi pin input is handled in the same way as normal nmi interrupt servicing that occu rs during an emergency (because the nmi interrupt handler address is unique). ther efore, when a program must be able to distinguish between these two situations, a software status must be prepared in advance and that status must be set before setting the psmr register using a store instructi on or a bit manipulation instruction. by checking for this status during nmi interrupt servicing, an ordinary nmi can be distinguished from the pr ocessing that is started when idle mode is released by nmi pin input. (b) release according to reset pin input this is the same as a normal reset operation. chapter 9 clock generation function user?s manual u14359ej5v1ud 320 9.5.5 software stop mode (1) setting and operation status in software stop mode, the clock generator (oscillator and pll synthesizer) is stopp ed. the overall system is stopped, and ultra-low power consumption is achieved in which only leakage current is lost. the system is switched to software st op mode by using a store instructi on (st or sst instruction) or bit manipulation instruction (set1, clr1, or not1 in struction) to set the psc and psmr registers (see 9.5.2 control registers ). when pll mode and resonator connection mode (cesel bit of ckc register = 0) ar e used, the oscillator's oscillation stabilization time must be secu red after software stop mode is released. in both pll and direct mode, following the release of software stop mode, execution of the program is started after the count time of the time base counter has elapsed. although program execution stops in software stop mode, the contents of all registers, internal ram, and ports are maintained in the state they were in i mmediately before software stop mode began. the operation of all on-chip peripheral i/o uni ts (excluding ports) is also stopped. table 9-6 shows the status of each hardware unit in software stop mode. chapter 9 clock generation function user?s manual u14359ej5v1ud 321 table 9-6. operation stat us in software stop mode function operation status clock generator stopped internal system clock stopped cpu stopped ports maintained note on-chip peripheral i/o (excluding ports) stopped internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are maintained in the state they were in immediately before software stop mode began. d0 to d15 a0 to a25 high impedance rd, we, oe, bcyst uwr, lwr, iord, iowr ldqm, udqm cs0 to cs7 high-level output lcas, ucas ras1, ras3, ras4, ras6 sdras sdcas refrq operating hldak high-level output hldrq wait selfref input (no sampling) sdcke sdclk clkout low-level output note when the v dd value is within the operable range. howe ver, even if it drops below the minimum operable voltage, as long as the data retention voltage v dddr is maintained, the contents of only the internal ram will be maintained. chapter 9 clock generation function user?s manual u14359ej5v1ud 322 (2) release of software stop mode software stop mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (intp1nm), or reset pin input. also, to release software stop mode when pll mode (cksel pin = low level) and resonator connection mode (cesel bi t of ckc register = 0) are used, the oscillator?s oscillation stabilization time must be secured (n = 0 to 3, m = 0 to 3). moreover, the oscillation stabilization time must be secured even when an external clock is connected (cesel bit = 1). see 9.4 pll lockup for details. (a) release according to a non-maskable interr upt request or an unmasked maskable interrupt request the software stop mode can be released by an inte rrupt request only when it has been set with the intm and nmim bits of the pcs register cleared to 0. the idle mode can not be released if it is specified that the level of the intp1nm pin is detected. software stop mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request (intp1nn) regardless of the priority. however, if the system is set to software stop mode during an interrupt servicing routine, operation will differ as follows (n = 0 to 3). (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being servicing, software stop mode is released, but the newly generated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt request that is currently being serviced, software stop mode is released and the newly generated interrupt request is acknowledged. table 9-7. operation after software stop mode is released by interrupt request cancellation source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction if the system is set to software stop mode during an nmi servicing routine, software stop mode is released, but the interrupt is not ackn owledged (interrupt is held pending). interrupt servicing that is start ed when software stop mode is released by nmi pin input is handled in the same way as normal nmi interrupt servicing t hat occurs during an emergency (because the nmi interrupt handler address is unique) . therefore, when a program must be able to distinguish between these two situations, a software status must be prepar ed in advance and that status must be set before setting the psmr register using a store instru ction or a bit manipulation instruction. by checking for this status during nmi interrupt servic ing, an ordinary nmi can be distinguished from the servicing that is started when software stop mode is released by nmi pin input. (b) release according to reset pin input this is the same as a normal reset operation. chapter 9 clock generation function user?s manual u14359ej5v1ud 323 9.6 securing oscillation stabilization time 9.6.1 oscillation stabilization time security specification two specification methods can be used to secure the time from when software stop mode is released until the stopped oscillator stabilizes. (1) securing the time using an on-chip time base counter software stop mode is released when a valid edge is input to the nmi pin or a maskable interrupt request is input (intp1nm). if oscillation is started by inputting an active edge to the pin, the time base counter (tbc) starts counting, and the time required for the clock out put from the oscillation circuit to be stabilized is secured within that count time (n = 0 to 3, m = 0 to 3). oscillation stabilization time = tbc counting time after a fixed time, internal system clock output be gins, and processing branches to the nmi interrupt or maskable interrupt (intp1nn) handler address. oscillation waveform (x2) set software stop mode oscillator is stopped clkout (output) internal main clock stop state nmi (input) note time base counter's counting time note valid edge: when specified as the rising edge. the nmi pin should usually be set to an inactive level (for example, high level when the valid edge is specified as the falling edge) in advance. software stop mode is immediately released if softw are stop mode is set by nmi valid edge input or maskable interrupt request input (intp1nm) bef ore the cpu acknowledges the interrupt. if direct mode or external clock con nection mode (cesel bit of ckc regist er = 1) is used, program execution begins after the count time of the time base counter has elapsed. also, even if pll mode and resonato r connection mode (cesel bit of ckc register = 0) are used, program execution begins after the oscillation stabilization time is secured according to the time base counter. chapter 9 clock generation function user?s manual u14359ej5v1ud 324 (2) securing the time according to th e signal level width (reset pin input) software stop mode is released due to falling edge input to the reset pin. the time until the clock output from t he oscillator stabilizes is secured according to the low-level width of the signal that is input to the pin. the supply of internal system clocks be gins after a rising edge is input to the reset pin, and processing branches to the handler addr ess used for a system reset. oscillation waveform (x2) set software stop mode oscillator is stopped internal main clock stop state internal system reset signal oscillation stabilization time secured by reset reset (input) undefined clkout (output) undefined chapter 9 clock generation function user?s manual u14359ej5v1ud 325 9.6.2 time base counter (tbc) the time base counter (tbc) is used to secure the osci llator's oscillation stabilization time when software stop mode is released. when an external clock is connected (cesel bit of ckc regi ster = 1) or a resonator is connected (pll mode and cesel bit of ckc register = 0), the tbc counts the o scillation stabilization time after software stop mode is released, and program execution begi ns after the count is completed. the tbc count clock is selected according to the tbcs bi t of the ckc register, and the next counting time can be set (reference). table 9-8. counting time examples (f xx = 10 f x ) counting time f x = 4.0000 mhz f x = 5.0000 mhz tbcs bit count clock f xx = 40.000 mhz f xx = 50.000 mhz 0 f x /2 8 16.3 ms 13.1 ms 1 f x /2 9 32.6 ms 26.2 ms f x : external oscillation frequency f xx : internal system clock user?s manual u14359ej5v1ud 326 chapter 10 timer/counter function (real-time pulse unit) 10.1 timer c 10.1.1 features (timer c) timer c is a 16-bit timer/counter t hat can perform the following operations. ? interval timer function ? pwm output ? external signal cycle measurement 10.1.2 function overview (timer c) ? 16-bit timer/counter ? capture/compare common registers: 8 ? interrupt request sources ? capture/match interrupt requests: 8 ? overflow interrupt requests: 4 ? timer/counter count clock sources: 2 (selection of external pulse input or internal system clock division) ? either free-running mode or overflow stop mode can be selected as the operation mode when the timer/counter overflows ? timer/counter can be cleared by a match of the timer/counter and a compare register ? external pulse outputs: 4 chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 327 10.1.3 basic configuration of timer c table 10-1. timer c configuration timer count clock register read/write generated interrupt signal capture trigger timer output s/r other functions tmc0 read intov00 ? ? ? ccc00 read/write intm000 intp000 to00 (s) a/d conversion start trigger ccc01 read/write intm001 intp001 to00 (r) a/d conversion start trigger tmc1 read intov01 ? ? ? ccc10 read/write intm010 intp010 to01 (s) a/d conversion start trigger ccc11 read/write intm011 intp011 to01 (r) a/d conversion start trigger tmc2 read intov02 ? ? ? ccc20 read/write intm020 intp020 to02 (s) ? ccc21 read/write intm021 intp021 to02 (r) ? tmc3 read intov03 ? ? ? ccc30 read/write intm030 intp030 to03 (s) ? timer c f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 ccc31 read/write intm031 intp031 to03 (r) ? remarks f xx : internal system clock s/r: set/reset (1) timer c (16-bit timer/counter) r note q sq tmcn (16 bits) cccn0 cccn1 intov0n intm0n0 intp0n1 f xx m/2 f xx m/4 f xx m/8 f xx m/16 f xx m/32 f xx m/64 f xx m/128 f xx m/256 f xx /2 ti0n0/intp0n0 intm0n1 to0n clear & start selector selector f xx m note reset priority remarks 1. n = 0 to 3 2. f xx : internal system clock chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 328 10.1.4 timer c (1) timers c0 to c3 (tmc0 to tmc3) tmcn functions as a 16-bit free-running timer or as an event counter for an external signal. besides being mainly used for cycle measurement, tmcn can be used as pulse output (n = 0 to 3). tmcn is read-only in 16-bit units. cautions 1. the tmcn register can only be read. if the tmcn register is written, the subsequent operation is undefined. 2. if the tmccaen bit of the tmccn0 regist er is cleared (0), a reset is performed asynchronously. tmc1 fffff610h 0000h tmc2 fffff620h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tmc0 fffff600h 0000h address after reset 0 tmc3 fffff630h 0000h tmcn performs the count-up operations of an internal count clock or external count clock. timer start and stop are controlled by the tmccen bit of timer mode cont rol register cn0 (tmccn0) (n = 0 to 3). the internal or external count clock is selected by the et in bit of timer mode control register cn1 (tmccn1) (n = 0 to 3). (a) selection of the external count clock tmcn operates as an event counter. when the etin bit of timer mode control register cn1 (tmccn1) is set (1), tmcn counts the valid edges of the external clock input (ti0n0), synchronized with t he internal count clock. the valid edge is specified by valid edge select register cn (sescn) (n = 0 to 3). caution when the intp0n 0/ti0n0 pin is used as ti0n0 (external clock in put pin), disable the intp0n0 interrupt or set cccn0 to compare mode (n = 0 to 3). chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 329 (b) selection of the internal count clock tmcn operates as a free-running timer. when an internal clock is specified as the count cl ock by timer mode control register cn1 (tmccn1), tmcn is counted up for each input clock cycle s pecified by the csn0 to csn2 bits of the tmccn0 register (n = 0 to 3). division by the prescaler can be selected for the count clock from among f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, and f xx /512 by the tmccn0 register (f xx : internal system clock). an overflow interrupt can be generated if the timer overflows. also, the timer can be stopped following an overflow by setting the ostn bit of the tmccn1 register to 1. caution the count clock cannot be ch anged while the timer is operating. the conditions when the tmcn register becomes 0000h are shown below. (a) asynchronous reset ? tmccaen bit of tmccn0 register = 0 ? reset input (b) synchronous reset ? tmccen bit of tmccn0 register = 0 ? the cccn0 register is used as a compare regist er, and the tmcn and cccn0 registers match when clearing the tmcn register is enabled (c clrn bit of the tmccn1 register = 1) chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 330 (2) capture/compare registers cn0 and cn1 (cccn0 and cccn1) (n = 0 to 3) these capture/compare registers (cn0 and cn1) are 16-bit registers. they can be used as capture registers or compar e registers according to the cmsn0 and cmsn1 bit specifications of timer mode control re gister cn1 (tmccn1) (n = 0 to 3). these registers can be read or written in 16-bit units. (however, write operations can only be performed in compare mode.) ccc1n ccc2n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ccc0n fffff602h, fffff604h fffff612h, fffff614h fffff622h, fffff624h fffff632h, fffff634h 0000h 0000h 0000h 0000h address after reset 0 ccc3n remark n = 0 and 1 (a) setting these registers as capture regist ers (cmsn0 and cmsn1 of tmccn1 = 0) when these registers are set as capture registers, the valid edges of the corresponding external interrupt signals intp0n0 and intp0n1 are detected as capture triggers. the timer tmcn is synchronized with the capture trigger, and the value of tmcn is latched in the cccn0 and cccn1 registers (capture operation). the valid edge of the intp0n0 pin is specified (rising , falling, or both rising and falling edges) according to the ies0n01 and ies0n00 bits of the sescn re gister, and the valid edge of the intp0n1 pin is specified according to the ies0n11 and ies0n10 bits of the sescn register. the capture operation is per formed asynchronously to the count clo ck. the latched value is held in the capture register until another c apture operation is performed. when the tmccaen bit of timer mode control register cn 0 (tmccn0) is 0, 0000h is read (n = 0 to 3). if these registers are specified as capture registers, an interrupt is generated by detecting the valid edge of signals intp0n0 and intp0n1 (n = 0 to 3). caution if the capture operation contends with the timing of disabling the tmcn register from counting (when the tmccen bit of the tm ccn0 register = 0), the captured data becomes undefined. in addition, the intm0n 0 and intm0n1 interrupts do not occur (n = 0 to 3). chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 331 (b) setting these registers as compare regist ers (cmsn0 and cmsn1 of tmccn1 = 1) when these registers are set as compare registers, th e tmcn and register values are compared for each count clock, and an interrupt is generated by a match. if the cclrn bit of timer mode control register cn1 (tmccn1) is set (1), the tmcn value is cleared (0) at the same time as a match with the cccn0 register (it is not cleared (0) by a match with the cccn1 register) (n = 0 to 3). a compare register is equipped with a set/reset function. the correspondin g timer output (to0n) is set or reset, in synchronization with the generation of a match signal (n = 0 to 3). the interrupt selection source differs accord ing to the function of the selected register. cautions 1. to write to capture /compare registers cn0 and cn1, always set the tmccaen bit to 1 first. if the tmccaen bit is 0, the data that is wri tten will be invalid. 2. write to capture/compare registers cn0 and cn1 after setting them as compare registers via tmccn0 and tmccn1 register settings. if they are set as capture registers (cmsn0 and cmsn1 bits of tmccn1 re gister = 0), no data is written even if a write operation is performed to cccn0 and cccn1. 3. when these registers are set as compare registers, in tp0n0 and intp0n1 cannot be used (n = 0 to 3). chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 332 10.1.5 timer c control registers (1) timer mode control registers c00 to c30 (tmcc00 to tmcc30) the tmccn0 registers control the operatio n of tmcn (n = 0 to 3). these r egisters can be read or written in 8-bit or 1-bit units. be sure to set bits 3 and 2 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. the tmccaen and other bits cannot be set at the same time. the other bits and the registers of the other tmcn unit should alw ays be set after the tmccaen bit has been set. also, to use external pins related to the timer function when timer c is used, be sure to set (1) the tmccaen bit after set ting the external pins to control mode. 2. when conflict occurs be tween an overflow and a tmccn0 register write, the ovfn bit value becomes the value written during th e tmccn0 register write (n = 0 to 3). (1/2) <7> 6 5 4 3 2 <1> <0> address after reset tmcc00 ovf0 cs02 cs01 cs00 0 0 tmcce0 tmccae0 fffff606h 00h tmcc10 ovf1 cs12 cs11 cs10 0 0 tmcce1 tmccae1 fffff616h 00h tmcc20 ovf2 cs22 cs21 cs20 0 0 tmcce2 tmccae2 fffff626h 00h tmcc30 ovf3 cs32 cs31 cs30 0 0 tmcce3 tmccae3 fffff636h 00h bit position bit name function 7 ovfn (n = 0 to 3) overflow this is a flag that indicates tmcn overflow (n = 0 to 3). 0: no overflow occurs 1: overflow occurs when tmcn has counted up from ffffh to 0000h, the ovfn bit becomes 1 and an overflow interrupt request (intov0n) is generated at the same time. however, if tmcn is cleared to 0000h after a match at ffffh when the cccn0 register is set to compare mode (cmsn0 bit of tmccn1 register = 1) and clearing is enabled for a match when tmcn and cccn0 are compared (cclrn bit of tmccn1 register = 1), then tmcn is considered to be cleared and the ovfn bit does not become 1. also, no intov0n interrupt is generated. the ovfn bit retains the value 1 until 0 is written directly or until an asynchronous reset is performed because the tmccaen bit is 0. an interrupt operation due to an overflow is independent of the ovfn bit, and the interrupt request flag (ovifn) for intov0n is not affected even if the ovfn bit is manipulated. if an overflow occurs while the ovfn bit is being read, the flag value changes, and the change is reflected when the next read operation occurs. chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 333 (2/2) bit position bit name function count enable select selects the tmcn internal count clock (n = 0 to 3). csn2 csn1 csn0 count cycle 0 0 0 f xx /4 0 0 1 f xx /8 0 1 0 f xx /16 0 1 1 f xx /32 1 0 0 f xx /64 1 0 1 f xx /128 1 1 0 f xx /256 1 1 1 f xx /512 6 to 4 csn2 to csn0 (n = 0 to 3) caution the csn2 to csn0 bits must not be changed during timer operation. if they are to be changed, they must be changed after setting the tmccen bit to 0. if these bits are overwritten during timer operation, operation cannot be guaranteed. remark f xx : internal system clock 1 tmccen (n = 0 to 3) count enable controls the operation of tmcn (n = 0 to 3). 0: count disabled (stops at 0000h and does not operate) 1: counting operation is performed caution when tmccen = 0, the external pulse output (to0n) becomes inactive (the active level of to0n output is set by the actlvn bit of the tmccn1 register). 0 tmccaen (n = 0 to 3) clock action enable controls the internal count clock (n = 0 to 3). 0: the entire tmcn unit is asynchronously reset. the supply of clocks to the tmcn unit stops. 1: clocks are supplied to the tmcn unit cautions 1. when the tmccaen bit is set to 0, the tmcn unit can be asynchronously reset. 2. when tmccaen = 0, the tmcn unit is in a reset state. therefore, to operate tmcn, the tmccaen bit must be set to 1. 3. when the tmccaen bit is changed from 1 to 0, all registers of the tmcn unit are initialized. when tmccaen is set to 1 again, the tmcn unit registers must be set again. chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 334 (2) timer mode control registers c01 to c31 (tmcc01 to tmcc31) the tmccn1 registers control the operat ion of tmcn (n = 0 to 3). these registers can be read or written in 8-bit units. be sure to set bit 2 to 0. if it is set to 1, the operation is not guaranteed. cautions 1. the various bits of the tmccn1 register must not be changed dur ing timer operation. if they are to be changed, th ey must be changed after setting the tmccen bit of the tmccn0 register to 0. if these bits are overwritten durin g timer operation, operation cannot be guaranteed (n = 0 to 3). 2. if the entn1 and actlvn bits are change d at the same time, a glitch (spike shaped noise) may be generated in the to0n pin output . either create a circuit configuration that will not malfunction even if a glitch is ge nerated or make sure that the entn1 and actlvn bits do not change at the same time (n = 0 to 3). 3. to0n output is not changed by an externa l interrupt signal (intp0 n0 or intp0n1). to use the to0n signal, specify th at the capture/compare regi sters are compare registers (cmsn0 and cmsn1 bits of tmccn1 register = 1) (n = 0 to 3). (1/2) 7 6 5 4 3 2 1 0 address after reset tmcc01 ost0 ent01 actlv0 eti0 cclr0 0 cms01 cms00 fffff608h 20h tmcc11 ost1 ent11 actlv1 eti1 cclr1 0 cms11 cms10 fffff618h 20h tmcc21 ost2 ent21 actlv2 eti2 cclr2 0 cms21 cms20 fffff628h 20h tmcc31 ost3 ent31 actlv3 eti3 cclr3 0 cms31 cms30 fffff638h 20h bit position bit name function 7 ostn (n = 0 to 3) overflow stop sets the operation when tmcn has overflowed (n = 0 to 3). 0: after the overflow, counting continues (free-running mode) 1: after the overflow, the timer maintains the value 0000h, and counting stops (overflow stop mode). at this time, the tmccen bit of tmccn0 remains at 1. counting is restarted by writing 1 to the tmccen bit. 6 entn1 (n = 0 to 3) enable to pin external pulse output is enabled/disabled (to0n) (n = 0 to 3). 0: external pulse output is disabled. output of the actlvn bit inactive level to the to0n pin is fixed. the to0n pi n level is not changed even if a match signal from the corresponding compare register is generated. 1: external pulse output is enabled. a compare register match causes to0n output to change. however, if capture mode is set, to0n output does not change. the actlvn bit inactive level is output from the time when timer output is enabled until a matc h signal is first generated. caution if either cccn0 or cccn1 is specified as a capture register, the entn1 bit must be set to 0. chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 335 (2/2) bit position bit name function 5 actlvn (n = 0 to 3) active level specifies the active level for external pulse output (to0n) (n = 0 to 3). 0: active level is low level 1: active level is high level caution the initial value of the actlvn bit is 1. 4 etin (n = 0 to 3) external input specifies a switch between the external and internal count clock. 0: specifies the input clock (int ernal). the count clock can be selected according to the csn2 to csn0 bits of tmccn0 (n = 0 to 3). 1: specifies the external clock (ti0n0). the valid edge can be selected according to the tesn1 and tesn0 bit specifications of sescn (n = 0 to 3). 3 cclrn (n = 0 to 3) compare clear enable sets whether the clearing of tmcn is enabled or disabled during a compare operation (n = 0 to 3). 0: clearing is disabled 1: clearing is enabled (if cccn0 and tmcn match during a compare operation, tmcn is cleared) 1 cmsn1 (n = 0 to 3) capture/compare mode select selects the operation mode of the capture/compare register (cccn1) (n = 0 to 3). 0: the register operates as a capture register 1: the register operates as a compare register 0 cmsn0 (n = 0 to 3) capture/compare mode select selects the operation mode of the capture/compare register (cccn0) (n = 0 to 3). 0: the register operates as a capture register 1: the register operates as a compare register remarks 1. a reset takes precedence for the flip-f lop of the to0n output (n = 0 to 3). 2. when the a/d converter is set to timer trigger m ode, the match interrupt of the compare registers becomes a start trigger for a/d conversion, and th e conversion operation begins. at this time, the compare register match interrupt also functions as a compare register match interrupt for the cpu. to prevent the generati on of a compare register match interrupt for the cpu, disable interrupts using the interrupt mask bits (p00mk0, p00mk1, p01mk0, and p01mk1) of the interrupt control registers (p00ic0 , p00ic1, p01ic0, and p01ic1). chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 336 (3) valid edge select register s c0 to c3 (sesc0 to sesc3) these registers specify the valid edge of an exte rnal interrupt request (intp000, intp001, intp010, intp011, intp020, intp021, intp030, intp031, an d ti000 to ti030) from an external pin. the rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin. each of these registers can be read or written in 8-bit units. be sure to set bits 5 and 4 to 0. if they are set to 1, the operation is not guaranteed. caution the various bits of the sescn register must not be changed during timer operation. if they are to be changed, they must be changed after setting the tmccen bit of the tmccn0 register to 0. if the sescn register is ov erwritten during timer ope ration, operation cannot be guaranteed. 7 6 5 4 3 2 1 0 address after reset sesc0 tes01 tes00 0 0 ies0011 ies0010 ies0001 ies0000 fffff609h 00h 7 6 5 4 3 2 1 0 address after reset sesc1 tes11 tes10 0 0 ies0111 ies0110 ies0101 ies0100 fffff619h 00h 7 6 5 4 3 2 1 0 address after reset sesc2 tes21 tes20 0 0 ies0211 ies0210 ies0201 ies0200 fffff629h 00h 7 6 5 4 3 2 1 0 address after reset sesc3 tes31 tes30 0 0 ies0311 ies0310 ies0301 ies0300 fffff639h 00h bit position bit name function 7, 6 tesn1, tesn0 (n = 0 to 3) edge select specifies the valid edge of the intpn and ti000 to ti030 pins. xesn1 xesn0 operation 0 0 falling edge 3, 2 iesn1, iesn0 (n = 001, 011, 021, 031) 0 1 rising edge 1 0 rfu (reserved) 1 1 both rising and falling edges 1, 0 iesn1, iesn0 (n = 000, 010, 020, 030) ti010 tclr1 intp011 intp010 tclr2 ti020 intp021 intp020 ti030 tclr3 intp031 intp030 ti000 intp001 intp000 chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 337 10.1.6 timer c operation (1) count operation timer c can function as a 16-bit free-running timer or as an external signal event counter. the setting for the type of operation is specified by ti mer mode control registers cn0 and cn1 (tmccn0 and tmccn1) (n = 0 to 3). when it operates as a free-running timer, if the cccn 0 or cccn1 register and the tmcn count value match, an interrupt signal is generated and the timer output sig nal (to0n) can be set or reset. also, a capture operation that holds the tmcn count value in the cccn0 or cccn1 register is performed, in synchronization with the valid edge that was detected from the external in terrupt request input pin as an external trigger. the capture value is held until the nex t capture trigger is generated. caution when using the intp0n0/ti0n 0 pin as an external clock input pin (ti0n0), be sure to disable the intp0n0 interrupt or set cccn0 regist er to compare mode (n = 0 to 3). figure 10-1. basic operation of timer c 0001h 0000h 0002h 0003h fbfeh fbffh 0001h 0002h 0000h tmcn count clock ? count disabled tmccen 0 ? count start tmccen 1 ? count start tmccen 1 remark n = 0 to 3 chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 338 (2) overflow when the tmcn register has counted the count clock from ffffh to 0000h, the ovfn bit of the tmccn0 register is set (1), and an overflow interrupt (intov0n) is generated at the same time (n = 0 to 3). however, if the cccn0 r egister is set to compare mode (cmsn0 bit = 1) and to the value ffffh when match clearing is enabled (cclrn bit = 1), then the tmcn register is considered to be cleared and the ovfn bit is not set (1) when the tmcn register changes fr om ffffh to 0000h. also, the over flow interrupt (intov0n) is not generated . when the tmcn register is changed from ffffh to 000 0h because the tmccen bit changes from 1 to 0, the tmcn register is considered to be cleared, but the ovfn bit is not set (1) and no intov0n interrupt is generated. also, timer operation can be stopped after an overflow by setting the ostn bit of the tmccn1 register to 1. when the timer is stopped due to an over flow, the count operation is not re started until the tmccen bit of the tmccn0 register is set (1). operation is not affected even if the tmcce n bit is set (1) during a count operation. remark n = 0 to 3 figure 10-2. operation after overflow (when ostn = 1) overflow count start overflow ffffh ffffh tmcn 0 intov0n ostn 1 tmccen 1 tmccen 1 remark n = 0 to 3 chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 339 (3) capture operation the tmcn register has two capture/compare regist ers. these are the cccn0 register and the cccn1 register. a capture operation or a compare operation is performed according to the settings of both the cmsn1 and cmsn0 bits of the tmccn1 register. if t he cmsn1 and cmsn0 bits of the tmccn1 register are set to 0, the register oper ates as a capture register. a capture operation that capt ures and holds the tmcn count value asynchronously relative to the count clock is performed in synchronization with an external trigger. the valid edge that is detected from an external interrupt request input pin (intp0n0 or intp0n1) is used as an external trigger (capture trigger). the tmcn count value during counting is captured and held in the capture register, in synchronization with that capture trigger signal. the capture register value is held until the next captur e trigger is generated. also, an interrupt request (intm0n0 or intm0n1) is generated by intp0n0 or intp0n1 signal input. the valid edge of the capture trigger is set by valid edge select register cn (sescn). if both the rising and falling edges are set as capture tr iggers, the input pulse width from an external source can be measured. also, if only one of the edges is set as the capture trigger, the input pulse cycle can be measured. remark n = 0 to 3 figure 10-3. capture operation example tmc1 0 tmcce1 intp011 ccc11 (capture register) n n (capture trigger) (capture trigger) remarks 1. when the tmcce1 bit is 0, no capture oper ation is performed even if intp011 is input. 2. valid edge of intp011: rising edge chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 340 figure 10-4. tmc1 capture operation e xample (when both edges are specified) tmc1 ? count start tmcce1 1 ? overflow ovf1 1 d0 d1 d2 d0 d1 d2 interrupt request (intp011) (tmc1 count values) capture register (ccc11) remark d0 to d2: tm c1 count values chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 341 (4) compare operation the tmcn register has two capture/compare regist ers. these are the cccn0 register and the cccn1 register. a capture operation or a compare operation is performed according to the settings of both the cmsn1 and cmsn0 bits of the tmccn1 register. if t he cmsn1 and cmsn0 bits of the tmccn1 register are set to 1, the register oper ates as a compare register. a compare operation that compares t he value that was set in the compare register and the tmcn count value is performed. if the tmcn count value matches the value of the compare register, which had been set in advance, a match signal is sent to the output controller. the match signal causes the timer output pin (to0n) to change and an interrupt request signal (intm0n0 or intm 0n1) to be generated at the same time. if the cccn0 or cccn1 registers are set to 0000h, the 00 00h after the tmcn register counts up from ffffh to 0000h is judged as a match. in this case, the tmcn register value is cleared (0) at the next count timing, however, this 0000h is not judged as a match. also, the 0000h when the tmcn register begins counting is not judged as a match. if match clearing is enabled (cclrn bit = 1) for the cccn0 register, the tmcn register is cleared when a match with the tmcn register o ccurs during a compare operation. remark n = 0 to 3 figure 10-5. compare op eration example (1/2) (a) when cclr0 = 1 and ccc00 is other than 0000h 0001h tmc0 count up 0000h n n n ? 1 compare register (ccc00) match detection (intm000) to00 pin remarks 1. the match is detected immediately after the count-up, and the match detection signal is generated. 2. n 0000h chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 342 figure 10-5. compare op eration example (2/2) (b) when cclr0 = 1 and ccc00 is 0000h 0001h 0000h 0000h 0000h ffffh tmc0 intov00 count-up compare register (ccc00) match detection (intm000) to00 pin remark the match is detected immediately after the count-up, and the match detection signal is generated. chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 343 (5) external pulse output timer c has four timer output pins (to0n). an external pulse output (to0n) is generated w hen a match of the two compare registers (cccn0 and cccn1) and the tmcn register is detected. if a match is detected when the tmcn count value an d the cccn0 value are compared, the output level of the to0n pin is set. also, if a match is detect ed when the tmcn count value and the cccn1 value are compared, the output level of the to0n pin is reset. the output level of the to0n pin can be specified by the tmccn1 register. remark n = 0 to 3 table 10-2. to0n output control to0n output entn1 actlvn external pulse output output level 0 0 disable high level 0 1 disable low level 1 0 enable when the cccn0 register is matched: low level when the cccn1 register is matched: high level 1 1 enable when the cccn0 register is matched: high level when the cccn1 register is matched: low level remark n = 0 to 3 figure 10-6. tmc1 compare operati on example (set/reset output mode) tmc1 count value 0 count start tmcce1 1 clear & start clear & start ccc10 ccc10 ccc11 ccc11 ccc11 interrupt request (intm010) interrupt request (intm011) to01 pin ent11 1 actlv1 1 chapter 10 timer/counter function (real-time pulse unit) 344 user?s manual u14359ej5v1ud 10.1.7 application examples (timer c) (1) interval timer by setting the tmccn0 and tmccn1 registers as shown in figure 10-7, timer c operates as an interval timer that repeatedly generates interrupt requests with the value that wa s preset in the cccn0 register as the interval. when the counter value of the tmcn register matches the setting value of the cccn0 register, the tmcn register is cleared (0000h) and an interrupt request signa l (intm0n0) is generated at the same time that the count operation resumes. remark n = 0 to 3 figure 10-7. contents of register settings when timer c is used as interval timer supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 1 0 note 0/1 1 ostn entn1 actlvn etin cclrn cmsn1 cmsn0 0/1 0/1 0/1 0/1 0 note 0 note 11 ovfn tmccn0 tmccn1 csn2 csn1 csn0 tmccen tmccaen use cccn0 register as compare register clear tmcn register due to match with cccn0 register continue counting after tmcn register overflows note be sure to set bits 3 and 2 of the tmccn0 regist er and bit 2 of the tmccn1 register to 0. if they are set to 1, the operation is not guaranteed. remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0 to 3 chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 345 figure 10-8. interval time r operation timing example 0000h 0001h p 0000h 0001h pp p p p p 0000h 0001h t count start interval time interval time interval time count clock tmcn register cccn0 register intm0n0 interrupt clear clear remarks 1. p: setting value of cccn0 register (0000h to ffffh) t: count clock cycle interval time = (p + 1) t 2. n = 0 to 3 chapter 10 timer/counter function (real-time pulse unit) 346 user?s manual u14359ej5v1ud (2) pwm output by setting the tmccn0 and tmccn1 registers as shown in figure 10-9, timer c can output a pwm signal, whose frequency is determined according to the setting of the csn2 to csn0 bits of the tmccn0 register, with the values that were preset in the cccn0 and cccn1 registers determining the intervals. when the counter value of the tmcn register matches the setting value of the cccn0 register, the to0n output becomes active. then, when the counter value of the tmcn register matches the setting value of the cccn1 register, the to0n output becomes inactive. the tmcn register contin ues counting. when it overflows, its count value is cleared to 0000h, and the re gister continues counting. in this way, a pwm signal whose frequency is determined according to the setting of the csn2 to csn0 bits of the tmccn0 register can be output. when the setting value of the cccn0 register and the setting value of the cccn1 register are the same, the to0n output remains inactive and does not change. the active level of the to0n output can be se t by the actlvn bit of the tmccn1 register. remark n = 0 to 3 figure 10-9. contents of register settings when timer c is used for pwm output supply input clocks to internal units enable count operation 0 1 0/1 0/1 0 0 note 11 ostn entn1 actlvn etin cclrn cmsn1 cmsn0 0/1 0/1 0/1 0/1 0 note 0 note 11 ovfn tmccn0 tmccn1 csn2 csn1 csn0 tmccen tmccaen use cccn0 register as compare register use cccn1 register as compare register disable clearing of tmcn register due to match with cccn0 register enable external pulse output (to0n) continue counting after tmcn register overflows note be sure to clear bits 3 and 2 of the tmccn0 regist er and bit 2 of the tmccn1 register to 0. if they are set to 1, the operation is not guaranteed. remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0 to 3 chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 347 figure 10-10. pwm output timing example 0000h 0001h p ppp p p qqq q q qpq 0000h ffffh 0001h count clock tmcn register cccn0 register cccn1 register intm0n0 interrupt intm0n1 interrupt to0n (output) count start clear t remarks 1. p: setting value of cccn0 register (0000h to ffffh) q: setting value of cccn 1 register (0000h to ffffh) p q t: count clock cycle pwm cycle = 65,536 t 65,536 p q duty ? = 2. in this example, the active level of the to0n output is set to the high level. 3. n = 0 to 3 chapter 10 timer/counter function (real-time pulse unit) 348 user?s manual u14359ej5v1ud (3) cycle measurement by setting the tmccn0 and tmccn1 registers as shown in figure 10-11, timer c can measure the cycle of signals input to the intp0n0 or intp0n1 pin. the valid edge of the intp0n0 pin is selected accord ing to the ies0n01 and ies0n00 bits of the sescn register, and the valid edge of the intp0n1 pin is select ed according to the ies0n11 and ies0n10 bits of the sescn register. either the rising edge, the falling edge, or both edges can be selected as the valid edges of both pins. if the cccn0 register is set as a capture register, the va lid edge input of the intp0n0 pin is set as the trigger for capturing the tmcn register value in the cccn0 register. when this value is captured, an intm0n0 interrupt is generated. similarly, if the cccn1 register is se t as a capture register, the valid edge input of the intp0n1 pin is set as the trigger for capturing the tmcn register value in the cccn1 register. when this value is captured, an intm0n1 interrupt is generated. the cycle of signals input to the intp0n0 pin is calc ulated by obtaining the difference between the tmcn register?s count value (dx) that was captured in the cccn0 register accord ing to the x-th valid edge input of the intp0n0 pin and the tmcn regist er?s count value (d(x+1)) that wa s captured in the cccn0 register according to the (x+1)-th valid edge input of the intp0n0 pin and multiplying the value of this difference by the cycle of the clock control signal. the cycle of signals input to the intp0n1 pin is calc ulated by obtaining the difference between the tmcn register?s count value (dx) that was captured in the cccn1 register accord ing to the x-th valid edge input of the intp0n1 pin and the tmcn regist er?s count value (d(x+1)) that wa s captured in the cccn1 register according to the (x+1)-th valid edge input of the intp0n1 pin and multiplying the value of this difference by the cycle of the clock control signal. remark n = 0 to 3 chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 349 figure 10-11. contents of register settings when timer c is used for cycle measurement supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 0/1 0 note 00 ostn entn1 actlvn etin cclrn cmsn1 cmsn0 0/1 0/1 0/1 0/1 0 note 0 note 11 ovfn tmccn0 tmccn1 csn2 csn1 csn0 tmccen tmccaen use cccn0 register as capture register (when measuring the cycle of intp0n0 input) use cccn1 register as capture register (when measuring the cycle of intp0n1 input) continue counting after tmcn register overflows note be sure to clear bits 3 and 2 of the tmccn0 register and bit 2 of the tmccn1 register to 0. if they are set to 1, the operation is not guaranteed. remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0 to 3 chapter 10 timer/counter function (real-time pulse unit) 350 user?s manual u14359ej5v1ud figure 10-12. cycle measurement operation timing example 0001h 0000h 0001h 0000h ffffh d0 d1 d2 d3 d3 d2 d1 d0 (d1 ? d0) t (d3 ? d2) t {(10000h ? d1) + d2} t note t count clock tmcn register intp0n0 (input) cccn0 register intm0n0 interrupt intov0n interrupt no overflow overflow occurs no overflow clear count start note when an overflow is generated once. remarks 1. d0 to d3: tmcn register count values t: count clock cycle 2. in this example, the valid edge of the intp0n0 input has been set to both edges (rising and falling). 3. n = 0 to 3 chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 351 10.1.8 cautions (timer c) various cautions concerning timer c are shown below. (1) if a conflict occurs between the reading of the cccn0 register and a capture operation when the cccn0 register is used in capture mode, an external trigger (intp0n0) valid edge is detected and an external interrupt request signal (intm0n0) is generated, however, the timer value is not stored in the cccn0 register. (2) if a conflict occurs between the reading of the cccn1 register and a capture operation when the cccn1 register is used in capture mode, an external trigger (intp0n1) valid edge is detected and an external interrupt request signal (intm0n1) is generated, however, the timer value is not stored in the cccn1 register. (3) the following bits and registers must not be rewritten during operation (tmccen = 1). ? csn2 to csn0 bits of tmccn0 register ? tmccn1 register ? sescn register (4) the tmccaen bit of the tmccn0 register is a tmcn reset signal. to use tmcn , first set (1) the tmccaen bit. (5) the analog noise eliminat ion time + two cycles of the count clock are required to de tect the valid edge of the external interrupt request signal (intp0n0 or intp0n1) or the external clock input (ti0n0). t herefore, edge detection will not be performed normally for changes that are less than the analog noise elimination time + two cycles of the count clock. for deta ils of analog noise elimination, refer to 7.3.8 noise elimination . (6) the operation of an external interrupt request sign al (intm0n0 or intm0n1) is automatically determined according to the operating state of the capture/compare register. when th e capture/compare register is used for a capture operation, the external interrupt reques t signal is used for valid edge detection. when the capture/compare register is used for a compare operation, the external interrupt request signal is used for an interrupt indicating a match with the tmcn register. (7) if the entn1 and actlvn bits are changed at the same time, a glitch (spike shaped noise) may be generated in the to0n pin output. either create a circui t configuration that will not ma lfunction even if a glitch is generated or make sure that the entn1 and ac tlvn bits are not changed at the same time. remark n = 0 to 3 chapter 10 timer/counter function (real-time pulse unit) 352 user?s manual u14359ej5v1ud 10.2 timer d 10.2.1 features (timer d) timer d functions as a 16-bit interval timer. 10.2.2 function overview (timer d) ? 16-bit interval timer ? compare registers: 4 ? interrupt request sources: 4 sources ? count clock selected from divisions of internal system clock 10.2.3 basic configuration of timer d table 10-3. timer d configuration timer count clock register read/write generated interrupt signal capture trigger timer output s/r other functions tmd0 read ? ? ? ? cmd0 read/write intcmd0 ? ? ? tmd1 read ? ? ? ? cmd1 read/write intcmd1 ? ? ? tmd2 read ? ? ? ? cmd2 read/write intcmd2 ? ? ? tmd3 read ? ? ? ? timer d f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 cmd3 read/write intcmd3 ? ? ? remark f xx : internal system clock s/r: set/reset (1) timer d (16-bit timer/counter) tmdn (16 bits) cmdn intcmdn clear & start f xx m/2 f xx m/4 f xx m/8 f xx m/16 f xx m/32 f xx m/64 f xx m/128 f xx m/256 f xx /2 f xx m remarks 1. n = 0 to 3 2. f xx : internal system clock chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 353 10.2.4 timer d (1) timers d0 to d3 (tmd0 to tmd3) tmdn is a 16-bit timer. it is mainly used as an interval timer for software (n = 0 to 3). starting and stopping tmdn is controlle d by the tmdcen bit of the timer mode control register dn (tmcdn) (n = 0 to 3). division by the prescaler can be selected for the count clock from among f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, and f xx /512 by the csn0 to csn2 bits of the tmcdn register (f xx : internal system clock). tmdn is read-only in 16-bit units. tmd1 fffff550h 0000h tmd2 fffff560h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tmd0 fffff540h 0000h address after reset 0 tmd3 fffff570h 0000h the conditions for which the tmdn register becomes 0000h are shown below (n = 0 to 3). ? reset input ? tmdcaen bit = 0 ? tmdcen bit = 0 ? match of tmdn register and cmdn register ? overflow cautions 1. if the tmdcaen bit of the tmcdn re gister is cleared (0), a reset is performed asynchronously. 2. if the tmdcen bit of the tmcdn register is cleared (0), a reset is performed, in synchronization with the internal clock. similarly, a synch ronized reset is performed after a match with the cmdn regi ster and after an overflow. 3. the count clock must not be changed during a ti mer operation. if it is to be overwritten, it should be overwritten after the tmdcen bit is cleared (0). 4. up to 4 internal system clocks are required after a value is set in the tmdcen bit until the set value is transferred to internal unit s. when a count operation begins, the count cycle from 0000h to 0001h diffe rs from subsequent cycles. 5. after a compare match is generated, the timer is cleared at the next count clock. therefore, if the division ratio is large, the timer value may not be zero even if the timer value is read immediately after a match interrupt is generated. chapter 10 timer/counter function (real-time pulse unit) 354 user?s manual u14359ej5v1ud (2) compare registers d0 to d3 (cmd0 to cmd3) cmdn and the tmdn register count value are comp ared, and an interrupt request signal (intcmdn) is generated when a match occurs. tmdn is cleared, in syn chronization with this match. if the tmdcaen bit of the tmcdn register is set to 0, a reset is performed a synchronously, and the registers are initialized (n = 0 to 3). the cmdn registers are configured with a master/slave configuration. when a cmdn register is written, data is first written to the master register and then the master register data is tr ansferred to the slave register. in a compare operation, the slave register value is compared with the count value of the tmdn register. when a cmdn register is read, data in the master side is read out. cmdn can be read or written in 16-bit units. cautions 1. a write operation to a cmdn register requires 4 internal system clocks until the value that was set in the cmdn register is tran sferred to internal un its. when writing continuously to the cmdn regi ster, be sure to reserve a ti me interval of at least 4 internal system clocks. 2. the cmdn register can be overwritten on ly once in a single tmdn register cycle (from 0000h until an intcmdn interrupt is generated due to a matc h of the tmdn register and cmdn register). if this cannot be secured by the application, make sure that the cmdn register is not overwritte n during timer operation. 3. note that a match signal will be generated after an overfl ow if a value less than the counter value is written in the cmdn regist er during tmdn register operation (figure 10- 13). cmd1 fffff552h 0000h cmd2 fffff562h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cmd0 fffff542h 0000h address after reset 0 cmd3 fffff572h 0000h chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 355 figure 10-13. example of ti ming during tmdn operation (a) when tmdn < cmdn tmdn tmdcaen tmdcen cmdn intcmdn mn n n remark m = tmdn value when overwritten n = cmdn value when overwritten m < n (b) when tmdn > cmdn tmdn tmdcaen tmdcen cmdn intcmdn m ffffh n n n remark m = tmdn value when overwritten n = cmdn value when overwritten m > n chapter 10 timer/counter function (real-time pulse unit) 356 user?s manual u14359ej5v1ud 10.2.5 timer d control registers (1) timer mode control register s d0 to d3 (tmcd0 to tmcd3) the tmcdn registers control the operation of timer dn (n = 0 to 3). these registers can be read or wr itten in 8-bit or 1-bit units. caution the tmdcaen and other bits cannot be set at the same time. the other bits and the registers of the other tmdn units should a lways be set after the tmdcaen bit has been set. (1/2) 7 6 5 4 3 2 <1> <0> address after reset tmcd0 0 cs02 cs01 cs00 0 0 tmdce0 tmdcae0 fffff544h 00h tmcd1 0 cs12 cs11 cs10 0 0 tmdce1 tmdcae1 fffff554h 00h tmcd2 0 cs22 cs21 cs20 0 0 tmdce2 tmdcae2 fffff564h 00h tmcd3 0 cs32 cs31 cs30 0 0 tmdce3 tmdcae3 fffff574h 00h bit position bit name function count enable select selects the tmdn internal count clock cycle (n = 0 to 3). csn2 csn1 csn0 count cycle 0 0 0 f xx /4 0 0 1 f xx /8 0 1 0 f xx /16 0 1 1 f xx /32 1 0 0 f xx /64 1 0 1 f xx /128 1 1 0 f xx /256 1 1 1 f xx /512 6 to 4 csn2 to csn0 (n = 0 to 3) caution the csn2 to csn0 bits must not be changed during timer operation. if they are to be changed, they must be changed after setting the tmdcen bit to 0. if these bits are overwritten during timer operation, operation cannot be guaranteed. remark f xx : internal system clock 1 tmdcen (n = 0 to 3) count enable controls the operation of tmdn (n = 0 to 3). 0: count disabled (stops at 0000h and does not operate) 1: counting operation is performed caution the tmdcen bit is not cleared even if a match is detected by the compare operation. to stop the count operation, clear the tmdcen bit. chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 357 (2/2) bit position bit name function 0 tmdcaen (n = 0 to 3) clock action enable controls the internal count clock (n = 0 to 3). 0: the entire tmdn unit is reset asyn chronously. the supply of input clocks to the tmdn unit stops. 1: input clocks are supplied to the tmdn unit cautions 1. when the tmdcaen bit is set to 0, the tmdn unit can be asynchronously reset. 2. when tmdcaen = 0, the tmdn unit is in a reset state. therefore, to operate tmdn, the tmdcaen bit must be set to 1. 3. if the tmdcaen bit is cleared to 0, all the registers of the tmdn unit are initialized. if tmdcaen is set to 1 again, be sure all the registers of the tmdn unit have been set again. chapter 10 timer/counter function (real-time pulse unit) 358 user?s manual u14359ej5v1ud 10.2.6 timer d operation (1) compare operation tmdn can be used for a compare operation in which the va lue that was set in a compare register (cmdn) is compared with the tmdn count value (n = 0 to 3). if a match is detected by the compare operation, an in terrupt (intcmdn) is generated. the generation of the interrupt causes tmdn to be cleared (0) at the next count timing. this function enables timer d to be used as an interval timer. cmdn can also be set to 0. in this case, when an overflow occurs and tmdn becomes 0, a match is detected and intcmdn is generated. although the tmdn value is cleared (0) at the next count timing, intcmdn is not generated by this match. figure 10-14. tmd0 compar e operation example (1/2) (a) when cmd0 is set to n (non-zero) 1 0 n n tmd0 count clock cmd0 tmd0 clear match detected (intcmd0) count up clear remark interval time = (n + 1) (count clock cycle) n = 1 to 65,536 (ffffh) chapter 10 timer/counter function (real-time pulse unit) user?s manual u14359ej5v1ud 359 figure 10-14. tmd0 compar e operation example (2/2) (b) when cmd0 is set to 0 1 0 0 0 ffffh overflow tmd0 count clock cmd0 tmd0 clear match detected (intcmd0) count up clear remark interval time = (ffffh + 2) (count clock cycle) chapter 10 timer/counter function (real-time pulse unit) 360 user?s manual u14359ej5v1ud 10.2.7 application examples (timer d) (1) interval timer this section explains an example in which timer d is used as an interval timer with 16-bit precision. interrupt requests (intcmdn) are output at equal intervals (see figure 10-14 tmd0 compare operation example ). the setup procedure is shown below (n = 0 to 3). <1> set (1) the tmdcaen bit. <2> set each register. ? select the count clock using the csn0 to csn2 bits of the tmcdn register. ? set the compare value in the cmdn register. <3> start counting by setting (1) the tmdcen bit. <4> if the tmdn register and cmdn register va lues match, an intcmdn interrupt is generated. <5> intcmdn interrupts are generated thereafter at equal intervals. remark n = 0 to 3 10.2.8 cautions (timer d) various cautions concerning timer d are shown below. (1) to operate tmdn, first set (1) the tmdcaen bit. (2) up to 4 internal system clocks are required after a value is set in the tmdcen bit until the set value is transferred to internal units. w hen a count operation begins, the count cycle from 0000h to 0001h differs from subsequent cycles. (3) to initialize the tmdn register st atus and start counting again, clear (0) the tmdcen bit and then set (1) the tmdcen bit after an interval of 4 internal system clocks has elapsed. (4) up to 4 internal system clocks are required until the va lue that was set in the cmdn register is transferred to internal units. when writing continuously to the cmdn register, be sure to secure a time interval of at least 4 internal system clocks. (5) the cmdn register can be overwr itten only once during a timer/coun ter operation (from 0000h until an intcmdn interrupt is generated due to a match of the tmdn register and cmdn regist er). if this cannot be secured, make sure that the cmdn register is not overwritten during a ti mer/counter operation. (6) the count clock must not be changed during a timer oper ation. if it is to be overwritten, it should be overwritten after the tmdcen bit is cleared (0). if t he count clock is overwritt en during a timer operation, operation cannot be guaranteed. (7) a match signal will be generated after an overflow if a value less than the counter value is written in the cmdn register during tmdn register operation. remark n = 0 to 3 user?s manual u14359ej5v1ud 361 chapter 11 serial interface function 11.1 features the serial interface function provides two types of seri al interfaces equipped with six transmit/receive channels of which four channels can be used simultaneously. the following two interface formats are available. (1) asynchronous serial interface (uart0 to uart2): 3 channels (2) clocked serial interface (csi0 to csi2): 3 channels uart0 to uart2, which use the method of transmitting/r eceiving one byte of serial data following a start bit, enable full-duplex communication to be performed. csi0 to csi2 transfer data ac cording to three types of sign als (3-wire serial i/o). these signals are the serial clock (sck0 to sck2), serial input (si0 to si 2), and serial output (so0 to so2) signals. 11.1.1 switching between uart and csi modes in the v850e/ma1, since uart0 and csi0 pin and the ua rt1 and csi1 pin are alternate function pins, they cannot be used at the same time. the pmc4 and pfc4 registers must be set in advance (see 14.3.5 port 4 ). also, since uart2 and csi2 have alternate functions as external interrupt request input pins (intp120 and intp130 to intp133), the pmc3 and pfc3 registers must be set in advance (see 14.3.4 port 3 ). if the mode is switched during a transmit or receive operat ion in uartn or csin, operat ion cannot be guaranteed. chapter 11 serial interface function 362 user?s manual u14359ej5v1ud 11.2 asynchronous serial interfaces 0 to 2 (uart0 to uart2) 11.2.1 features ? transfer rate: 300 bps to 1,562.5 kbps (using a dedica ted baud rate generator and an internal system clock of 50 mhz) ? full-duplex communications on-chip receive buffer (rxbn) on-chip transmit buffer (txbn) ? two-pin configuration txdn: transmit data output pin rxdn: receive data input pin ? reception error detection function ? parity error ? framing error ? overrun error ? interrupt sources: 3 types ? reception error interrupt (intsern): interrupt is generated according to the logical or of the three types of reception errors ? reception completion interrupt (intsrn): interrupt is generated when receive data is transferred from the shift register to the receive buffer after serial transfer is completed during a reception enabled state ? transmission completion interrupt (intstn): interr upt is generated when the serial transmission of transmit data (8 or 7 bits) from the shift register is completed ? the character length of transmit/receive data is s pecified according to the asim0 to asim2 registers ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? on-chip dedicated baud rate generator remark n = 0 to 2 chapter 11 serial interface function user?s manual u14359ej5v1ud 363 11.2.2 configuration uartn is controlled by the asynchronous serial interface mode register (asimn), asynchronous serial interface status register (asisn), and asynchronous serial interface transmission status register (asifn) (n = 0 to 2). receive data is held in the receive buffer (rxbn), and trans mit data is written to the transmit buffer (txbn). figure 11-1 shows the configuration of the asynchronous serial interface. (1) asynchronous serial inte rface mode registers 0 to 2 (asim0 to asim2) the asimn register is an 8-bit register for specifying the operation of the asynch ronous serial interface. (2) asynchronous serial interface status registers 0 to 2 (asis0 to asis2) the asisn register consists of a set of flags that indicate the error contents when a reception error occurs. the various reception error flags are set (1) when a re ception error occurs and are reset (0) when the asisn register is read. (3) asynchronous serial interface transmission st atus registers 0 to 2 (asif0 to asif2) the asifn register is an 8-bit regist er that indicates the status when a transmit operation is performed. this register consists of a transmit buffer data flag, which indicates the hold status of txbn data, and the transmit shift register data flag, which indi cates whether transmission is in progress. (4) reception control parity check receive operations are controlled according to the cont ents set in the asimn register. a check for parity errors is also performed during a receive operation, an d if an error is detected, the value corresponding to the error contents is set in the asisn register. (5) receive shift register this is a shift register that converts the serial data t hat was input to the rxdn pin to parallel data. one byte of data is received, and if a stop bi t is detected, the receive data is transferred to the receive buffer. this register cannot be directly manipulated. (6) receive buffer (rxbn) rxbn is an 8-bit buffer register for holding receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, re ceive data is transferred from the rece ive shift register to the receive buffer, in synchronization with the end of the shift-in processing of one frame. also, the reception completion interrupt request (intsr n) is generated by the transfe r of data to the receive buffer. (7) transmit shift register this is a shift register that converts the parallel data that was transferred from the transmit buffer to serial data. when one byte of data is transferred from the transmit buf fer, the shift register data is output from the txdn pin. the transmission completion interrupt request (intstn) is generated in synchroniz ation with the completion of transmission of one frame. this register cannot be directly manipulated. chapter 11 serial interface function 364 user?s manual u14359ej5v1ud (8) transmit buffer (txbn) txbn is an 8-bit buffer for transmit data. a transmit oper ation is started by writing transmit data to txbn. (9) addition of transmission control parity transmit operations are controlled by adding a start bit, parit y bit, or stop bit to the data that is written to the txbn register, according to the contents that were set in the asimn register. figure 11-1. asynchronous se rial interface block diagram parity framing overrun internal bus asynchronous serial interface mode register n (asimn) receive buffer (rxbn) receive shift register reception control parity check transmit buffer (txbn) transmit shift register addition of transmission control parity brgn intsern intsrn intstn rxdn txdn remark n = 0 to 2 chapter 11 serial interface function user?s manual u14359ej5v1ud 365 11.2.3 control registers (1) asynchronous serial inte rface mode registers 0 to 2 (asim0 to asim2) these are 8-bit registers for controlling t he transfer operations of uart0 to uart2. these registers can be read or wr itten in 8-bit or 1-bit units. cautions 1. when using uartn, set the external pins related to the uartn func tion in the control mode, set clock select register n (cksrn) and baud ra te generator control register n (brgcn). then set the uartcaen bit to 1 before setting the other bits. 2. be sure to set uartcaen bit = 1 and rxen bit = 1 while the rx dn pin is high level. if uartcaen bit = 1 and rxen bit = 1 is set wh ile the rxdn pin is lo w level, reception will inadvertently start. chapter 11 serial interface function 366 user?s manual u14359ej5v1ud (1/3) <7> <6> <5> 4 3 2 1 0 address after reset asim0 uartcae0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 fffffa00h 01h asim1 uartcae1 txe1 rxe1 ps11 ps10 cl1 sl1 isrm1 fffffa10h 01h asim2 uartcae2 txe2 rxe2 ps21 ps20 cl2 sl2 isrm2 fffffa20h 01h bit position bit name function 7 uartcaen (n = 0 to 2) clock enable controls the operation clock (n = 0 to 2). 0: stops supply of clocks to uartn unit 1: supplies clocks to uartn unit cautions 1. when the uartcaen bit is set to 0, the uartn unit can be asynchronously reset note . 2. when uartcaen = 0, the uartn unit is in a reset state. therefore, to operate uartn, the uartcaen bit must be set to 1. 3. when the uartcaen bit is changed from 1 to 0, all registers of the uartn unit are initialized. when the uartcaen is set to 1 again, the uartn unit registers must be set again. the txdn pin output is always high le vel in the transmission disable state, irrespective of the setting of the uartcaen bit. 6 txen (n = 0 to 2) transmit enable specifies whether transmis sion is enabled or disabled. 0: transmission is disabled 1: transmission is enabled cautions 1. on startup, set uartcaen to 1 and then set txen to 1. to stop transmission, clear txen to 0 and then uartcaen to 0. 2. when the transmission unit status is to be initialized, the transmission status may not be able to be initialized unless the txen bit is set (1) again after an interval of two cycles of the basic clock has elapsed since the txen bit was cleared (0) (for the basic clock, see 11.2.6 (1) (a) basic clock (clock)). note the asisn, asifn, and rxbn registers are reset. chapter 11 serial interface function user?s manual u14359ej5v1ud 367 (2/3) bit position bit name function 5 rxen (n = 0 to 2) receive enable specifies whether reception is enabled or disabled. 0: reception is disabled note 1: reception is enabled cautions 1. on startup, set uartcaen to 1 and then set rxen to 1. to stop transmission, clear rxen to 0 and then uartcaen to 0. 2. when the reception unit status is to be initialized, the reception status may not be able to be initialized unless the rxen bit is set (1) again after an interval of two cycles of the basic clock has elapsed since the rxen bit was cleared (0) (for the basic clock, see 11.2.6 (1) (a) basic clock (clock)) . 4, 3 psn1, psn0 (n = 0 to 2) parity select controls the parity bit. psn1 psn0 transmit operation receive operation 0 0 do not output a parity bit receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity cautions 1. to overwrite the psn1 and psn0 bits, first clear (0) the txen and rxen bits. 2. if ?0 parity? is selected for reception, no parity judgement is made. therefore, no error interrupt is generated because the pen bit of the asisn register is not set. ? even parity if the transmit data contains an odd number of bits with the value ?1?, the parity bit is set (1). if it contains an even number of bits with the value ?1?, the parity bit is cleared (0). this controls the num ber of bits with the value ?1? contained in the transmit data and the parity bit so that it is an even number. during reception, the number of bits wi th the value ?1? contained in the receive data and the parity bit is counted, and if the number is odd, a parity error is generated. ? odd parity in contrast to even parity, odd parity c ontrols the number of bits with the value ?1? contained in the transmit data and the parity bit so that it is an odd number. during reception, the number of bits wi th the value ?1? contained in the receive data and the parity bit is counted, and if the number is even, a parity error is generated. note when reception is disabled, the receive shift register d oes not detect a start bit. no shift-in processing or transfer processing to the receive buffer is perfo rmed, and the contents of the receive buffer are retained. when reception is enabled, the receive shift operat ion starts, in synchroniza tion with the detection of the start bit, and when the reception of one frame is completed, the contents of the receive shift register are transferred to the receive buffer. a reception completion interrupt (intsrn) is also generated, in synchronizat ion with the transfer to the receive buffer. chapter 11 serial interface function 368 user?s manual u14359ej5v1ud (3/3) bit position bit name function 4, 3 psn1, psn0 (n = 0 to 2) ? 0 parity during transmission, the parity bit is cleared (0) regardless of the transmit data. during reception, no parity error is gener ated because no parity bit is checked. ? no parity no parity bit is added to transmit data. during reception, the receive data is considered to have no parity bit. no parityerror is generated because there is no parity bit. 2 cln (n = 0 to 2) character length specifies the character length of the transmit/receive data. 0: 7 bits 1: 8 bits caution to overwrite the cln bit, first clear (0) the txen and rxen bits. 1 sln (n = 0 to 2) stop bit length specifies the stop bit length of the transmit data. 0: 1 bit 1: 2 bits cautions 1. to overwrite the sln bi t, first clear (0) the txen bit. 2. since reception always operates by using a single stop bit length, the sln bit setting does not affect receive operations. 0 isrmn (n = 0 to 2) interrupt serial receive mode specifies whether the generation of recept ion completion interrupt requests when an error occurs is enable or disabled. 0: a reception error interrupt request (intsern) is generated when an error occurs. in this case, no reception completi on interrupt request (intsrn) is generated. 1: a reception completion interrupt request (intsrn) is generated when an error occurs. in this case, no reception error inte rrupt request (intsern) is generated. caution to overwrite the isrmn bit, first clear (0) the rxen bit. chapter 11 serial interface function user?s manual u14359ej5v1ud 369 (2) asynchronous serial interface status registers 0 to 2 (asis0 to asis2) these registers, which consist of 3-bit error flags ( pen, fen, and oven), indicate the error status when uartn reception is completed (n = 0 to 2). the status flag, which indicates a reception error, alwa ys indicates the status of t he error that occurred most recently. that is, if the same error occurred several times before the receive data was read, this flag would hold only the status of the error that occurred last. the asisn register is cleared to 00h by a read operat ion. when a reception error occurs, the receive buffer (rxbn) should be read after the asisn register is read. these registers are read-only in 8-bit units. caution when the uartcaen bit or r xen bit of the asimn register is set to 0, or when the asisn register is read, the pen, fen, and oven bi ts of the asisn register are cleared (0). 7 6 5 4 3 2 1 0 address after reset asis0 0 0 0 0 0 pe0 fe0 ove0 fffffa03h 00h asis1 0 0 0 0 0 pe1 fe1 ove1 fffffa13h 00h asis2 0 0 0 0 0 pe2 fe2 ove2 fffffa23h 00h bit position bit name function 2 pen (n = 0 to 2) parity error this is a status flag that indicates a parity error. 0: when the uartcaen and rxen bits of the asimn register are cleared to 0 or when the asisn register is read 1: when reception was completed, the receive data parity did not match the parity bit caution the operation of the pen bit differs according to the settings of the psn1 and psn0 bits of the asimn register. 1 fen (n = 0 to 2) framing error this is a status flag that indicates a framing error. 0: when the uartcaen and rxen bits of the asimn register are cleared to 0 or when the asisn register is read 1: when reception was completed, no stop bit was detected caution for receive data stop bits, only the first bit is checked regardless of the stop bit length. 0 oven (n = 0 to 2) overrun error this is a status flag that indicates an overrun error. 0: when the uartcaen and rxen bits of the asimn register are cleared to 0 or when the asisn register is read 1: uartn completed the next receive operation before reading the rxbn receive data. caution when an overrun error occurs, the next receive data value is not written to the rxbn register and the data is discarded. chapter 11 serial interface function 370 user?s manual u14359ej5v1ud (3) asynchronous serial interface transmission st atus registers 0 to 2 (asif0 to asif2) these registers, which consist of 2-bit status flags, indicate the status during transmission. by writing the next data to the txbn r egister after data is transferred from the txbn register to transmit shift register, transmit operations can be performed contin uously without suspension even during an interrupt interval. when transmission is performed continuously, data should be written after referencing the txbfn bit of the asifn register to prevent writ ing to the txbn register by mistake. these registers are read-only in 8-bit or 1-bit units. remark n = 0 to 2 7 6 5 4 3 2 <1> <0> address after reset asif0 0 0 0 0 0 0 txbf0 txsf0 fffffa05h 00h asif1 0 0 0 0 0 0 txbf1 txsf1 fffffa15h 00h asif2 0 0 0 0 0 0 txbf2 txsf2 fffffa25h 00h bit position bit name function 1 txbfn (n = 0 to 2) transmit buffer flag this is a transmit buffer data flag. 0: no data to be transferred next exists in the txbn register (when the uartcaen or txen bit of the asimn register is cleared to 0 or when data has been transferred to the transmit shift register) 1: data to be transferred next exists in the txbn register (when data has been written to the txbn register). caution to successively transmit data, make sure that this flag is 0, and then write data to the txbn register. if data is written to the txbn register while this flag is 1, the transmit data cannot be guaranteed. 0 txsfn (n = 0 to 2) transmit shift flag this is a transmit shift register data fl ag. it indicates the transmission status of uartn. 0: initial status or waiting for transmission (when the uartcaen or txen bit of the asimn register is cleared to 0 or if no next data is transferred from the txbn register after completion of transfer). 1: under transmission (if data is tran sferred from the txbn register) caution before initializing the transmit unit, make sure that this flag is 0 after occurrence of the transmission completion interrupt. if initialization is executed while this flag is 1, the transmit data is not guaranteed. chapter 11 serial interface function user?s manual u14359ej5v1ud 371 (4) receive buffer registers 0 to 2 (rxb0 to rxb2) these are 8-bit buffer registers for st oring parallel data that had been conver ted by the receive shift register. when reception is enabled (rxen = 1 in the asimn register ), receive data is transferred from the receive shift register to the receive buffer, in synchronization with the completion of the shift-in processing of one frame. also, a reception completion interrupt request (intsrn) is generated by the transfer to the receive buffer. for information about the timing for gener ating these interrupt requests, see 11.2.5 (4) receive operation . if reception is disabled (rxen = 0 in the asimn registe r), the contents of the receive buffer are retained, and no processing is performed for transferring data to the receive buffer even when the shift-in processing of one frame is completed. also, no reception completion interrupt is generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxbn register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overrun error occurs, the receive data at that time is not transferred to the rxbn register. except when a reset is input, the rxbn register becomes ffh even when uartcaen = 0 in the asimn register. these registers are read-only in 8-bit units. remark n = 0 to 2 7 6 5 4 3 2 1 0 address after reset rxb0 rxb07 rxb06 rxb05 rxb04 rxb03 rxb02 rxb01 rxb00 fffffa02h ffh rxb1 rxb17 rxb16 rxb15 rxb14 rxb13 rxb12 rxb11 rxb10 fffffa12h ffh rxb2 rxb27 rxb26 rxb25 rxb24 rxb23 rxb22 rxb21 rxb20 fffffa22h ffh bit position bit name function 7 to 0 rxbn7 to rxbn0 (n = 0 to 2) receive buffer stores receive data. 0 can be read for rxbn7 when 7-bi t character data is received. chapter 11 serial interface function 372 user?s manual u14359ej5v1ud (5) transmit buffer registers 0 to 2 (txb0 to txb2) these are 8-bit buffer registers for setting transmit data. when transmission is enabled (txen = 1 in the asimn regi ster), the transmit operat ion is started by writing data to txbn. when transmission is disabled (txen = 0 in the asimn regist er), even if data is written to txbn, the value is ignored. the txbn data is transferred to the transmit shift regi ster, and a transmission completion interrupt request (intstn) is generated, in synchron ization with the completion of the transmission of one frame from the transmit shift register. for information about the timing for generating these interrupt requests, see 11.2.5 (2) transmit operation . when txbfn = 1 in the asifn register, wr iting must not be performed to txbn. these registers can be read or written in 8-bit units. remark n = 0 to 2 7 6 5 4 3 2 1 0 address after reset txb0 txb07 txb06 txb05 txb04 txb 03 txb02 txb01 txb00 fffffa04h ffh txb1 txb17 txb16 txb15 txb14 txb 13 txb12 txb11 txb10 fffffa14h ffh txb2 txb27 txb26 txb25 txb24 txb 23 txb22 txb21 txb20 fffffa24h ffh bit position bit name function 7 to 0 txbn7 to txbn0 (n = 0 to 2) transmit buffer writes transmit data. chapter 11 serial interface function user?s manual u14359ej5v1ud 373 11.2.4 interrupt requests the following three types of interrupt reques ts are generated from uartn (n = 0 to 2). ? reception error interrupt (intsern) ? reception completion interrupt (intsrn) ? transmission completion interrupt (intstn) the default priorities among these three types of interrupt requests is, from hi gh to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt. table 11-1. generated inte rrupts and default priorities interrupt priority reception error 1 reception completion 2 transmission completion 3 (1) reception error interrupt (intsern) when reception is enabled, a recepti on error interrupt is generated accordi ng to the logical or of the three types of reception errors explained for the asisn regist er. whether a reception error interrupt (intsern) or a reception completion interrupt (intsrn) is generated when an error occurs can be specified using the isrmn bit of the asimn register. when reception is disabled, no rec eption error interrupt is generated. (2) reception completion interrupt (intsrn) when reception is enabled, a reception completion in terrupt is generated when dat a is shifted in to the receive shift register and transferred to the receive buffer. a reception completion interrupt request can be generated in place of a reception error interrupt according to the isrmn bit of the asimn register ev en when a reception error has occurred. when reception is disabled, no reception completion interrupt is generated. (3) transmission completion interrupt (intstn) a transmission completion interrupt is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmit shift register. chapter 11 serial interface function 374 user?s manual u14359ej5v1ud 11.2.5 operation (1) data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consis ts of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 11-2. the character bit length within one data frame, the type of parity, and the stop bit length are specified by the asynchronous serial interface mode register n (asimn) (n = 0 to 2). also, data is transferred with the least significant bit (lsb) first. figure 11-2. asynchronous serial interface transmit/receive data format 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits chapter 11 serial interface function user?s manual u14359ej5v1ud 375 (2) transmit operation when uartcaen is set to 1 in the asimn regist er, a high level is output to the txdn pin. then, when txen is set to 1 in the asimn register, transmission is enabled, and the transmit operation is started by writing transmit data to transmi t buffer register n (txbn) (n = 0 to 2). (a) transmission enabled state this state is set by the txen bit in the asimn register (n = 0 to 2). ? txen = 1: transmission enabled state ? txen = 0: transmission disabled state however, when the transmission enabled state is se t, to use uart0 and uart1, which share pins with clocked serial interfaces 0 and 1 (csi0 and csi1), the csicaen bit of clocked serial interface mode registers 0 and 1 (csim0 and csim1) should be set to 0. since uartn does not have a cts (transmission enab led signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (b) starting a transmit operation in the transmission enabled state, a transmit operation is started by writing transmit data to transmit buffer register n (txbn). when a transm it operation is started, the data in txbn is transferred to transmit shift register n. then, transmit shift register n out puts data to the txdn pin sequentially beginning with the lsb (the transmit data is transferred sequentially st arting with the start bit). the start bit, parity bit, and stop bits are added automatically (n = 0 to 2). (c) transmission interrupt request when the transmit shift register becomes empty, a transmission comple tion interrupt request (intstn) is generated. the timing for generating the intstn inte rrupt differs according to the specification of the stop bit length. the intstn interrupt is generated at the same time that the last stop bit is output (n = 0 to 2). if the data to be transmitted next has not been written to the txbn regi ster, the transmit operation is suspended. caution normally, when transmit shift register n becomes empty, a transmission completion interrupt (intstn) is gene rated. however, no transmission completion interrupt (intstn) is generated if transmit shift regi ster n becomes empty due to the input of a reset. chapter 11 serial interface function 376 user?s manual u14359ej5v1ud figure 11-3. asynchronous serial interf ace transmission comple tion interrupt timing start stop d0 d1 d2 d6 d7 parity parity txdn (output) intstn (output) start d0 d1 d2 d6 d7 txdn (output) intstn (output) stop (a) stop bit length: 1 (b) stop bit length: 2 remark n = 0 to 2 chapter 11 serial interface function user?s manual u14359ej5v1ud 377 (3) continuous transmission operation uartn can write the next data to the txbn register at the time that the transmit shift register starts the shift operation. this enables an efficient transmission rate to be realized by continuously transmitting data even during interrupt servicing after the transmission of one dat a frame (n = 0 to 2). by reading the txsfn bit of the asifn register after the transmission completion inte rrupt has occurred, data can be efficiently written to the txbn register two times (2 bytes) without havi ng to wait for the transmission time of 1 data frame. when continuous transmission is performed, data should be written after referencing the asifn register to confirm the transmission status and w hether or not data can be written to the txbn register (n = 0 to 2). caution the txbfn and txsfn bits of the asifn regi ster change from ?10? to ?11?, and to ?01? during continuous transmission. to check the status, therefore, do not use a combination of the txbfn and txsfn bits for judgment. use only the txbfn bit for judgment when executing continuous transmission. txbfn enables/disables writi ng to the txbn register 0 enables writing. 1 disables writing. caution to successively transmit data, make sure that the txbfn bit is 0 after the first transmit data (first byte) has been written to the txbn regi ster, before writing the next transmit data (second byte) to the txbn register . if data is written to the txbn register while the txbfn bit is 1, the transmit data is not guaranteed. while successive transmission is under execution, whet her data has been written to the txbn register can be checked by checking the txsfn bit after occurr ence of the transmission completion interrupt. txsfn transmission status 0 transmission has been completed. 1 transmission is under execution. cautions 1. before initiali zing the transmit unit after comple tion of successive transmission, make sure that the txsfn bit is 0 after the transmission completion interrupt has occurred. if initialization is executed while the txsfn bit is 1, the transmit data cannot be guaranteed. 2. while data is successively transmitted, an overrun error may occur because the next transmission may be completed before the intstn interrupt servicing is executed after transmission of 1 data frame. the overrun error can be detected by incorporating a program that can count the number of transmit data and by refere ncing the txsfn bit. chapter 11 serial interface function 378 user?s manual u14359ej5v1ud figure 11-4. continuous transmission processing flow no no no no yes yes yes yes txbfn = 0 when asifn register is read? set registers. write first byte of transmit data to txbn register. write second byte of transmit data to txbn register. interrupt occurs. transfer executed necessary number of times? write transmit data to txbn register. txsfn = 1 when asifn register is read? txsfn = 0 when asifn register is read? end of transmission processing wait for interrupt. remark n = 0 to 2 chapter 11 serial interface function user?s manual u14359ej5v1ud 379 (a) starting procedure the procedure for starting continuous transmission is shown below. figure 11-5. continuous tr ansmission starting procedure txdn (output) data (1) data (2) <5> <1> <2> <4> intstn (output) txbn register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asifn register (txbfn, txsfn bits) 00 11 note 11 01 01 11 01 11 transmit shift register start bit stop bit stop bit start bit 10 note refer to 11.2.7 cautions (2) . remark n = 0 to 2 asifn register transmission starting procedure internal operation txbfn txsfn ? set transmission mode <1> start transmission unit 0 0 ? write data (1) 1 0 <2> generate start bit start data (1) transmission ? read asifn register (confirm that txbfn bit = 0) 1 0 0 0 1 note 1 1 1 ? write data (2) < chapter 11 serial interface function 380 user?s manual u14359ej5v1ud (b) ending procedure the procedure for ending continuous transmission is shown below. figure 11-6. continuous transmission ending procedure txdn (output) data (m ? 1) data (m) <11> <7> <6> <8> <10> intstn (output) txbn register data (m ? 1) data (m ? 1) data (m) ffh data (m) <9> asifn register (txbfn and txsfn bits) uartcaen bit or txen bit 11 01 11 01 00 transmit shift register start bit stop bit stop bit start bit remark n = 0 to 2 asifn register transmission ending procedure internal operation txbfn txsfn <6> transmission of data (m ? 2) is in progress 1 1 <7> generate intst interrupt ? read asifn register (confirm that the txbfn bit = 0) 0 0 1 1 ? write data (n) <8> generate start bit start data (m ? 1) transmission < chapter 11 serial interface function user?s manual u14359ej5v1ud 381 (4) receive operation the awaiting reception state is set by setting uartcaen to 1 in the asimn register and then setting rxen to 1 in the asimn register. to start the receive operation, start sampling at the falling edge when the falling of the rxdn pin is detected. if the rxdn pin is low level at a start bit sampling point, the start bit is recognized. when the receive operation begins, serial data is stored sequentially in the receive shift register according to the baud rate that was set. a reception completion in terrupt (intsrn) is generated each time the reception of one frame of data is completed. normally, the receive data is transferred from the receive buffer (rxbn) to memory by this interrupt servicing (n = 0 to 2). (a) reception enabled state the receive operation is set to the reception enabled state by setting the rxen bit in the asimn register to 1 (n = 0 to 2). ? rxen = 1: reception enabled state ? rxen = 0: reception disabled state however, when the reception enabled state is se t, to use uart0 and uart1, which share pins with clocked serial interfaces 0 and 1 (csi0 and csi1), the operation of csin must be disabled by setting the csicaen bit of clocked serial interface mode regist ers 0 and 1 (csim0 and csim1) to 0 (n = 0 to 2). in the reception disabled state, the reception hardware stands by in the in itial state. at this time, the contents of the receive buffer are retained, and no re ception completion interrupt or reception error interrupt is generated. (b) starting a receive operation a receive operation is started by the detection of a start bit. the rxdn pin is sampled using the serial clock fr om the baud rate generator (brgn) (n = 0 to 2). (c) reception completion interrupt when rxen = 1 in the asimn register and the reception of one frame of data is completed (the stop bit is detected), a reception completion inte rrupt (intsrn) is generated and t he receive data within the receive shift register is transferred to rxbn at the same time (n = 0 to 2). also, if an overrun error occurs, the receive data at that time is not transferred to the receive buffer (rxbn), and either a reception completion interrupt (i ntsrn) or a reception error interrupt (intsern) is generated according to the setting of isrmn bit of the asimn register. if a parity error or framing error occurs during recept ion operation, the reception operation continues up to the position at which the stop bit is received. after completion of reception, a reception completion interrupt (intsrn) or reception e rror interrupt (intsern) occurs, acco rding to the setting of the isrmn bit of the asimn register (the rece ive data in the receive shift regi ster is transferred to rxbn). if the rxen bit is reset (0) during a receive operation, the receive operation is immediately stopped. the contents of the receive buffer (rxbn) and of the asynchr onous serial interface status register (asisn) at this time do not change, and no reception completion interrupt (intsrn) or reception error interrupt (intsern) is generated. no reception completion interrupt is generated when rxen = 0 (reception is disabled). chapter 11 serial interface function 382 user?s manual u14359ej5v1ud figure 11-7. asynchronous serial interf ace reception completion interrupt timing start d0 d1 d2 d6 d7 rxdn (input) intsrn (output) rxbn register parity stop cautions 1. be sure to read the recei ve buffer (rxbn) when a reception error occurs. unless rxbn is read, an o verrun error occurs when the n ext data is received, causing the reception error status to persist. 2. data is received always with a st op bit. the second stop bit is ignored. remark n = 0 to 2 (5) reception error the three types of errors that can occur during a re ceive operation are a parity error, framing error, and overrun error. the data reception resu lt is that the various flags of the asisn register are set (1), and a reception error interrupt (intsern) or a reception completion interrupt (intsrn) is generated at the same time. the isrmn bit of the asimn register spec ifies whether intsern or intsrn is generated. the type of error that occurred during reception can be ascertained by reading the contents of the asisn register during the intsern or intsrn interrupt servicing. the contents of the asisn register are reset (0) by reading the asisn register (if the next reception data contains an error, the corresponding error flag is set (1)). table 11-2. reception error causes error flag reception error cause pen parity error the parity specification during transm ission did not match the parity of the reception data fen framing error no stop bit was detected oven overrun error the reception of the next data was completed before data was read from the receive buffer remark n = 0 to 2 chapter 11 serial interface function user?s manual u14359ej5v1ud 383 (a) separation of rece ption error interrupt a reception error interrupt can be separated from the intsrn interrupt and generated as an intsern interrupt by clearing the isrmn bit of t he asimn register (n = 0 to 2) to 0. figure 11-8. when reception error interrupt is se parated from ints rn interrupt (isrmn bit = 0) (a) no error occurs during reception (b) an e rror occurs during reception intsrn does not occur intsrn (output) (reception completion interrupt) intsern (output) (reception error interrupt) intsrn (output) (reception completion interrupt) intsern (output) (reception error interrupt) remark n = 0 to 2 figure 11-9. when reception error interrupt is in cluded in intsrn inte rrupt (isrmn bit = 1) (a) no error occurs during reception (b) an erro r occurs during reception intsern does not occur intsrn (output) (reception completion interrupt) intsern (output) (reception error interrupt) intsrn (output) (reception completion interrupt) intsern (output) (reception error interrupt) remark n = 0 to 2 chapter 11 serial interface function 384 user?s manual u14359ej5v1ud (6) parity types and co rresponding operation a parity bit is used to detect a bit error in communication data. normally, the same type of parity bit is used at the transmission and reception sides. (a) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the value ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 (ii) during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (b) odd parity (i) during transmission in contrast to even parity, the parity bit is contro lled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 (ii) during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (d) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no parity bit. since there is no parity bit, no parity error is generated. chapter 11 serial interface function user?s manual u14359ej5v1ud 385 (7) receive data noise filter the rxdn signal is sampled at the rising edge of the prescaler output clock. if the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see figure 11- 11 ). see 11.2.6 (1) (a) basic clock (clock) regarding the basic clock. also, since the circuit is configured as shown in figur e 11-10, internal processing during a receive operation is delayed by up to 2 clocks accord ing to the external signal status. figure 11-10. noise filter circuit rxdn q clock in ld_en q in internal signal a internal signal b match detector remark n = 0 to 2 figure 11-11. timing of rx dn signal judg ed as noise internal signal a clock rxdn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match remark n = 0 to 2 chapter 11 serial interface function 386 user?s manual u14359ej5v1ud 11.2.6 dedicated baud rate genera tors 0 to 2 (brg0 to brg2) a dedicated baud rate generator, which consists of a s ource clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception in uartn. the dedicated baud rate generator output can be selected as the serial clock for each channel. separate 8-bit counters exist fo r transmission and for reception. (1) baud rate genera tor configuration figure 11-12. baud rate generator configuration f xx /2 f xx f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 clock (f xclk ) selector uartcaen 8-bit counter match detector baud rate brgcn: brgn7 to brgn0 1/2 uartcaen and txen (or rxen) cksrn: tpsn3 to tpsn0 remarks 1 . n = 0 to 2 2. f xx : internal system clock (a) basic clock (clock) when uartcaen = 1 in the asimn register, the clock selected according to the tpsn3 to tpsn0 bits of the cksrn register is supplied to the transmission/rec eption unit. this clock is called the basic clock, and its frequency is referred to as f xclk . when uartcaen = 0, the clock signal is fixed at low level. chapter 11 serial interface function user?s manual u14359ej5v1ud 387 (2) serial clock generation a serial clock can be generated according to the setti ngs of the cksrn and brgcn registers (n = 0 to 2). the basic clock input to the 8-bit counter is selected according to the tpsn3 to tpsn0 bits of the cksrn register. the 8-bit counter divisor value can be selected acco rding to the brgn7 to brgn0 bits of the brgcn register. (a) clock select registers 0 to 2 (cksr0 to cksr2) the cksrn register is an 8-bit register for select ing the basic block according to the tpsn3 to tpsn0 bits. the clock selected by the tpsn3 to tpsn0 bits becomes the basic clock of the transmission/ reception module. its frequency is referred to as f xclk . these registers can be read or written in 8-bit units. cautions 1. the maximum allowabl e frequency of the basic clock (f xclk ) is 25 mhz. therefore, when the system clock? s frequency is 50 mhz, bits tp sn3 to tpsn0 cannot be set to 0000b (n = 0 to 2). if the system clock frequency is 50 mhz, set the tpsn3 to tp sn0 bits to a value other than 0000b and set the uartcaen bi t of the asimn register to 1. 2. if the tpsn3 to tpsn0 bits are to be overwritten, the uartcaen bit of the asimn register should be set to 0 first. 7 6 5 4 3 2 1 0 address after reset cksr0 0 0 0 0 tps03 tps02 tps01 tps00 fffffa06h 00h cksr1 0 0 0 0 tps13 tps12 tps11 tps10 fffffa16h 00h cksr2 0 0 0 0 tps23 tps22 tps21 tps20 fffffa26h 00h bit position bit name function specifies the basic clock. tpsn3 tpsn2 tpsn1 tpsn0 basic clock (f xclk ) 0 0 0 0 f xx 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1,024 1 0 1 1 f xx /2,048 1 1 arbitrary arbitrary setting prohibited 3 to 0 tpsn3 to tpsn0 (n = 0 to 2) remark f xx : internal system clock chapter 11 serial interface function 388 user?s manual u14359ej5v1ud (b) baud rate generator control re gisters 0 to 2 (brgc0 to brgc2) the brgcn register is an 8-bit regist er that controls the baud rate (serial transfer speed) of uartn. these registers can be read or written in 8-bit units. caution if the brgn7 to brgn0 bits are to be overwritten, txen and rxen should be set to 0 in the asimn register first (n = 0 to 2). 7 6 5 4 3 2 1 0 address after reset brgc0 mdl07 mdl06 mdl05 mdl04 mdl03 mdl02 mdl01 mdl00 fffffa07h ffh brgc1 mdl17 mdl16 mdl15 mdl14 mdl13 mdl12 mdl11 mdl10 fffffa17h ffh brgc2 mdl27 mdl26 mdl25 mdl24 mdl23 mdl22 mdl21 mdl20 fffffa27h ffh bit position bit name function specifies the 8-bit counter?s divisor value. brgn7 brgn6 brgn5 brgn4 brgn3 brgn2 brgn1 brgn0 divisor value (k) serial clock 0 0 0 0 0 x x x ? setting prohibited 0 0 0 0 1 0 0 0 8 f xclk /8 0 0 0 0 1 0 0 1 9 f xclk /9 0 0 0 0 1 0 1 0 10 f xclk /10 1 1 1 1 1 0 1 0 250 f xclk /250 1 1 1 1 1 0 1 1 251 f xclk /251 1 1 1 1 1 1 0 0 252 f xclk /252 1 1 1 1 1 1 0 1 253 f xclk /253 1 1 1 1 1 1 1 0 254 f xclk /254 1 1 1 1 1 1 1 1 255 f xclk /255 7 to 0 brgn7 to brgn0 (n = 0 to 2) remarks 1. f xclk : frequency of basic clock (clock) selected according to tpsn3 to tpsn0 bits of cksrn register. 2. k: value set according to brgn7 to brgn0 bits (k = 8, 9, 10, ..., 255) 3. the baud rate is the output clock for the 8-bit counter divided by 2 4. x: don?t care ? ? ? ? ? ? ? ? ? ? chapter 11 serial interface function user?s manual u14359ej5v1ud 389 (c) baud rate the baud rate is the value obtained according to the following formula. [bps] k 2 f rate baud xclk = f xclk = frequency of basic clock (clock) selected accord ing to tpsn3 to tpsn0 bits of cksrn register. k = value set according to brgn7 to brgn0 bits of brgcn register (k = 8, 9, 10, ..., 255) (d) baud rate error the baud rate error is obtained according to the following formula. [%] 100 1 rate) baud (normal rate baud desired error) with rate (baud rate baud actual (%) error ? = ? ? ? ? ? ? ? ? cautions 1. make sure that the baud rate erro r during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error duri ng reception is within th e allowable baud rate range during reception, which is described in paragraph (4). example: basic clock (clock) frequency = 20 mhz = 20,000,000 hz settings of brgn7 to brgn0 bits in brgcn register = 01000001b (k = 65) target baud rate = 153,600 bps baud rate = 20 m/(2 65) = 20,000,000/(2 65) = 153,846 [bps] error = (153,846/153,600 ? 1) 100 = 0.160 [%] chapter 11 serial interface function 390 user?s manual u14359ej5v1ud (3) baud rate setting example table 11-3. baud rate generator setting data f xx = 50 mhz f xx = 40 mhz f xx = 33 mhz f xx = 10 mhz baud rate (bps) f xclk k err f xclk k err f xclk k err f xclk k err 300 f xx /2 9 163 ? 0.15 f xx /2 10 65 0.16 f xx /2 8 215 ? 0.07 f xx /2 7 130 0.16 600 f xx /2 8 163 ? 0.15 f xx /2 9 65 0.16 f xx /2 7 215 ? 0.07 f xx /2 6 130 0.16 1,200 f xx /2 7 163 ? 0.15 f xx /2 8 65 0.16 f xx /2 6 215 ? 0.07 f xx /2 5 130 0.16 2,400 f xx /2 6 163 ? 0.15 f xx /2 7 65 0.16 f xx /2 5 215 ? 0.07 f xx /2 4 130 0.16 4,800 f xx /2 5 163 ? 0.15 f xx /2 6 65 0.16 f xx /2 4 215 ? 0.07 f xx /2 3 130 0.16 9,600 f xx /2 4 163 ? 0.15 f xx /2 5 65 0.16 f xx /2 3 215 ? 0.07 f xx /2 2 130 0.16 19,200 f xx /2 3 163 ? 0.15 f xx /2 4 80 0.16 f xx /2 2 215 ? 0.07 f xx /2 1 130 0.16 31,250 f xx /2 3 100 0 f xx /2 3 65 0 f xx /2 2 132 0 f xx /2 1 80 0 38,400 f xx /2 2 163 ? 0.15 f xx /2 3 65 0.16 f xx /2 1 215 ? 0.07 f xx /2 0 130 0.16 76,800 f xx /2 2 81 0.47 f xx /2 2 65 0.16 f xx /2 1 107 0.39 f xx /2 0 65 0.16 153,600 f xx /2 1 81 0.47 f xx /2 1 65 0.16 f xx /2 1 54 ? 0.54 f xx /2 0 33 ? 1.36 312,500 f xx /2 1 40 0 f xx /2 1 32 0 f xx /2 1 26 1.54 f xx /2 0 16 0 caution the maximum allowable fr equency of the basic clock (f xclk ) is 25 mhz. remark f xx : internal system clock f xclk : basic clock k: settings of brgn7 to brgn0 bits in brgcn register (n = 0 to 2) err: baud rate error [%] chapter 11 serial interface function user?s manual u14359ej5v1ud 391 (4) allowable baud rate range during reception the degree to which a discrepancy from the transmission destination?s baud rate is allowed during reception is shown below. caution the equations described be low should be used to set the baud rate error during reception so that it always is withi n the allowable error range. figure 11-13. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartn transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0 to 2 as shown in figure 11-13, after the st art bit is detected, the receive data latch timing is determined according to the counter that was set by the brgc n register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. applying this to 11-bit reception is, theoretically, as follows. fl = (brate) ? 1 brate: uartn baud rate (n = 0 to 2) k: brgcn setting value (n = 0 to 2) fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: fl k 2 2 k 21 fl k 2 2 k fl 11 flmin + = ? ? = chapter 11 serial interface function 392 user?s manual u14359ej5v1ud therefore, the maximum baud rate that can be re ceived at the transfer destination is as follows. brate 2 21k k 22 (flmin/11) brmax 1 + = = ? similarly, the maximum allowable transfer rate can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 flmax 11 10 ? = + ? = 11 fl k 20 2 k 21 flmax ? = therefore, the minimum baud rate that can be received at the transfer destination is as follows. brate 2 21k k 20 (flmax/11) brmin 1 ? = = ? the allowable baud rate error of uartn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 11-4. maximum and mini mum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the reception precision depends on the number of bits in one frame, the basic clock frequency, and the division ratio (k). the higher the basic clock frequency and the larger the division ratio (k), the higher the precision. 2. k: brgcn setting value (n = 0 to 2) chapter 11 serial interface function user?s manual u14359ej5v1ud 393 (5) transfer rate durin g continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the basic clock longer than normal. however, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 11-14. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the basic clock frequency by f xclk yields the following equation. flstp = fl + 2/f xclk therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + 2/f xclk 11.2.7 cautions the points to be noted when using uartn are described below (n = 0 to 2). (1) when the supply of clocks to uart n is stopped (for example, idle or software stop mode), operation stops with each register retaining the value it had immediately before the supply of clocks was stopped. the txdn pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. however, operation is not gua ranteed after the supply of clocks is rest arted. therefore, after the supply of clocks is restarted, the circuits should be initialized by setting uartcaen = 0, rxen = 0, and txen = 0. (2) uartn is of two-buffer configuration, consisting of transmit buffers (txbn) and transmit shift registers, and has status flags (txbfn and txsfn bits of the asifn register) that indicate the status of the respective buffers. if the txbfn and txsfn bits are read at the same time during successive transmission, the value changes as follows: 10 11 01. to successively transmit data, therefore, judge the status using only the txbfn bit. chapter 11 serial interface function 394 user?s manual u14359ej5v1ud 11.3 clocked serial interfaces 0 to 2 (csi0 to csi2) 11.3.1 features ? transfer rate: master mode: maximum 3.125 mbps (when internal system clock operates at 50 mhz) slave mode: maximum 5 mbps ? half-duplex communications ? master mode and slave mode can be selected ? transmission data length: 8 bits ? transfer data direction can be switched between msb first and lsb first ? eight clock signals can be selected (7 master clocks and 1 slave clock) ? 3-wire method son: serial data output sin: serial data input sckn: serial clock i/o ? interrupt sources: 1 type ? transmission/reception completion interrupt (intcsin) ? transmission/reception mode or reception-only mode can be specified ? on-chip transmit buffer (sotbn) remark n = 0 to 2 11.3.2 configuration csin is controlled by the clocked serial interface mode regi ster (csimn) (n = 0 to 2). transmit/receive data can be written to or read from the sion register. (1) clocked serial interface mode regi sters 0 to 2 (csim0 to csim2) the csimn register is an 8-bit register for specifying the operation of csin. (2) clocked serial interface clock selection registers 0 to 2 (csic0 to csic2) the csicn register is an 8-bit register fo r controlling the transmit operation of csin. (3) serial i/o shift registers 0 to 2 (sio0 to sio2) the sion register is an 8-bit register for converting between serial data and parallel data. sion is used for both transmission and reception. data is shifted in (reception) or shifted out (transmission) beginning at either the msb side or the lsb side. actual transmit/receive operations are controlled by reading or writing sion. (4) clocked serial interface transmit buffe r registers 0 to 2 (sotb0 to sotb2) the sotbn register is an 8-bit buffer register for storing transmit data. (5) selector the selector selects the serial clock to be used. (6) serial clock controller the serial clock controller controls the supply of serial clocks to the shift register. when an internal clock is used, it also controls the clocks that are output to the sckn pin. chapter 11 serial interface function user?s manual u14359ej5v1ud 395 (7) serial clock counter the serial clock counter counts serial clocks that are output or input during transmit and receive operations and checks that 8-bit data has been transmitted or received. (8) interrupt controller the interrupt controller controls whether or not an interrupt request is generated when the serial clock counter has counted eight serial clocks. figure 11-15. clocked seri al interface block diagram f xx /2 15 f xx /2 14 f xx /2 12 f xx /2 10 f xx /2 8 f xx /2 6 f xx /2 4 sckn sin sckn son intcsin control signal transmit data control serial clock controller clock start/stop control & clock phase control interrupt controller selector transmission control so selection so latch transmit data buffer register n (sotbn) shift register n (sion) remarks 1. n = 0 to 2 2. f xx : internal system clock chapter 11 serial interface function 396 user?s manual u14359ej5v1ud 11.3.3 control registers (1) clocked serial interface mode regi sters 0 to 2 (csim0 to csim2) the csimn register controls the operation of csin (n = 0 to 2). these registers can be read or written in 8-bit or 1-bit units. be sure to set bits 5 and 3 to 1 to 0. if they are set to 1, the operation is not guaranteed. caution to use csin, be sure to set the external pi ns related to the csin function to control mode and set the csicn register. then set the csi caen bit to 1 before setting the other bits. chapter 11 serial interface function user?s manual u14359ej5v1ud 397 <7> <6> 5 <4> 3 2 1 <0> address after reset csim0 csicae0 trmd0 0 dir0 0 0 0 csot0 fffff900h 00h csim1 csicae1 trmd1 0 dir1 0 0 0 csot1 fffff910h 00h csim2 csicae2 trmd2 0 dir2 0 0 0 csot2 fffff920h 00h bit position bit name function 7 csicaen (n = 0 to 2) csi operation permission/prohibition specifies whether csin operation is enabled or disabled (n = 0 to 2). 0: csin operation is disabled (son = low level, sckn = high level) 1: csin operation is enabled cautions 1. if csicaen is set to 0, the csin unit can be reset asynchronously. 2. if csicaen = 0, the csin unit is in a reset state. therefore, to operate csin, csicaen must be set to 1. 3. if the csicaen bit is changed from 1 to 0, all registers of the csin unit are initialized. to set csicaen to 1 again, the registers of the csin unit must be set again. 6 trmdn (n = 0 to 2) transmission/reception mode control specifies the transmission/reception mode. 0: reception-only mode 1: transmission/reception mode if trmdn = 0, reception-only transfers are performed. in addition, the son pin output is fixed at low level. data recepti on is started by reading the sion register. if trmdn = 1, transmission/reception is started by writing data to the sotbn register. caution the trmdn bit can be overwritten only when csotn = 0. 4 dirn (n = 0 to 2) transmit direction mode control specifies the transfer direction mode (msb or lsb). 0: the transfer data?s start bit is msb 1: the transfer data?s start bit is lsb caution the dirn bit can be overwritten only when csotn = 0. 0 csotn (n = 0 to 2) csi status of transmission this is a transfer status display flag. 0: idle status 1: transfer execution status this flag is used to judge whether writing to the shift register (sion) is enabled or not when starting serial data transm ission in transmission/reception mode (trmdn = 1) caution the csotn bit is reset when the csicaen bit is cleared (0). chapter 11 serial interface function 398 user?s manual u14359ej5v1ud (2) clocked serial interface clock selection registers 0 to 2 (csic0 to csic2) the csicn register is an 8-bit register t hat controls the transmit operation of csin. these registers can be read or written in 8-bit units. caution the csic2 to csic0 registers can be over written when csicaen = 0 in the csimn register. (1/2) 7 6 5 4 3 2 1 0 address after reset csic0 0 0 0 ckp0 dap0 cks02 cks01 cks00 fffff901h 00h csic1 0 0 0 ckp1 dap1 cks12 cks11 cks10 fffff911h 00h csic2 0 0 0 ckp2 dap2 cks22 cks21 cks20 fffff921h 00h bit position bit name function clock phase selection bit, data phase selection bit specifies the data transmission/reception timing for sckn. ckpn dapn operation mode 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) 4, 3 ckpn, dapn (n = 0 to 2) chapter 11 serial interface function user?s manual u14359ej5v1ud 399 (2/2) bit position bit name function input clock selection specifies the input clock. cksn2 cksn1 cksn0 input clock mode 0 0 0 f xx /2 15 master mode 0 0 1 f xx /2 14 master mode 0 1 0 f xx /2 12 master mode 0 1 1 f xx /2 10 master mode 1 0 0 f xx /2 8 master mode 1 0 1 f xx /2 6 master mode 1 1 0 f xx /2 4 master mode 1 1 1 external clock (sckn) slave mode 2 to 0 cksn2 to cksn0 (n = 0 to 2) remark f xx : internal system clock (a) baud rate baud rate (bps) cksn2 cksn1 cksn0 50 mhz operation 40 mhz operation 33 mhz operation 25 mhz operation 20 mhz operation 0 0 0 1,526 1,221 1,007 763 610 0 0 1 3,052 2,441 2,014 1,526 1,221 0 1 0 12,207 9,766 8,057 6,104 4,883 0 1 1 48,828 39,063 32,227 24,414 19,531 1 0 0 195,313 156,250 128,906 97,656 78,125 1 0 1 781,250 625,000 515,625 390,625 312,500 1 1 0 3,125,000 2,500,000 2,062,500 1,562,500 1,250,000 chapter 11 serial interface function 400 user?s manual u14359ej5v1ud (3) serial i/o shift registers 0 to 2 (sio0 to sio2) the sion register is an 8-bit shift register that converts parallel data to serial data. if trmdn = 0 in the csimn register, the transfer is started by reading sion. except when a reset is input, the sion register becomes 00h even when the csicaen bit of the csimn register is cleared (0). these registers are read-only in 8-bit units. caution sion can be accessed only when the system is in an idle state (csotn = 0 in the csimn register). 7 6 5 4 3 2 1 0 address after reset sio0 sio07 sio06 sio05 sio04 sio 03 sio02 sio01 sio00 fffff902h 00h sio1 sio17 sio16 sio15 sio14 sio 13 sio12 sio11 sio10 fffff912h 00h sio2 sio27 sio26 sio25 sio24 sio 23 sio22 sio21 sio20 fffff922h 00h bit position bit name function 7 to 0 sion7 to sion0 (n = 0 to 2) serial i/o shifts data in (reception) or shifts dat a out (transmission) beginning at the msb or the lsb side. chapter 11 serial interface function user?s manual u14359ej5v1ud 401 (4) receive-only serial i/o shift registers 0 to 2 (sioe0 to sioe2) the sioen register is an 8-bit shift register that converts parallel data into serial data. a receive operation does not start even if the sioen register is read while the trmd bit of the csimn register is 0. therefore this register is used to read the value of the sion regist er (receive data) without starting a receive operation. except when a reset is input, the sioen register becomes 00h even when the csicaen bit of the csimn register is cleared (0). these registers are read-only in 8-bit units. caution sioen can be accessed only when the system is in an idle state (csotn = 0 in the csimn register). 7 6 5 4 3 2 1 0 address after reset sioe0 sioe07 sioe06 sioe05 sioe04 sioe03 sioe02 sioe01 sioe00 fffff903h 00h sioe1 sioe17 sioe16 sioe15 sioe14 sioe13 sioe12 sioe11 sioe10 fffff913h 00h sioe2 sioe27 sioe26 sioe25 sioe24 sioe23 sioe22 sioe21 sioe20 fffff923h 00h bit position bit name function 7 to 0 sioen7 to sioen0 (n = 0 to 2) serial i/o shifts data in (reception) beginning at the msb or the lsb side. chapter 11 serial interface function 402 user?s manual u14359ej5v1ud (5) clocked serial interface transmit buffe r registers 0 to 2 (sotb0 to sotb2) the sotbn register is an 8-bit buffer register for storing transmit data. if transmission/reception mode is set (trmdn = 1 in the csimn register), a transmit operation is started by writing data to the sotbn register. reset input sets the sotbn register to 00h. these registers can be read or written in 8-bit units. caution sotbn can be accessed only when the system is in an idle state (csotn = 0 in the csimn register). 7 6 5 4 3 2 1 0 address after reset sotb0 sotb07 sotb06 sotb 05 sotb04 sotb03 sotb02 sotb01 sotb00 fffff904h 00h sotb1 sotb17 sotb16 sotb 15 sotb14 sotb13 sotb12 sotb11 sotb10 fffff914h 00h sotb2 sotb27 sotb26 sotb 25 sotb24 sotb23 sotb22 sotb21 sotb20 fffff924h 00h bit position bit name function 7 to 0 sotbn7 to sotbn0 (n = 0 to 2) serial i/o writes transmit data. chapter 11 serial interface function user?s manual u14359ej5v1ud 403 11.3.4 operation (1) transfer mode csin transmits and receives data in three lines: 1 clock line and 2 data lines. in reception-only mode (trmdn = 0 in the csimn register), the transfer is started by reading the sion register (n = 0 to 2). in transmission/reception mode (trmdn = 1 in the csimn r egister), the transfer is started by writing data to the sotbn register. when an 8-bit transfer of csin ends, the csotn bit of the csimn register becomes 0, and transfer stops automatically. also, when the transfer ends, a transmission/reception completion interrupt (intcsin) is generated. cautions 1. when csotn = 1 in the csimn register , the control registers a nd data registers should not be accessed. 2. if transmit data is writte n to the sotbn register and the trmdn bit of the csimn register is changed from 0 to 1, seria l transfer is not performed. (2) serial clock (a) when internal clock is selected as the serial clock if reception or transmission is started, a serial clock is output from the sckn pin, and the data of the sin pin is taken into the sion register sequentially or data is output to the son pin sequentially from the sion register at the timing when the data has been synchronized with the serial clock in accordance with the setting of the ckpn and dapn bits of the csicn register (n = 0 to 2). (b) when external clock is selected as the serial clock if reception or transmission is started, the data of the sin pin is taken into the sion register sequentially or output to the son pin sequentially in synchronization with the serial clock that has been input to the sckn pin following transmission/reception startup in accordance with the setting of the ckpn and dapn bits of the csicn register (n = 0 to 2). if serial clock is input to the sckn pin when neither reception nor transmission is started, a shift operation will not be executed. chapter 11 serial interface function 404 user?s manual u14359ej5v1ud figure 11-16. transfer timing (a) when trmdn = 1, dirn = 0, ckpn = 0, and dapn = 0 10101010 1 0101010 (aah) (55h) (write 55h to sotbn) 55h (transmission data) csotn bit sckn reg-r/w sotbn sion sin son intcsin interrupt abh 56h adh b5h 6ah d5h aah 5ah remark n = 0 to 2 (b) when trmdn = 1, dirn = 0, ckpn = 0, and dapn = 1 10101010 1 0101010 (aah) (55h) (write 55h to sotbn) 55h (transmission data) csotn bit sckn reg-r/w sotbn sion sin son intcsin interrupt abh 56h adh b5h 6ah d5h aah 5ah remark n = 0 to 2 chapter 11 serial interface function user?s manual u14359ej5v1ud 405 figure 11-17. clock timing (a) when ckpn = 0 and dapn = 0 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (b) when ckpn = 1 and dapn = 0 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (c) when ckpn = 0 and dapn = 1 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (d) when ckpn = 1 and dapn = 1 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 remark n = 0 to 2 chapter 11 serial interface function 406 user?s manual u14359ej5v1ud 11.3.5 output pins (1) sckn pin when csin operation is disabled (csicaen = 0) , the sckn pin output state is as follows. ckpn sckn pin output 0 fixed at high level 1 fixed at low level remarks 1. when the ckpn bit is overwritten, the sckn pin output changes. 2. n = 0 to 2 (2) son pin when csin operation is disabled (csicaen = 0), the son pin output state is as follows. trmdn dapn dirn son pin output 0 x x fixed at low level 0 x son latch value (low level) 0 sotbn7 value 1 1 1 sotbn0 value remarks 1. if any of the trmdn, dapn, and dirn bits is overwritten, the son pin output changes. 2. n = 0 to 2 3. x: don?t care chapter 11 serial interface function user?s manual u14359ej5v1ud 407 11.3.6 system configuration example csin performs 8-bit length data transfer using three signal lines: a serial clock (sckn), serial input (sin), and serial output (son). this is effective when connecting peripheral i/o that incorporate a conventional clocked serial interface, or a display controller to the v850e/ma1 (n = 2 to 0). when connecting the v850e/ma1 to several devices, lines for handshake are required. since the first communication bit can be selected as an msb or lsb, communication with various devices can be achieved. figure 11-18. system configuration example of csi sck master cpu slave cpu (3-wire serial i/o 3-wire serial i/o) so si port (interrupt) port si so port port (interrupt) sck 408 user?s manual u14359ej5v1ud chapter 12 a/d converter 12.1 features ? analog input: 8 channels ? 10-bit a/d converter ? on-chip a/d conversion result register (adcr0 to adcr7) 10 bits 8 ? a/d conversion trigger mode a/d trigger mode timer trigger mode external trigger mode ? successive approximation method 12.2 configuration the a/d converter of the v850e/ma1 adopts the successive ap proximation method, and uses a/d converter mode registers 0, 1, 2 (adm0, adm1, adm2 ), and the a/d conversion result regi ster (adcr0 to adcr7) to perform a/d conversion operations. (1) input circuit the input circuit selects the analog input (ani0 to an i7) according to the mode set by the adm0 and adm1 registers and sends the input to the sample & hold circuit. (2) sample & hold circuit the sample & hold circuit samples each of the analog i nput signals sequentially sent from the input circuit, and sends them to the voltage comparator. this circui t also holds the sampled analog input signal during a/d conversion. (3) voltage comparator the voltage comparator compares the analog input signal with the output volt age of the series resistor string voltage tap. (4) series resistor string the series resistor string is used to gen erate voltages to match analog inputs. the series resistor string is connect ed between the reference voltage pin (av ref ) for the a/d converter and the gnd pin (av ss ) for the a/d converter. to make 1,024 equal voltage steps between these 2 pins, it is configured from 1,023 equal resistors and 2 re sistors with 1/2 of t he resistance value. the voltage tap of the series resist or string is selected by a tap sele ctor controlled by the successive approximation register (sar). chapter 12 a/d converter 409 user?s manual u14359ej5v1ud (5) successive approximation register (sar) the sar is a 10-bit register that sets series resistor string voltage tap data, whose values match analog input voltage values, 1 bit at a time starti ng from the most significant bit (msb). if data is set in the sar all the way to the least signifi cant bit (lsb) (a/d conversion completed), the contents of the sar (conversion results) are held in the a/d conversion result register (adcrn). when all the specified a/d conversion operations have been comple ted, an a/d conversion end interrupt (intad) occurs. (6) a/d conversion result register (adcrn) adcrn is a 10-bit register that hold s a/d conversion results. each ti me a/d conversion is completed, the conversion results are loaded from the su ccessive approximation register (sar). reset input sets this register to 0000h. (7) controller the controller selects the analog input, generates the sa mple & hold circuit operation timing, and controls the conversion trigger according to the mode set by the adm0 and adm1 registers. (8) ani0 to ani7 pins these are 8-channel analog input pins for the a/d c onverter. they input the analog signals to be a/d converted. caution make sure that the voltag es input to ani0 to ani7 do not exceed the rated values. if a voltage higher than av dd or lower than av ss (even within the range of the absolute maximum ratings) is input to a channel, the c onversion value of the ch annel is undefined, and the conversion values of the othe r channels may also be affected. (9) av ref pin this is the pin for inputting the reference voltage of the a/d converter. it converts signals input to the anin pin to digital signals based on the voltage applied between av ref and av ss . in the v850e/ma1, the av ref pin functions alternately as the av dd pin. it is therefore impossible to set voltage separately for the av ref pin and the av dd pin. chapter 12 a/d converter 410 user?s manual u14359ej5v1ud figure 12-1. block diag ram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 intm000 intm001 intm010 intm011 intad input circuit adm0 (8) 8 voltage comparator sar (10) adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 10 10 10 90 internal bus tap selector av dd/ av ref r/2 r r/2 series resistor string 70 adm1 (8) 70 av ss 8 adm2 (8) 70 8 edge detection adtrg controller sample & hold circuit f xx /2 remark f xx : internal system clock cautions 1. if there is noise at the analog input pins (ani0 to ani7) or at the reference voltage input pin (av ref ), that noise may generate an illegal conversion result. software processing will be needed to avoid a negative effect on the system from this illegal conversion result. an example of this softwar e processing is shown below. ? take the average result of a number of a/d conversions and use that as the a/d conversion result. ? execute a number of a/d conversions con secutively and use those results, omitting any exceptional results that may have been obtained. ? if an a/d conversion result that is judged to have genera ted a system malfunction is obtained, be sure to recheck the system malfunction before performing malfunction processing. 2. do not apply a voltage outside the av ss to av ref range to the pins that are used as a/d converter input pins. chapter 12 a/d converter 411 user?s manual u14359ej5v1ud 12.3 control registers (1) a/d converter mode register 0 (adm0) the adm0 register is an 8-bit regist er that selects the analog input pi n, specifies the operation mode, and executes conversion operations. this register can be read/written in 8-bit or 1-bit units. however, when data is written to the adm0 register during an a/d conversion operation, the conversion oper ation is initialized and conversion is executed from the beginning. bit 6 cannot be written to and writing executed is ignored. cautions 1. when the adce bit is 1 in the timer trigger mode and external trigger mode, the trigger signal standby state is set. to clear the adce bit, write ?0? or reset. in the a/d trigger mode, the conversion trigge r is set by writing 1 to the adce bit. after the operation, when the mode is changed to the timer trigger mode or external trigger mode without clearing the adce bit, the trigge r input standby state is set immediately after the register value is changed. 2. it takes 7 to 9 clocks until the adcs bit is set to 1 from when the adce bit was set to 1 in the a/d trigger mode. chapter 12 a/d converter 412 user?s manual u14359ej5v1ud address fffff200h <7> adce adm0 <6> adcs 5 bs 4 ms 3 0 2 anis2 1 anis1 0 anis0 after reset 00h bit position bit name function 7 adce convert enable enables or disables a/d conversion operation. 0: disabled 1: enabled 6 adcs converter status indicates the status of a/d converter. this bit is read only. 0: stopped 1: operating 5 bs buffer select specifies buffer mode in the select mode. 0: 1-buffer mode 1: 4-buffer mode 4 ms mode select specifies operation mode of a/d converter. 0: scan mode 1: select mode analog input select specifies the analog input pin to be a/d converted. select mode scan mode anis2 anis1 anis0 a/d trigger mode timer trigger mode, external trigger mode a/d trigger mode timer trigger mode notes 1, 2 , external trigger mode note 2 0 0 0 ani0 ani0 ani0 1 0 0 1 ani1 ani1 ani0, ani1 2 0 1 0 ani2 ani2 ani0 to ani2 3 0 1 1 ani3 ani3 ani0 to ani3 4 1 0 0 ani4 setting prohibited ani0 to ani4 4 + ani4 1 0 1 ani5 setting prohibited ani0 to ani5 4 + ani4, ani5 1 1 0 ani6 setting prohibited ani0 to ani6 4 + ani4 to ani6 1 1 1 ani7 setting prohibited ani0 to ani7 4 + ani4 to ani7 2 to 0 anis2 to anis0 notes 1. in the timer trigger mode (4-trigger mode) in the scan mode, because the scanning sequence of the ani0 to ani3 pins is specified by the s equence in which the match signals are generated from the compare register, the num ber of trigger inputs should be specified instead of specifying a certain analog input pin. 2. if anis2 = 1, conversion is executed up to anin, starting from ani3, after the trigger is counted four times (n = 4 to 7). chapter 12 a/d converter 413 user?s manual u14359ej5v1ud (2) a/d converter mode register 1 (adm1) the adm1 register is an 8-bit register that spec ifies the conversion operation time and trigger mode. this register can be read/written in 8-bit units. howe ver, when data is written to the adm1 register during an a/d conversion operation, the conv ersion operation is initialized and conversion is executed from the beginning. cautions 1. it takes the followin g number of clocks from trigger input to completion of a/d conversion, in addition to th e clocks specified using the fr 2 to fr0 bits. (refer to 12.8.6 supplementary informati on on a/d conversion time.) in a/d trigger mode: 11 to 13 clocks (9 to 11 cl ocks + 2 clocks) in timer trigger mode or external trigger mode: 7 to 9 cl ocks (5 to 7 cl ocks + 2 clocks) 2. in the timer trigger mode or external tri gger mode, be sure to input the trigger at an interval longer than the number of clocks spec ified using the fr2 to fr0 bits. (refer to 12.8.2 timer trigger/external trigger interval.) chapter 12 a/d converter 414 user?s manual u14359ej5v1ud address fffff201h 7 0 adm1 6 trg2 5 trg1 4 trg0 3 0 2 fr2 1 fr1 0 fr0 after reset 07h bit position bit name function trigger mode specifies the trigger mode. trg2 trg1 trg0 trigger mode 0 0 0/1 a/d trigger mode 0 1 0 timer trigger mode (1-trigger mode) 0 1 1 timer trigger mode (4-trigger mode) 1 1 1 external trigger mode other than above setting prohibited 6 to 4 trg2 to trg0 remark the valid edge of the external input signal in the external trigger mode is specified by bits 7 and 6 (es1231, es 1230) of the external interrupt mode register (intm3). for details, refer to 7.3.9 (1) external interrupt mode registers 1 to 4 (intm1 to intm4) . frequency specifies the conversion operation time. these bits control the conversion time so that it is the same value irrespective of the oscillation frequency. conversion operation time note fr2 fr1 fr0 number of conversion clocks f xx = 50 mhz f xx = 40 mhz f xx = 33 mhz 0 0 0 96 setting prohibited setting prohibited setting prohibited 0 0 1 144 setting prohibited setting prohibited setting prohibited 0 1 0 192 setting prohibited setting prohibited 5.82 s 0 1 1 240 4.80 s 6.00 s 7.27 s 1 0 0 336 6.72 s 8.40 s 10.18 s 1 0 1 384 7.68 s 9.60 s setting prohibited 1 1 0 480 9.60 s setting prohibited setting prohibited 1 1 1 672 setting prohibited setting prohibited setting prohibited 2 to 0 fr2 to fr0 note set the conversion operation time in the range of 5 to 10 s. remark f xx = internal system clock chapter 12 a/d converter 415 user?s manual u14359ej5v1ud (3) a/d converter mode register 2 (adm2) the adm2 register is an 8-bit register that cont rols the reset and clock of the a/d converter. this register can be read/written in 8-bit or 1-bit units. caution because adcae = 0 after reset release, the a/d converter enters th e reset state. when operating the a/d converter, be sure to writ e to the adm0 and adm1 registers after setting the adcae bit of the adm2 register to 1 (it is impossible to write to the adm0 and adm1 registers when adcae = 0). moreover, when the adcae bit is set to 0, all registers related to the a/d converter are initialized. address fffff202h 7 0 adm2 6 0 5 0 4 0 3 0 2 0 1 0 <0> adcae after reset 00h bit position bit name function 0 adcae clock action enable controls the a/d converter operation. 0: clock supply to the a/d c onverter is stopped, the a/d converter is in the reset state 1: the clock is supplied to the a/d co nverter, a/d converter operation is enabled chapter 12 a/d converter 416 user?s manual u14359ej5v1ud (4) a/d conversion result registers (adcr0 to adcr7, adcr0h to adcr7h) the adcrn register is a 10-bit regist er holding the a/d conversion results. there are eight 10-bit registers. these registers are read-only in 16-bit or 8-bit units. during 16-bit access, the adcrn register is specified, and during higher 8-bit access, the adcrnh register is specified (n = 0 to 7). when reading the 10-bit data of the a/d conversion resu lts from the adcrn register during 16-bit access, only the lower 10 bits are valid and the higher 6 bits are always read as 0. 15 0 14 0 13 0 12 0 11 0 10 0 9 ad n9 8 ad n8 7 ad n7 6 ad n6 5 ad n5 4 ad n4 3 ad n3 2 ad n2 1 ad n1 0 ad n0 adcrn address fffff210h to fffff21eh after reset 0000h 7 ad n9 6 ad n8 5 ad n7 4 ad n6 3 ad n5 2 ad n4 1 ad n3 0 ad n2 adcrnh address fffff220h to fffff227h after reset 00h remark n = 0 to 7 the correspondence between each analog input pin and the adcrn register (except the 4-buffer mode) is shown below. analog input pin adcrn register ani0 adcr0, adcr0h ani1 adcr1, adcr1h ani2 adcr2, adcr2h ani3 adcr3, adcr3h ani4 adcr4, adcr4h ani5 adcr5, adcr5h ani6 adcr6, adcr6h ani7 adcr7, adcr7h chapter 12 a/d converter 417 user?s manual u14359ej5v1ud the relationship between the analog voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (of the a/d conversion re sult register n (adcrn)) is as follows: 0.5) 1,024 av v ( int adcr ref in + = or, 1,024 av 0.5) (adcr v 1,024 av 0.5) (adcr ref in ref + < ? int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref : av ref pin voltage adcr: value of a/d conversion result register n (adcrn) figure 12-2 shows the relationship between the ana log input voltage and the a/d conversion results. figure 12-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ref 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion results (adcrn) remark n = 0 to 7 chapter 12 a/d converter 418 user?s manual u14359ej5v1ud 12.4 a/d converter operation 12.4.1 basic operation of a/d converter a/d conversion is executed by the following procedure. (1) the adcae bit of the adm2 register is set (1). (2) the selection of the analog input and specification of the operation mode, trigger mode, etc. should be specified using the adm0 and adm1 registers note 1 . when the adce bit of the adm0 register is set (1), a/ d conversion starts in the a/d trigger mode. in the timer trigger mode and external trig ger mode, the trigger standby state note 2 is set. (3) the voltage generated from the vo ltage tap of the series resistor st ring and analog input are compared by the comparator. (4) when the comparison of the 10 bits ends, the conver sion results are stored in the adcrn register. when a/d conversion has been performed the specified number of times, the a/ d conversion end interrupt (intad) is generated (n = 0 to 7). notes 1. when the adm0 to adm2 registers are changed during the a/d conversion operation, the a/d conversion operation before the change is stopped and the conver sion results are not stored in the adcrn register. 2. during the timer trigger mode and external trigger mode, if the adce bit of the adm0 register is set to 1, the mode changes to the trigger standby state. the a/d conversi on operation is started by the trigger signal, and the tr igger standby state is returned when the a/d conversion operation ends. chapter 12 a/d converter 419 user?s manual u14359ej5v1ud 12.4.2 operation mode and trigger mode various conversion operations can be specified for the a/ d converter by specifying the operation mode and trigger mode. the operation mode and trigger mode are set by the adm0 and adm1 registers. the following shows the relationship betwe en the operation mode and trigger mode. setting value trigger mode operation mode adm0 adm1 analog input 1 buffer xx010xxxb 000x0xxxb select 4 buffers xx110xxxb 000x0xxxb a/d trigger scan xxx00xxxb 000x0xxxb ani0 to ani7 1 buffer xx010xxxb 00100xxxb select 4 buffers xx110xxxb 00100xxxb ani0 to ani3 1 trigger scan xxx00xxxb 00100xxxb ani0 to ani7 note 1 buffer xx010xxxb 00110xxxb select 4 buffers xx110xxxb 00110xxxb ani0 to ani3 timer trigger 4 trigger scan xxx00xxxb 00110xxxb ani0 to ani7 note 1 buffer xx010xxxb 01100xxxb select 4 buffers xx110xxxb 01100xxxb ani0 to ani3 external trigger scan xxx00xxxb 01100xxxb ani0 to ani7 note note the ani4 to ani7 pins are converted serially. (1) trigger mode there are three types of trigger modes that serve as the start timing of a/d conversion processing: a/d trigger mode, timer trigger mode, and external trigger mode . the ani0 to ani3 pins are able to specify all of these modes, but the ani4 to ani7 pins can only s pecify the a/d trigger mode. the timer trigger mode consists of the 1-trigger mode and 4-trigger mode as the sub-trigger modes. these trigger modes are set by the adm1 register. (a) a/d trigger mode this mode starts the conversion timing of the analog input set to the ani0 to ani7 pins, and by setting the adce bit of the adm0 register to 1, starts a/d conversion. the an i4 to ani7 pins are always set in this mode. (b) timer trigger mode specifies the conversion timing of the analog input set for the ani0 to ani3 pins using the values set to the timer c compare register. this mode can only be s pecified by pins ani0 to ani3 (in select mode). this register creates the analog input conversion timing by generating the match interrupts (intm000, intm001, intm010, intm011) of the four capture/ compare registers (ccc00, ccc01, ccc10, ccc11) connected to 16-bit timer c (tmc0, tmc1). mo reover, because the match interrupts (intm000, intm001, intm010, intm011) are also used as exte rnal pin interrupts (intp000, intp001, intp010, intp011), the analog input conversion timing is generat ed even when external pin interrupts are input. there are two sub-trigger modes: 1- trigger mode and 4-trigger mode. chapter 12 a/d converter 420 user?s manual u14359ej5v1ud ? 1-trigger mode a mode that uses one match interrupt from ti mer c as the a/d conversion start timing. ? 4-trigger mode a mode that uses four match interrupts from timer c as the a/d conversion start timing. (c) external trigger mode a mode that specifies the conversion timing of the analog input to the ani0 to ani3 pins using the adtrg pin. this mode can be specifi ed only with the ani0 to ani3 pins. (2) operation mode there are two operation modes that set the ani0 to ani7 pins: select mode and scan mode. the select mode has sub-modes that consist of 1-buffer mode an d 4-buffer mode. these modes are set by the adm0 register. (a) select mode in this mode, one analog input specified by the adm0 register is a/d converted. the conversion results are stored in the adcrn register corresponding to the analog input (anin). for this mode, the 1-buffer mode and 4-buffer mode are provided for storing the a/d conversion results (n = 0 to 7). ? 1-buffer mode in this mode, one analog input specified by the adm0 register is a/d conver ted. the conversion results are stored in the adcrn register correspon ding to the analog input (anin). the anin and adcrn register correspond one to one, and an a/ d conversion end interrupt (intad) is generated each time one a/d conversion ends. chapter 12 a/d converter 421 user?s manual u14359ej5v1ud figure 12-3. select mode operat ion timing: 1-buffer mode (ani1) ani1 (input) a/d conversion data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) data 6 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) adcr1 register intad interrupt conversion start (adm0 register setting) adce bit set adce bit set adce bit set adce bit set conversion start (adm0 register setting) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adcrn register analog input chapter 12 a/d converter 422 user?s manual u14359ej5v1ud ? 4-buffer mode in this mode, one analog input is a/d converted f our times and the results ar e stored in the adcr0 to adcr3 registers. the a/d conversion end interr upt (intad) is generated when the four a/d conversions end. figure 12-4. select mode operat ion timing: 4-buffer mode (ani6) ani6 (input) a/d conversion data 1 (ani6) data 2 (ani6) data 3 (ani6) data 4 (ani6) data 5 (ani6) data 6 (ani6) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani6) adcr0 data 2 (ani6) adcr1 data 3 (ani6) adcr2 data 4 (ani6) adcr3 data 5 (ani6) adcr0 adcrn register intad interrupt conversion start (adm0 register setting) conversion start (adm0 register setting) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adcrn register analog input ( 4) chapter 12 a/d converter 423 user?s manual u14359ej5v1ud (b) scan mode in this mode, the analog inputs specified by the ad m0 register are selected sequentially from the ani0 pin, and a/d conversion is execut ed. the a/d conversion results ar e stored in the adcrn register corresponding to the analog input (n = 0 to 7). w hen the conversion of the spec ified analog input ends, the a/d conversion end interr upt (intad) is generated. figure 12-5. scan mode operation ti ming: 4-channel scan (ani0 to ani3) ani3 (input) ani0 (input) ani1 (input) ani2 (input) a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani0) adcr0 data 2 (ani1) adcr1 data 3 (ani2) adcr2 data 4 (ani3) adcr3 data 5 (ani0) adcr0 adcrn register intad interrupt conversion start (adm0 register setting) conversion start (adm0 register setting) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adcrn register analog input chapter 12 a/d converter 424 user?s manual u14359ej5v1ud 12.5 operation in a/d trigger mode when the adce bit of the adm0 register is set to 1, a/d conversion is started. 12.5.1 select mode operation in this mode, the analog input specified by the adm0 regi ster is a/d converted. the conversion results are stored in the adcrn register corresponding to the analog input. in the select mode, the 1-buffer mode and 4-buffer mode are supported according to the storing method of the a/d conversion results (n = 0 to 7). (1) 1-buffer mode (a/d trigger select: 1 buffer) in this mode, one analog input is a/d converted once . the conversion results are stored in one adcrn register. the analog input and adcrn register correspond one to one. each time an a/d conversion is executed, an a/d conversion end interrupt (i ntad) is generated and a/d conversion ends. analog input a/d conversion result register anin adcrn if 1 is written in the adce bit of the adm0 register, a/d conversion can be restarted. this mode is most appropriate for applications in which the results of each first-time a/d conversion are read. figure 12-6. example of 1-buffer mode op eration (a/d trigger select: 1 buffer) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adm0 (1) the adce bit of adm0 is set to 1 (enable) (2) ani2 is a/d converted (3) the conversion result is stored in adcr2 (4) the intad interrupt is generated chapter 12 a/d converter 425 user?s manual u14359ej5v1ud (2) 4-buffer mode (a/d trigger select: 4 buffers) in this mode, one analog input is a/d converted four times and the results are stored in the adcr0 to adcr3 registers. when the 4th a/d conv ersion ends, an a/d conversion end interrupt (intad) is generated and the a/d conversion is stopped. analog input a/d conversion result register anin adcr0 anin adcr1 anin adcr2 anin adcr3 if 1 is written in the adce bit of the adm0 register, a/d conversion can be restarted. this mode is suitable for applications in which the av erage of the a/d conversi on results is calculated. figure 12-7. example of 4-buffer mode op eration (a/d trigger select: 4 buffers) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adm0 ( 4) (1) the adce bit of adm0 is set to 1 (enable) (6) ani4 is a/d converted (2) ani4 is a/d converted (7) the conversion result is stored in adcr2 (3) the conversion result is stored in adcr0 (8) ani4 is a/d converted (4) ani4 is a/d converted (9) the conversion result is stored in adcr3 (5) the conversion result is stored in adcr1 (10) the intad interrupt is generated chapter 12 a/d converter 426 user?s manual u14359ej5v1ud 12.5.2 scan mode operations in this mode, the analog inputs specified by the adm0 re gister are selected sequentially from the ani0 pin, and a/d conversion is executed. the a/d conversion results are stored in the adcrn register corresponding to the analog input (n = 0 to 7). when conversion of all the specified analog input ends , the a/d conversion end interr upt (intad) is generated, and a/d conversion is stopped. analog input a/d conversion result register ani0 adcr0 anin note adcrn note set by the ani0 to ani2 bits of the adm0 register. if 1 is written in the adce bit of the adm0 register, a/d conversion can be restarted. this mode is most appropriate for applications in whic h multiple analog inputs are constantly monitored. figure 12-8. example of scan m ode operation (a/d trigger scan) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adm0 (1) the adce bit of adm0 is set to 1 (enable) (8) ani3 is a/d converted (2) ani0 is a/d converted (9) the conversion result is stored in adcr3 (3) the conversion result is stored in adcr0 (10) ani4 is a/d converted (4) ani1 is a/d converted (11) the conversion result is stored in adcr4 (5) the conversion result is stored in adcr1 (12) ani5 is a/d converted (6) ani2 is a/d converted (13) the conversion result is stored in adcr5 (7) the conversion result is stored in adcr2 (14) the intad interrupt is generated . . . . . . chapter 12 a/d converter 427 user?s manual u14359ej5v1ud 12.6 operation in timer trigger mode conversion timings for up to four-channel analog inputs (ani0 to ani3) can be set for the a/d converter using the interrupt signal output from the tmc compare register. two 16-bit timers (tmc0, tmc1) and four capture/co mpare registers (ccc00, ccc0 1, ccc10, cc11) are used for the timer to specify the analog conversion trigger. the following two modes are provided according to the value set in the tmcc01 or tmcc11 register. (1) 1-shot mode to use the 1-shot mode, set the ostn bit of the tm ccn1 register (overflow stop mode) to 1 (n = 0, 1). when tmc overflows, 0000h is held, and counter operation stops. thereafter, tmcn does not output the match interrupt signal (a/d conversion trigger) of the compare register, and the a/ d converter enters the a/d conversion standby state. the tmcn count operation restarts when the tmccen bit of the tmccn0 register is set to 1. the 1-shot mode is used when the a/d conv ersion cycle is longer than the tmc cycle. (n = 0, 1). (2) loop mode to use the loop mode, set the ost bit (free-running mode) of the tmccn1 register to 0 (n = 0, 1). when tmcn overflows, it starts counting from 0000h a gain, and the match interrupt signal (a/d conversion trigger) of the compare register is repeatedly output. a/d conversion is also repeated. chapter 12 a/d converter 428 user?s manual u14359ej5v1ud 12.6.1 select mode operation in this mode, an analog input (ani0 to ani3) specified by the adm0 register is a/d c onverted. the conversion results are stored in the adcrn register. in the sele ct mode, the 1-buffer mode and 4-buffer mode are provided according to the storing method of the a/d conversion results (n = 0 to 3). (1) 1-buffer mode operation (tim er trigger select: 1 buffer) in this mode, one analog input is a/d converted once and the conversion results are stored in one adcrn register. there are two modes in the 1-buffer mode: 1-trigger mo de and 4-trigger mode, according to the number of triggers. (a) 1-trigger mode (timer trigge r select: 1 buffer, 1 trigger) in this mode, one analog input is a/d converted once using the trigge r of the match interrupt signal (intm000) and the results are stor ed in one adcrn register. an a/d conversion end interrupt (intad) is generated for each a/d conversion and a/ d conversion is stopped (n = 0 to 3). trigger analog input a/d conversion result register intm000 interrupt anin adcrn in 1-shot mode, a/d conversion stops after one conver sion. to restart a/d conversion, set the tmcce0 bit of the tmcc00 register to 1. when set to the loop mode, unless the adce bit of t he adm0 register is set to 0, a/d conversion is repeated each time a match interrupt is generated. figure 12-9. example of 1-trigger mode operat ion (timer trigger sel ect: 1 buffer 1 trigger) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 (1) the adce bit of adm0 is set to 1 (enable) (2) the ccc00 compare is generated (3) ani1 is a/d converted (4) the conversion result is stored in adcr1 (5) the intad interrupt is generated chapter 12 a/d converter 429 user?s manual u14359ej5v1ud (b) 4-trigger mode (timer trigge r select: 1 buffer, 4 triggers) in this mode, one analog input is a/d converted using four match interrupt signals (intm000, intm001, intm010, intm011) as triggers and the results are st ored in one adcrn register. the a/d conversion end interrupt (intad) is generated wi th each a/d conversion, and the adcs bit of the adm0 register is reset (0). the results of one a/d conversion are he ld in the adcrn register until the next a/d conversion ends. perform transmission of the conversion results to the memory and other operations using the intad interrupt after each a/d conversion ends (n = 0 to 3). trigger analog input a/d conversion result register intm000 interrupt anin adcrn intm001 interrupt anin adcrn intm010 interrupt anin adcrn intm011 interrupt anin adcrn in one-shot mode, a/d conversion stops after four conversions. to restart a/d conversion, set the tmccen bit of the tmccn0 register to 1 to restart t he tmcn. when the first match interrupt after tmcn is restarted is generated, the adcs bit is set (1) and a/d conversion is started (n = 0, 1). when set to the loop mode, unless the adce bit of t he adm0 register is set to 0, a/d conversion is repeated each time a match interrupt is generated. the match interrupts (intm000, in tm001, intm010, intm011) can be generated in any order. also, even in cases where the same trigger is input continuously, it is received as a trigger. figure 12-10. example of 4-trigger mode operat ion (timer trigger sel ect: 1 buffer 4 triggers) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 intm001 intm010 intm011 no particular order ( 4) ( 4) (1) the adce bit of adm0 is set to 1 (enable) (10) the ccc11 compare is generated (random) (2) the ccc10 compare is generated (r andom) (11) ani2 is a/d converted (3) ani2 is a/d converted (12) the conversion result is stored in adcr2 (4) the conversion result is stored in adcr2 (13) the intad interrupt is generated (5) the intad interrupt is generated (14) the ccc00 compare is generated (random) (6) the ccc01 compare is generated (r andom) (15) ani2 is a/d converted (7) ani2 is a/d converted (16) the conversion result is stored in adcr2 (8) the conversion result is stored in adcr2 (17) the intad interrupt is generated (9) the intad interrupt is generated chapter 12 a/d converter 430 user?s manual u14359ej5v1ud (2) 4-buffer mode operation (tim er trigger select: 4 buffers) in this mode, a/d conversion of one analog input is executed four times, and the results are stored in the adcr0 to adcr3 registers. there are two 4-buffer modes: 1-trigger mode and 4-trigger mode, according to the number of triggers. this mode is suitable for applications in which the av erage of the a/d conversi on results is calculated. (a) 1-trigger mode in this mode, one analog input is a/d converted four times using the ma tch interrupt signal (intm000) as a trigger, and the results are stored in adcr0 to ad cr3 registers. the a/d conversion end interrupt (intad) is generated when the four a/d conv ersions end and a/d conversion is stopped. trigger analog input a/d conversion result register intm000 interrupt anin adcr0 intm000 interrupt anin adcr1 intm000 interrupt anin adcr2 intm000 interrupt anin adcr3 if the one-shot mode is set and the tmcce0 bit of t he tmcc00 register is set to 1, and if the match interrupt occurs less than four times, the intad in terrupt does not occur and the standby state is set. figure 12-11. example of 1-trigger mode operati on (timer trigger selec t: 4 buffers 1 trigger) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 ( 4) ( 4) (1) the adce bit of adm0 is set to 1 ( enable) (8) the ccc00 compare is generated (2) the ccc00 compare is generated (9) ani2 is a/d converted (3) ani2 is a/d converted (10) the conversion result is stored in adcr2 (4) the conversion result is stored in a dcr0 (11) the ccc00 compare is generated (5) the ccc00 compare is generated (12) ani2 is a/d converted (6) ani2 is a/d converted (13) the conversion result is stored in adcr3 (7) the conversion result is stored in adcr1 (14) the intad interrupt is generated chapter 12 a/d converter 431 user?s manual u14359ej5v1ud (b) 4-trigger mode in this mode, one analog input is a/d converted using four match interrupt signals (intm000, intm001, intm010, intm011) as triggers and the results are stored in four adcrn register s. the a/d conversion end interrupt (intad) is generated when the a/d c onversions end, the adcs bit is reset (0), and a/d conversion is stopped. trigger analog input a/d conversion result register intm000 interrupt anin adcr0 intm001 interrupt anin adcr1 intm010 interrupt anin adcr2 intm011 interrupt anin adcr3 in 1-shot mode, a/d conversion stops after four co nversions. to restart the a/d conversion, set the tmccen bit of the tmccn0 register to 1 to restart tm cn. when the first match interrupt after tmcn is restarted is generated, the adcs bit is set (1) and a/d conversion is started (n = 0, 1). when set to the loop mode, unless the adce bit of t he adm0 register is set to 0, a/d conversion is repeated each time a match interrupt is generated. the match interrupts (intm000, intm001, intm010, intm011) can be generated in any order, and the conversion results are stored in t he adcrn register corresponding to the input trigger. also, even in cases where the same trigger is input continuously, it is received as a trigger. figure 12-12. example of 4-trigger mode operati on (timer trigger selec t: 4 buffers 4 triggers) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 intm001 intm010 intm011 no particular order no particular order ( 4) (1) the adce bit of adm0 is set to 1 (enable) (8) the ccc10 compare is generated (random) (2) the ccc01 compare is generated (random) (9) ani2 is a/d converted (3) ani2 is a/d converted (10) the conversion result is stored in adcr2 (4) the conversion result is stored in adcr1 (11) the ccc00 compare is generated (random) (5) the ccc11 compare is generated (r andom) (12) ani2 is a/d converted (6) ani2 is a/d converted (13) the conversion result is stored in adcr0 (7) the conversion result is stored in adcr3 (14) the intad interrupt is generated chapter 12 a/d converter 432 user?s manual u14359ej5v1ud 12.6.2 scan mode operation in this mode, the analog inputs specifi ed by the adm0 register are selected sequentially from the ani0 pin and are a/d converted the specif ied number of times using the match interrupt signal as a trigger. in the conversion operation, first t he analog input lower channels (ani0 to ani3) are a/d converted the specified number of times. if the lower channels (ani0 to ani3) of t he analog input are set by the adm0 register so that they are scanned, and when the set number of a/d conversions ends, the a/d c onversion end interrupt (intad) is generated and a/d conv ersion is stopped. when the higher channels (ani4 to an i7) of the analog input are set by the adm0 register so that they are scanned, after the conversion of the lo wer channel is ended, the mode is shi fted to the a/d trigger mode, and the remaining a/d conversions are executed. the conversion results are stored in t he adcrn register corresponding to the analog input. when conversion of all the specified analog inputs has ended, th e a/d conversion end interrupt (intad) is generated and a/d conversion is stopped (n = 0 to 7). there are two scan modes: 1-trigger mode and 4-tr igger mode, according to the number of triggers. this mode is most appropriate for applications in whic h multiple analog inputs are constantly monitored. (1) 1-trigger mode (timer trigger scan: 1 trigger) in this mode, analog inputs are a/d converted the specified number of time s using the match interrupt signal (intm000) as a trigger. the analog input a nd adcrn register correspond one to one. when all the specified a/d conversi ons have ended, the a/d conversion end interrupt (intad) is generated and a/d conversion is stopped. trigger analog input a/d conversion result register intm000 interrupt ani0 adcr0 intm000 interrupt ani1 adcr1 intm000 interrupt ani2 adcr2 intm000 interrupt ani3 adcr3 ani4 adcr4 ani5 adcr5 ani6 adcr6 (a/d trigger mode) ani7 adcr7 when the match interrupt is generated after all the s pecified a/d conversions have ended, a/d conversion is restarted. in 1-shot mode, and when less than a specified numb er of match interrupts are generated, the intad interrupt is not generated and the standby state is set. chapter 12 a/d converter 433 user?s manual u14359ej5v1ud figure 12-13. example of 1-trigger mode op eration (timer trigger scan: 1 trigger) (a) setting when scanning ani0 to ani3 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 (1) the adce bit of adm0 is set to 1 ( enable) (8) the ccc00 compare is generated (2) the ccc00 compare is generated (9) ani2 is a/d converted (3) ani0 is a/d converted (10) the conversion result is stored in adcr2 (4) the conversion result is stored in a dcr0 (11) the ccc00 compare is generated (5) the ccc00 compare is generated (12) ani3 is a/d converted (6) ani1 is a/d converted (13) the conversion result is stored in adcr3 (7) the conversion result is stored in adcr1 (14) the intad interrupt is generated caution intm000 cannot be used as a trigger for the analog inputs enclosed in the broken lines. when a setting is made to scan ani0 to ani7, ani4 to ani7 are converted in a/d trigger mode (see (b) below). (b) setting when scanning ani0 to ani7 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 (1) to (13) same as (a) (18) ani6 is a/d converted (14) ani4 is a/d converted (19) the conversion result is stored in adcr6 (15) the conversion result is stored in adcr4 (20) ani7 is a/d converted (16) ani5 is a/d converted (21) the conversion result is stored in adcr7 (17) the conversion result is stored in adcr5 (22) the intad interrupt is generated chapter 12 a/d converter 434 user?s manual u14359ej5v1ud (2) 4-trigger mode in this mode, analog inputs are a/d converted for the number of times specified using the match interrupt signal (intm000, intm001, intm010, intm011) as a trigger. the analog input and adcrn register correspond one to one. when all the specified a/d conversi ons have ended, the a/d conversion end interrupt (intad) is generated and a/d conversion is stopped. trigger analog input a/d conversion result register intm000 interrupt ani0 adcr0 intm001 interrupt ani1 adcr1 intm010 interrupt ani2 adcr2 intm011 interrupt ani3 adcr3 ani4 adcr4 ani5 adcr5 ani6 adcr6 (a/d trigger mode) ani7 adcr7 to restart a/d conversion in 1-shot mode, restart tm cn. if set to the loop mode and the adce bit of the adm0 register is 1, a/d conversion is restarted w hen a match interrupt is generated after conversion has ended. the match interrupt can be generated in any order. ho wever, because the trigger signal and the analog input correspond one to one, the scanning sequence is determ ined according to the order in which the match signals of the compare register are generated. chapter 12 a/d converter 435 user?s manual u14359ej5v1ud figure 12-14. example of 4-trigger mode op eration (timer trigger scan: 4 triggers) (a) setting when scanning ani0 to ani3 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 random intm001 intm010 intm011 (1) the adce bit of adm0 is set to 1 (enable) (8) the ccc00 compare is generated (random) (2) the ccc01 compare is generated (random) (9) ani0 is a/d converted (3) ani1 is a/d converted (10) the conversion result is stored in adcr0 (4) the conversion result is stored in adcr1 (11) the ccc10 compare is generated (random) (5) the ccc11 compare is generated (r andom) (12) ani2 is a/d converted (6) ani3 is a/d converted (13) the conversion result is stored in adcr2 (7) the conversion result is stored in adcr3 (14) the intad interrupt is generated caution intm0nn cannot be used as a trigger for the analog inputs enclosed in the broken lines tm0nn (n = 0, 1). when a setting is ma de to scan ani0 to ani7, ani4 to ani7 are converted in a/d trigger mode (see (b) below). (b) setting when scanning ani0 to ani7 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 intm001 intm010 intm011 random (1) to (13) same as (a) (18) ani6 is a/d converted (14) ani4 is a/d converted (19) the conversion result is stored in adcr6 (15) the conversion result is stored in adcr4 (20) ani7 is a/d converted (16) ani5 is a/d converted (21) the conversion result is stored in adcr7 (17) the conversion result is stored in adcr5 (22) the intad interrupt is generated chapter 12 a/d converter 436 user?s manual u14359ej5v1ud 12.7 operation in external trigger mode in the external trigger mode, the analog inputs (ani0 to ani3) are a/d converted by the adtrg pin input timing. the adtrg pin has an alternate function as the p37 and intp 123 pins. to set the external trigger mode, set the pmc37 bit of the pmc3 register to 1 and bits tr g2 to trg0 of the adm1 register to 110. for the valid edge of the external input signal during the ex ternal trigger mode, the rising edge, falling edge, or both rising and falling edges can be specified using bits es1 231 and es1230 of the intm3 register. for details, see 7.3.9 (1) external interrupt mode re gisters 1 to 4 (intm1 to intm4) . 12.7.1 select mode operations (external trigger select) in this mode, one analog input (ani0 to ani3) specified by the adm0 register is a/d converted. the conversion results are stored in the adcrn register corresponding to the analog input. there are two select modes: 1-buffer mode and 4-buffer mode, according to the storing me thod of the a/d conversion results (n = 0 to 3). (1) 1-buffer mode (externa l trigger select: 1-buffer) in this mode, one analog input is a/d converted using the adtrg signal as a trigger. the conversion results are stored in one adcrn register. the analog input and the a/d conversi on results register correspond one to one. the a/d conversion end in terrupt (intad) is generated for each a/d conversion, and a/d conversion is stopped. trigger analog input a/d conversion result register adtrg signal anin adcrn while the adce bit of the adm0 regist er is 1, a/d conversion is repeated every time a trigger is input from the adtrg pin. this mode is most appropriate for applications in wh ich the results are read after each a/d conversion. figure 12-15. example of 1-buffer mode oper ation (external trigger select: 1 buffer) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adtrg (1) the adce bit of adm0 is set to 1 (enable) (2) the external trigger is generated (3) ani2 is a/d converted (4) the conversion result is stored in adcr2 (5) the intad interrupt is generated chapter 12 a/d converter 437 user?s manual u14359ej5v1ud (2) 4-buffer mode (externa l trigger select: 4 buffers) in this mode, one analog input is a/ d converted four times using the ad trg signal as a trigger and the results are stored in the adcr0 to adcr3 registers. the a/d conversion end interr upt (intad) is generated and a/d conversion is stopped a fter the 4th a/d conversion. trigger analog input a/d conversion result register adtrg signal anin adcr0 adtrg signal anin adcr1 adtrg signal anin adcr2 adtrg signal anin adcr3 while the adce bit of the adm0 regist er is 1, a/d conversion is repeated every time a trigger is input from the adtrg pin. this mode is suitable for applications in which calculat e the average of a/d conver sion result is calculated. figure 12-16. example of 4-buffer mode oper ation (external trigger select: 4 buffers) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter ( 4) ( 4) adtrg (1) the adce bit of adm0 is set to 1 (enabl e) (8) the external trigger is generated (2) the external trigger is generated (9) ani2 is a/d converted (3) ani2 is a/d converted (10) the conversion result is stored in adcr2 (4) the conversion result is stored in adcr0 (11) the external trigger is generated (5) the external trigger is generat ed (12) ani2 is a/d converted (6) ani2 is a/d converted (13) the conversion result is stored in adcr3 (7) the conversion result is stored in adcr1 (14) the intad interrupt is generated chapter 12 a/d converter 438 user?s manual u14359ej5v1ud 12.7.2 scan mode operation (external trigger scan) in this mode, the analog inputs specified by the adm0 re gister are selected sequentially from the ani0 pin using the adtrg signal as a trigger, and a/d converted. the a/d conversion resu lts are stored in the adcrn register corresponding to the analog input (n = 0 to 7). when the lower 4 channels (ani0 to ani3) of the analog in put are set by the adm0 register so that they are scanned, the a/d conversion end interrupt (intad) is gene rated when the number of a/ d conversions specified have ended, and a/d conversion is stopped. when the higher 4 channels (ani4 to ani7) of the analog in put are set by the adm0 register so that they are scanned, after the conversion of the lower 4 channels is en ded, the mode is shifted to the a/d trigger mode, and the remaining a/d conversions are executed. the conversion results are stored in the adcr n register corresponding to the analog input (n = 0 to 7). trigger analog input a/d conversion result register adtrg signal ani0 adcr0 adtrg signal ani1 adcr1 adtrg signal ani2 adcr2 adtrg signal ani3 adcr3 ani4 adcr4 ani5 adcr5 ani6 adcr6 (a/d trigger mode) ani7 adcr7 when the conversion of all the specified analog inputs has ended, the intad interrupt is generated and a/d conversion is stopped. when a trigger is input to the adtrg pin while the adce bit of the adm0 register is 1, a/d conversion is started again. this is most appropriate for applications in whic h multiple analog inputs are constantly monitored. chapter 12 a/d converter 439 user?s manual u14359ej5v1ud figure 12-17. example of scan mode operation (external trigger scan) (a) setting when scanning ani0 to ani3 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adtrg (1) the adce bit of adm0 is set to 1 (enabl e) (8) the external trigger is generated (2) the external trigger is generated (9) ani2 is a/d converted (3) ani0 is a/d converted (10) the conversion result is stored in adcr2 (4) the conversion result is stored in adcr0 (11) the external trigger is generated (5) the external trigger is generat ed (12) ani3 is a/d converted (6) ani1 is a/d converted (13) the conversion result is stored in adcr3 (7) the conversion result is stored in adcr1 (14) the intad interrupt is generated caution adtrg cannot be used as a trigger for th e analog inputs enclosed in the broken lines. when a setting is made to scan ani0 to ani7, ani4 to ani7 are converted in a/d trigger mode (see (b) below). (b) setting when scanning ani0 to ani7 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adtrg (1) to (13) same as (a) (18) ani6 is a/d converted (14) ani4 is a/d converted (19) the conversion result is stored in adcr6 (15) the conversion result is stored in adcr4 (20) ani7 is a/d converted (16) ani5 is a/d converted (21) the conversion result is stored in adcr7 (17) the conversion result is stored in adcr5 (22) the intad interrupt is generated chapter 12 a/d converter 440 user?s manual u14359ej5v1ud 12.8 notes on operation 12.8.1 stopping conversion operation when the adce bit of the adm0 register is set to 0 dur ing a conversion operation, t he conversion operation stops and the conversion results are not stored in the adcrn register (n = 0 to 7). 12.8.2 timer trigger/exter nal trigger interval set the interval (input time interval) of the trigger in t he external or timer trigger mode longer than the conversion time specified by the fr2 to fr0 bits of the adm1 register. (1) when interval = 0 when several triggers are input simultaneously, the an alog input with the smaller anin pin number is converted. the other trigger signals input simultaneously are ignored, and the number of trigger input is not counted. note, therefore, that t he saving of the result to the adcrn register upon the generation of an interrupt is an abnormality (n = 0 to 7). (2) when 0 < interval < conversion operation time when the timer trigger is input during a conversion operation, the conversion operation is aborted and the conversion starts according to the last timer trigger input. when conversion operations are aborte d, the conversion results are not stored in the adcrn register, and the number of trigger input are not counted. note, ther efore, that the saving of the result to the adcrn register upon the generation of an inte rrupt is an abnormality (n = 0 to 7). (3) when interval = conversion operation time when a trigger is input concurrently with the end of conversion (the end of conversion signal and the trigger are in contention), although the number of triggers input are counted, an interrupt is generated, and the value at the end of conversion is correctly saved in the adcrn register, desig n should be performed so that the interval is greater than the conversion operation time. 12.8.3 operation in standby mode (1) halt mode in this mode, a/d conversion continues. when this mode is released by nmi input, the adm0 and adm1 registers and adcrn register hold the value (n = 0 to 7). (2) idle mode, stop mode as clock supply to the a/d converter is stop ped, no conversion operations are performed. when these modes are released by nmi input or maskab le interrupt input (intp1xx), the adm0 and adm1 registers and the adcrn register hold the value. however, when the idle or software stop mode is set during a conversion operation, the conv ersion operation is stopped. at this time, if the mode released by nmi input or maskable interrupt input (i ntp1xx), the conversion operation re sumes, but the conversion result written to the adcrn register will become undefined (x = 0 to 3, n = 0 to 7). chapter 12 a/d converter 441 user?s manual u14359ej5v1ud 12.8.4 compare match interrupt in timer trigger mode the compare register?s match inte rrupt becomes an a/d conversion star t trigger and starts the conversion operation. when this happens, the compare register?s matc h interrupt also functions as a compare register match interrupt for the cpu. in order to pr event match interrupts from the compare register for the cpu, disable interrupts using the mask bits (p00mk0, p00mk1, p01mk0, p01mk1) of the interrupt control register (p00ic0, p00ic1, p01ic0, p01ic1). chapter 12 a/d converter 442 user?s manual u14359ej5v1ud 12.8.5 reconversion operation in timer 1 trigger mode in the timer 1 trigger mode, a/d conversion is started with the match interrupt signal (intm000) as the trigger. in the external trigger mode, a/d conversi on is started with the adtrg pin input timing as the trigger. however, when interrupt sources which are non-trigger s (intm001, intm010, intm011, intp001 note , intp010 note , intp011 note ) are generated during a/d conversion, after th is a/d conversion ends normally, the same a/d conversion may start again (reconversion operation). however, the reconversion oper ation will not be performed unless non-trigger interrupt sources are generated under these conditions. note external interrupt signals also used as external capt ure trigger inputs of timer c (tmc0, tmc1) also trigger reconversion. (1) reconversion operation in the ti mer trigger select 1 buffer 1 trigge r mode, external trigger select 1 buffer mode when non-trigger interrupt sources are generated during a/d conversion, the first a/d conversion ends normally, and the a/d conversion end interrupt (intad) is generated. th e a/d conversion results are stored in the adcrn register. a restarted a/d conversion is carried out normally , and the a/d conversion results are overwritten in the adcrn register. during reconver sion, the adcrn register can be read. after a/d conversion ends, the intad interrupt is generated, and a/d conversion stops. (2) reconversion operation in timer trigger select 4 buffer 1 trigger m ode, timer trigger scan 1 trigger mode, external trigger select 4 buffe r mode, external trigger scan mode a/d conversion is performed smoothl y until non-trigger interrupt sources are generated during conversion. when non-trigger interrupt sources are generated during a/d conversion , the current a/d conversion ends normally, and the a/d conversion re sults are stored in the adcrn register. after this, the same a/d conversion is performed, and the a/d conversion result s are overwritten in the adcrn register. during reconversion, the adcrn register can be read. a fter this, the remaining a/d conversion operations are performed normally, the a/d conversion end interrupt (intad) is generated, and a/d conversion stops. caution when non-trigger interrupt sources are ge nerated during the last a/ d conversion, the last a/d conversion ends normally, and the a/d con version end interrupt (int ad) is generated. after this, the same conversion as the last a/d conversion is pe rformed, the intad interrupt is generated, and a/d conversion stops. when reconversion operations occur, as conversion re sults are normal values, the effect on conversion will be minimized when using a methods in which the latest conversion values are acquired. however, if reconversion operations become abnormal, be sure to use the a/d trigger mode and start a/d conversion by setting the adce bit of the adm0 register in the interru pt servicing routine of the compare match interrupt of the timer or external pin interrupt. chapter 12 a/d converter 443 user?s manual u14359ej5v1ud 12.8.6 supplementary informa tion on a/d conversion time the time taken from trigger input to t he end of a/d conversion (t) is as follows. in a/d trigger mode (refer to figures 12-18 and 12-21 ): t = 9 to 11 clocks + number of clocks specifie d by the fr2 to fr0 bits of adm1 + 2 clocks in timer trigger mode (refer to figures 12-19 and 12-21 ): t = 5 to 7 clocks + number of clocks specified by the fr2 to fr0 bits of adm1 + 2 clocks in external trigger mode (refer to figures 12-20 and 12-21 ): t = 5 to 7 clocks + number of clocks specified by the fr2 to fr0 bits of adm1 + 2 clocks figure 12-18. a/d trigger mode a/ d conversion time (when adm1 = 00h) 7 to 9 clocks 9 to 11 clocks operation stopped (trigger input standby) sampling conversion of adn9 bit of adcrn register 2 clocks a/d conversion start f xx write signal adcs bit status remarks 1. f xx : internal system clock 2. n = 0 to 7 figure 12-19. timer trigger mode a/d co nversion time (when adm1 = 20h or 30h) conversion of adn9 bit of adcrn register 5 to 7 clocks operation stopped (trigger input standby) sampling f xx interrupt signal (intm0ab) status a/d conversion start remarks 1. f xx : internal system clock 2. n = 0 to 7 ab: when adm1 = 20h, ab = 00, when adm1 = 30h, ab = 00, 01, 10, 11 chapter 12 a/d converter 444 user?s manual u14359ej5v1ud figure 12-20. external trigger mode a/d conversion time (when adm1 = 60h) f xx adtrg input pin (falling edge) trigger detection signal (internal signal) status operation stopped (trigger input standby) sampling conversionof adn9 bit of adcrn reister a/d conversion start noise elimination (84 ns (typ.)) 5 to 7 clocks remark f xx : internal system clock figure 12-21. a/d conversion outline (one a/d conversion, fr0 to fr2 bits of adm1 register = 000 (96 clocks) sampling one a/d conversion number of clocks set using fr2 to fr0 bits of adm1 register (96 clocks) 2 clocks 4 clocks conversion of adn9 bit of adcrn register conversion of adn0 bit of adcrn register note f xx status intad interrupt note a/d conversion results (adcrn) can be read. remarks 1. f xx : internal system clock 2. n = 0 to 7 chapter 12 a/d converter 445 user?s manual u14359ej5v1ud 12.9 how to read a/d converter?s characteristic table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that can be recognized, i. e., the ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit). the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of c onvertible analog input voltages expressed in percentage, and can be expressed as follows, independently of the resolution. 1%fsr = (maximum value of convertible analog input vo ltage ? minimum value of convertible analog input voltage)/100 = (av ref ? 0)/100 = av ref /100 where the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the total error, independently of the resolution. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, linearity error and erro rs that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. figure 12-22. overall error ideal line 0 ...... 0 1 ...... 1 digital output overall error analog input av dd 0 chapter 12 a/d converter 446 user?s manual u14359ej5v1ud (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. because the a/d converter converts ana log input voltages in a range of 1/2 lsb into the same digital codes, quantization error is unavoidable. this error is not included in the total error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristic table. figure 12-23. quan tization error quantization error 1 ...... 1 0 ...... 0 0av ref analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this is a difference between the actually measured anal og input voltage and its theoretical value when digital output changes from 0?000 to 0?001 (1/2 lsb). figure 12-24. zero-scale error av ref analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10123 100 011 010 001 000 zero-scale errors chapter 12 a/d converter 447 user?s manual u14359ej5v1ud (5) full-scale error this is a difference between the actually measured anal og input voltage and its theoretical value when digital output changes from 1?110 to 0?111 (full scale ? 3/2 lsb). figure 12-25. full-scale error av ref analog input (lsb) digital output (lower 3 bits) 111 av ref ? 3 0 av ref ? 2av ref ? 1 100 011 010 000 full-scale errors (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error indicates the difference between the actually measured value and its theoretical value when a specific code is output. figure 12-26. differential linearity error ideal widths of 1 lsb differential linearity error 1 ...... 1 0 ...... 0 av ref analog input digital output chapter 12 a/d converter 448 user?s manual u14359ej5v1ud (7) integral linearity error this error indicates the extent to which the conversion ch aracteristics differ from the ideal linear relations. it indicates the maximum value of difference between t he actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. figure 12-27. integral linearity error 1 ...... 1 0 ...... 0 0av ref analog input digital output ideal line integral linearity errors (8) conversion time this is the time required to obtain digital output after each trigger has been generated. the conversion time in the characteristic table includes sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. sampling time conversion time 449 user's manual u14359ej5v1ud chapter 13 pwm unit 13.1 features ? pwmn: 2 channels ? pwmn: output pulse active level can be selected ? operation clock can be selected from among f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xx /64 (f xx is the internal system clock) ? pwmn output resolution can be sele cted from among 8, 9, 10, 12 bits remark n = 0, 1 13.2 block diagram counter (tmpn) (edge latch) comparator compare register (cmpn) (level latch) pwm buffer register (pwmbn) (level latch) 0 to 7 0 to 8 0 to 9 0 to 11 12 12 12 pwm control register n (pwmcn) (edge latch) alvn prmn1 pwmcaen 0 prmn0 pwpn1 pwpn2 pwpn0 0 to 7 0 to 8 0 to 9 0 to 11 s r note q pwmn reload processing overflow match output control block 2 3 2 selector f xx /2 selclk f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 note reset has priority. remarks 1. n = 0, 1 2. f xx : internal system clock chapter 13 pwm unit 450 user?s manual u14359ej5v1ud 13.3 control register (1) pwm control registers 0, 1 (pwmc0, pwmc1) the pwmcn register is used to contro l the pwmn?s operations (n = 0, 1). the pwmcn register can be read/wr itten in 8-bit or 1-bit units. caution when pwmn is used, be sure to set ext ernal pins related to pw mn to control mode. following that, set the operation clock, etc. using the pwmcn register and set the pwmen bit to 1 after the pwmbn register setting is made. chapter 13 pwm unit 451 user?s manual u14359ej5v1ud <7> <6> 5 4 3 2 1 0 address after reset pwmcn pwmen alvn prmn1 prmn0 0 pwpn2 pwpn1 pwpn0 fffffc00h, fffffc10h 40h bit position bit name description 7 pwmen note (n = 0, 1) pwm enable this bit is used to enable or disable pwmn operation. 0: pwm operation disabled 1: pwm operation enabled 6 alvn (n = 0, 1) active level this bit is used to specify t he active level for pwmn output. 0: active level is low level 1: active level is high level the pwmn outputs inactive level (low level) of the alvn bit after reset. prescaler mode this bit is used to select the bit length for the counter (tmpn) and compare register (cmpn). prmn1 prmn0 bit length for tmpn and cmpn 0 0 8 bits 0 1 9 bits 1 0 10 bits 1 1 12 bits 5, 4 prmn1, prmn0 (n = 0, 1) pwm prescaler clock mode this bit is used to select the pwmn?s operating clock. pwpn2 pwpn1 pwpn0 operating clock 0 0 0 f xx /2 0 0 1 f xx /4 0 1 0 f xx /8 0 1 1 f xx /16 1 0 0 f xx /32 1 0 1 f xx /64 other than above setting prohibited 2 to 0 pwpn2 to pwpn0 (n = 0, 1) note if pwmen is changed from 0 to 1, t he counter (tmpn) is reset to star t counting from 000h (in 12 bits). the first overflow permits the pwmn signal activa tion. if the bit length and operating clock of pwm0 and pwm1 are the same, the activation timing of t hese two pwmn signals can be adjusted. if pwmen was already 1, the counter is not reset upon an additional write of 1. when setting pwmen to 1, set it to 0 beforehand. remarks 1. n = 0, 1 2. f xx : internal system clock chapter 13 pwm unit 452 user?s manual u14359ej5v1ud (2) pwm buffer registers 0, 1 (pwmb0, pwmb1) the pwmbn register is a 12-bit buffer register that is used to set contro l data for the active signal width of pwmn output. bits 15 to 12 are fixed to zero. even if 1 is written in these bits, it is ignored. it is possible to directly read the values of bits 11 to 8 as written irrespective of t he bit length setting made by the pwmcn register. the contents in pwmbn registers are transferred to compare registers (cmp n) at the timing of the generation of an overflow from the pwmn output control counter (tmpn). the pwm buffer registers can be read or written in 16-bit units. remark n = 0, 1 15 0 14 0 13 0 12 0 11 pwm b11 10 pwm b10 9 pwm b9 8 pwm b8 7 pwm b7 6 pwm b6 5 pwm b5 4 pwm b4 3 pwm b3 2 pwm b2 1 pwm b1 0 pwm b0 pwmb0 15 0 14 0 13 0 12 0 11 pwm b11 10 pwm b10 9 pwm b9 8 pwm b8 7 pwm b7 6 pwm b6 5 pwm b5 4 pwm b4 3 pwm b3 2 pwm b2 1 pwm b1 0 pwm b0 pwmb1 address fffffc02h after reset 0000h address fffffc12h after reset 0000h 13.4 operation 13.4.1 basic operations when a pwmn pulse is output, the required data is fi rst set to the pwmcn and pwmbn registers, then the pwmcn register?s pwmen bit is set (1). this clears (0) the counter (tmpn) and, when t he first overflow occurs, the active level is set for pwmn output and the data is transfe rred from the pwmbn register to the compare register (cmpn). afterward, pwmn output goes inactive when a ma tch occurs between the tmpn and cmpn register values. when this is repeated, a pwmn signal whose active level is s pecified by the alvn bit in the pwmcn register is output from the pwmn pin. when the pwmcn register?s pwmen bit is cleared (0), pwmn output is stopped immediately and is set to the inactive level for the alvn level specified by the pwmcn register. if, during pwmn signal output, the values of the pwpn2 to pwpn0 bits, prm n1 and prmn0 bits, or alvn bit are changed, the cycle width and pulse width of the pwmn si gnal are not guaranteed within the cycle where the changes were made. remark n = 0, 1 chapter 13 pwm unit 453 user?s manual u14359ej5v1ud figure 13-1. pwm basic operation timing counter 00h feh ffh 00h 01h 02h feh ffh 00h 01h overflow signal pwmen bit start tmpn count pwmbn register feh cmpn register feh 00h comparator match signal reload pwmn (output) set reset set full count feh count remark n = 0, 1 figure 13-2. timing for write operation to pwmbn register counter overflow signal pwmen bit pwmbn register m cmpn register m x comparator match signal pwmn (output) set set full count fbh fch fdh feh ffh 00h 01h 00h start tmpn count 01h 02h 03h x fdh feh ffh 00h 01h 02h 03h 04h feh ffh 00h 01h m n pwmbn n q n q m count set n count remark n = 0, 1 chapter 13 pwm unit 454 user?s manual u14359ej5v1ud figure 13-3. timing when pwmbn register is set to 00h overflow signal pwmbn register 00h cmpn register comparator match signal pwmn (output) feh ffh 00h 01h feh 00h 01h 02h feh ffh 00h 01h 02h ffh counter 00h not set to active level l remark n = 0, 1 figure 13-4. timing when pwmbn register is set to ffh overflow signal pwmbn register ffh cmpn register comparator match signal pwmn (output) feh ffh 00h 01h feh 00h 01h 02h feh ffh 00h 01h 02h ffh counter ffh 1 count remark n = 0, 1 chapter 13 pwm unit 455 user?s manual u14359ej5v1ud 13.4.2 repetition frequency the repetition frequencies of pwmn are shown below (n = 0, 1). pwmn operating frequency resolution repetition frequency f xx /2 8 bits 9 bits 10 bits 12 bits f xx /2 9 f xx /2 10 f xx /2 11 f xx /2 13 f xx /4 8 bits 9 bits 10 bits 12 bits f xx /2 10 f xx /2 11 f xx /2 12 f xx /2 14 f xx /8 8 bits 9 bits 10 bits 12 bits f xx /2 11 f xx /2 12 f xx /2 13 f xx /2 15 f xx /16 8 bits 9 bits 10 bits 12 bits f xx /2 12 f xx /2 13 f xx /2 14 f xx /2 16 f xx /32 8 bits 9 bits 10 bits 12 bits f xx /2 13 f xx /2 14 f xx /2 15 f xx /2 17 f xx /64 8 bits 9 bits 10 bits 12 bits f xx /2 14 f xx /2 15 f xx /2 16 f xx /2 18 remark f xx : internal system clock 13.5 cautions the pwm0 pin has an alternate function as the p00 pin (port 0) and the pwm1 pin has an alternate function as the p10 pin (port 1). when using these pins for pwmn output, set the bits corresponding to the pmc0 and pmc1 registers to 1. if the bit settings corresponding to the pmc0 and pmc1 registers are changed during pwmn pulse output, the pwmn pulse output is not guaranteed. user?s manual u14359ej5v1ud 456 chapter 14 port functions 14.1 features ? input-only ports: 9 input/output ports: 106 ? function alternately as other peripheral i/o pins. ? it is possible to specify input and output in 1-bit units. chapter 14 port functions user?s manual u14359ej5v1ud 457 14.2 port configuration the v850e/ma1 incorporates a total of 115 input/output ports (including 9 input-only ports) labeled ports 0 through 5, and al, ah, dl, cs, ct, cm, cd, and bd. the port configuration is shown below. port 0 p00 to p07 port 1 p10 to p13 port 2 p21 to p27 p20 port 3 p30 to p37 port 4 p40 to p45 port 5 p50 to p52 port 7 p70 to p77 port al port ah pal0 to pal15 pah0 to pah9 port dl port cs port ct port cm pdl0 to pdl15 pcs0 to pcs7 pct0 pct1 pct4 pct7 pcm0 to pcm5 port cd pcd0 to pcd3 port bd pbd0 to pbd3 remark ports other than port 7 are 5 v tolerant buffers. chapter 14 port functions user?s manual u14359ej5v1ud 458 (1) function of each port the port functions of this product are shown below. 8-bit and 1-bit operations are possible on all ports, allo wing various kinds of control to be performed. in addition to their port functions, these pins also functi on as on-chip peripheral i/o input/output pins in the control mode. for the block types of each port, see (3) block diagram of port. port name pin name port function function in control mode block type port 0 p00 to p07 8-bit i/o real-time pulse unit (rpu) i/o external interrupt input pwm output dma controller input a, b, h port 1 p10 to p13 4-bit i/o real-time pulse unit (rpu) i/o external interrupt input pwm output a, b port 2 p20 to p27 1-bit input, 7-bit i/o nmi input real-time pulse unit (rpu) i/o external interrupt input dma controller output a, b, f, n port 3 p30 to p37 8-bit i/o serial interface i/o (csi2, uart2) external interrupt input a/d converter external trigger input b, h, i, l port 4 p40 to p45 6-bit i/o serial interf ace i/o (uart0/csi0, uart1/csi1) h, g, m port 5 p50 to p52 3-bit i/o real-time pulse unit (rpu) i/o external interrupt input a, b port 7 p70 to p77 8-bit input a/d converter input c port al pal0 to pal15 8-/16-bit i/o ex ternal address bus (a0 to a15) j port ah pah0 to pah9 8-/10-bit i/o external address bus (a16 to a25) j port dl pdl0 to pdl15 8-/16-bit i/o external data bus (d0 to d15) o port cs pcs0 to pcs7 8-bit i/o external bus interface control signal output j, k port ct pct0, pct1, pct4 to pct7 6-bit i/o external bus interface control signal output j port cm pcm0 to pcm5 6-bit i/o wait insertion signal input internal system clock output/bus clock output external bus interface control signal i/o self-refresh request signal input d, e, j, k port cd pcd0 to pcd3 4-bit i/o external bus interface control signal output j, k port bd pbd0 to pbd3 4-bit i/o dma controller output j chapter 14 port functions user?s manual u14359ej5v1ud 459 (2) function when each port?s pins are reset a nd registers that set the port/control mode (1/2) pin function after reset port name pin name single-chip mode 0 single-chip mode 1 romless mode 0 romless mode 1 register that sets the mode p00/pwm0 p00 (input mode) p01/intp000/ti000 p01 (input mode) p02/intp001 p02 (input mode) p03/to00 p03 (input mode) pmc0 p04/dmarq0/intp100 p04 (input mode) p05/dmarq1/intp101 p05 (input mode) p06/dmarq2/intp102 p06 (input mode) port 0 p07/dmarq3/intp103 p07 (input mode) pmc0, pfc0 p10/pwm1 p10 (input mode) p11/intp010/ti010 p11 (input mode) p12/intp011 p12 (input mode) port 1 p13/to01 p13 (input mode) pmc1 p20/nmi nmi ? p21/intp020/ti020 p21 (input mode) p22/intp021 p22 (input mode) p23/to02 p23 (input mode) pmc2 p24/tc0/intp110 p24 (input mode) p25/tc1/intp111 p25 (input mode) p26/tc2/intp112 p26 (input mode) port 2 p27/tc3/intp113 p27 (input mode) pmc2, pfc2 p30/so2/intp130 p30 (input mode) p31/si2/intp131 p31 (input mode) p32/sck2/intp132 p32 (input mode) p33/txd2/intp133 p33 (input mode) p34/rxd2/intp120 p34 (input mode) pmc3, pfc3 p35/intp121 p35 (input mode) p36/intp122 p36 (input mode) port 3 p37/adtrg/intp123 p37 (input mode) pmc3 p40/txd0/so0 p40 (input mode) p41/rxd0/si0 p41 (input mode) pmc4, pfc4 p42/sck0 p42 (input mode) pmc4 p43/txd1/so1 p43 (input mode) p44/rxd1/si1 p44 (input mode) pmc4, pfc4 port 4 p45/sck1 p45 (input mode) pmc4 chapter 14 port functions user?s manual u14359ej5v1ud 460 (2/2) pin function after reset port name pin name single-chip mode 0 single-chip mode 1 romless mode 0 romless mode 1 register that sets the mode p50/intp030/ti030 p50 (input mode) p51/intp031 p51 (input mode) port 5 p52/to03 p52 (input mode) pmc5 port 7 p70/ani0 to p77/ani7 p70 to p77 (input mode) ? port bd pbd0/dmaak0 to pbd3/dmaak3 pbd0 to pbd3 (input mode) pmcbd pcm0/wait pcm0 (input mode) wait pmccm pcm1/clkout/busclk pcm1 (input mode) clkout/busclk pmccm, pfccm pcm2/hldak pcm2 (input mode) hldak pcm3/hldrq pcm3 (input mode) hldrq pcm4/refrq pcm4 (input mode) refrq port cm pcm5/selfref pcm5 (input mode) selfref pmccm pct0/lcas/lwr/ldqm pct0 (input mode) lcas/lwr/ldqm pct1/ucas/uwr/udqm pct1 (input mode) ucas/uwr/udqm pct4/rd pct4 (input mode) rd pct5/we pct5 (input mode) we pct6/oe pct6 (input mode) oe port ct pct7/bcyst pct7 (input mode) bcyst pmcct pcs0/cs0 pcs0 (input mode) cs0 pcs1/cs1/ras1 pcs1 (input mode) cs1/ras1 pmccs pcs2/cs2/iowr pcs2 (input mode) cs2/iowr pmccs, pfccs pcs3/cs3/ras3 pcs3 (input mode) cs3/ras3 pcs4/cs4/ras4 pcs4 (input mode) cs4/ras4 pmccs pcs5/cs5/iord pcs5 (input mode) cs5/iord pmccs, pfccs pcs6/cs6/ras6 pcs6 (input mode) cs6/ras6 port cs pcs7/cs7 pcs7 (input mode) cs7 pmccs pcd0/sdcke pcd0 (input mode) sdcke pcd1/sdclk pcd1 (input mode) sdclk pmccd pcd2/lbe/sdcas pcd2 (input mode) lbe/sdcas port cd pcd3/ube/sdras pcd3 (input mode) ube/sdras pmccd, pfccd port ah pah0/a16 to pah9/a25 pah0 to pah9 (input mode) a16 to a25 pmcah port al pal0/a0 to pal15/a15 pal0 to pal15 (input mode) a0 to a15 pmcal port dl pdl0/d0 to pdl15/d15 pdl0 to pdl15 (input mode) d0 to d15 pmcdl chapter 14 port functions user?s manual u14359ej5v1ud 461 (3) block diagram of port figure 14-1. block diagram of type a internal bus wr pmc wr pm wr port rd in pmcmn pmmn pmn output signal in control mode selector selector selector pmn address remark m: port number n: bit number chapter 14 port functions user?s manual u14359ej5v1ud 462 figure 14-2. block diagram of type b wr pmc wr pm wr port rd in pmcmn pmmn pmn selector selector pmn address noise elimination edge detection input signal in control mode internal bus remark m: port number n: bit number figure 14-3. block diagram of type c rd in p7n anin sample & hold circuit input signal in control mode internal bus remark n = 0 to 7 chapter 14 port functions user?s manual u14359ej5v1ud 463 figure 14-4. block diagram of type d wr pmc mode0 to mode2 wr port rd in pmccmn wr pm pmcmn pcmn pcmn address input signal in control mode internal bus selector selector remark n = 0, 3 chapter 14 port functions user?s manual u14359ej5v1ud 464 figure 14-5. block diagram of type e wr pm wr port rd in pmcm5 pcm5 pcm5 address input signal in control mode internal bus selector selector wr pmc mode0 to mode2 pmccm5 figure 14-6. block diagram of type f rd in p20 address noise elimination edge detection 1 nmi internal bus selector chapter 14 port functions user?s manual u14359ej5v1ud 465 figure 14-7. block diagram of type g wr pmc wr pm rd in pmc4n pm4n wr port p4n p4n address output signal in control mode internal bus selector selector selector selector wr pfc pfc4n remark n = 0, 3 chapter 14 port functions user?s manual u14359ej5v1ud 466 figure 14-8. block diagram of type h wr pfc wr pmc wr pm wr port rd in pfcmn pmcmn pmmn pmn pmn address input signal in control mode internal bus selector selector selector edge detection remark m: port number n: bit number chapter 14 port functions user?s manual u14359ej5v1ud 467 figure 14-9. block diagram of type i wr pfc wr pmc wr pm wr port rd in pfc32 pmc32 pm32 p32 p32 sck2 output enable signal address input signal in control mode output signal in control mode internal bus selector selector selector selector chapter 14 port functions user?s manual u14359ej5v1ud 468 figure 14-10. block diagram of type j wr pm wr port rd in pmmn wr pmc pmcmn pmn pmn mode0 to mode2 address output signal in control mode internal bus selector selector selector remark m: port number n: bit number chapter 14 port functions user?s manual u14359ej5v1ud 469 figure 14-11. block diagram of type k wr pfc mode0 to mode2 wr pmc wr pm wr port rd in pfcmn pmcmn pmmn pmn pmn address output signal in control mode internal bus selector selector selector selector remark m: port number n: bit number chapter 14 port functions user?s manual u14359ej5v1ud 470 figure 14-12. block diagram of type l wr pmc wr pm rd in pmc3n pm3n wr port p3n p3n address output signal in control mode internal bus selector selector selector wr pfc pfc3n input signal in control mode remark n = 0, 3 chapter 14 port functions user?s manual u14359ej5v1ud 471 figure 14-13. block diagram of type m wr pmc wr pm wr port rd in pmc4n pm4n p4n p4n address input signal in control mode output signal in control mode sckx output enable signal internal bus selector selector selector remark n = 2, 5 x: 0 (when n = 2) 1 (when n = 5) chapter 14 port functions user?s manual u14359ej5v1ud 472 figure 14-14. block diagram of type n wr pmc wr pm rd in pmc2n pm2n wr port p2n p2n address output signal in control mode internal bus selector selector selector wr pfc pfc2n input signal in control mode remark m: port number n: bit number chapter 14 port functions user?s manual u14359ej5v1ud 473 figure 14-15. block diagram of type o wr pm wr port rd in pmdln wr pmc pmcdln pdln pdln address output signal in control mode input signal in control mode i/o control internal bus selector selector selector i/o control mode0 to mode2 remark n = 0 to 15 chapter 14 port functions user?s manual u14359ej5v1ud 474 14.3 port pin functions 14.3.1 port 0 port 0 is an 8-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset p0 p07 p06 p05 p04 p03 p02 p01 p00 fffff400h undefined bit position bit name function 7 to 0 p0n (n = 7 to 0) port 0 i/o port in addition to their function as port pins, the port 0 pins ca n also operate as real-time pulse unit (rpu) i/o, external interrupt request inputs, pwm output, and dm a request inputs in the control mode. (1) operation in control mode port alternate function remark block type p00 pwm0 pwm output a p01 intp000/ti000 external interrupt request input/ real-time pulse unit (rpu) input p02 intp001 external interrupt request input b p03 to00 real-time pulse unit (rpu) output a port 0 p04 to p07 dmarq0/intp100 to dmarq3/intp103 dma request input/ external interrupt request input h (2) i/o mode/control mode setting the port 0 i/o mode setting is performed by the port 0 mode register (pm0), and t he control mode setting is performed by the port 0 mode control register (pmc0) and the port 0 function control register (pfc0). (a) port 0 mode register (pm0) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pm0 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 fffff420h ffh bit position bit name function 7 to 0 pm0n (n = 7 to 0) port mode specifies input/output mode for p0n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 475 (b) port 0 mode control register (pmc0) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmc0 pmc07 pmc06 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 fffff440h 00h bit position bit name function 7 to 4 pmc0n (n = 7 to 4) port mode control specifies operation mode of p0n pin in combination with the pfc0 register. 0: i/o port mode 1: external interrupt request (intp103 to intp100) input mode/dma request (dmarq3 to dmarq0) input mode 3 pmc03 port mode control specifies operation mode of p03 pin. 0: i/o port mode 1: to00 output mode 2 pmc02 port mode control specifies operation mode of p02 pin. 0: i/o port mode 1: external interrupt request (intp001) input mode 1 pmc01 port mode control specifies operation mode of p01 pin. 0: i/o port mode 1: external interrupt request (intp000) input mode/ti000 input mode there is no register that switches between the external interrupt request (intp000) input mode and ti000 input mode ? when ti000 input mode is selected: mask the external interrupt request (intp000) or specify the ccc00 register as compare register. ? when external interrupt request (intp 000) input mode (including timer capture input) is selected: set the eti0 bit of the tmcc01 register to 0. 0 pmc00 port mode control specifies operation mode of p00 pin. 0: i/o port mode 1: pwm0 output mode chapter 14 port functions user?s manual u14359ej5v1ud 476 (c) port 0 function control register (pfc0) this register can be read/written in 8-bit or 1-bit units. bits 3 to 0, however, are fixed to 0, so writing 1 to these bits is ignored. caution when the port mode is specified by the port 0 mode control register (pmc0), the pfc0 setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfc0 pfc07 pfc06 pfc05 pfc04 0 0 0 0 fffff460h 00h bit position bit name function 7 to 4 pfc0n (n = 7 to 4) port function control specifies operation mode of p0n pin in control mode. 0: external interrupt request (intp103 to intp100) input mode 1: dma (dmarq3 to dmarq0) request input mode chapter 14 port functions user?s manual u14359ej5v1ud 477 14.3.2 port 1 port 1 is a 4-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset p1 ? ? ? ? p13 p12 p11 p10 fffff402h undefined bit position bit name function 3 to 0 p1n (n = 3 to 0) port 1 i/o port in addition to their function as port pins, the port 1 pins ca n also operate as real-time pulse unit (rpu) i/o, external interrupt request inputs, and pw m output in the control mode. (1) operation in control mode port alternate function remark block type p10 pwm1 pwm output a p11 ti010/intp010 external interrupt request input/ real-time pulse unit (rpu) input p12 intp011 external interrupt request input b port 1 p13 to01 real-time pulse unit (rpu) output a (2) i/o mode/control mode setting the port 1 i/o mode setting is performed by the port 1 mode register (pm1), and t he control mode setting is performed by the port 1 mode control register (pmc1). (a) port 1 mode register (pm1) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pm1 1 1 1 1 pm13 pm12 pm11 pm10 fffff422h ffh bit position bit name function 3 to 0 pm1n (n = 3 to 0) port mode specifies input/output mode for p1n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 478 (b) port 1 mode control register (pmc1) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmc1 0 0 0 0 pmc13 pmc12 pmc11 pmc10 fffff442h 00h bit position bit name function 3 pmc13 port mode control specifies operation mode of p13 pin. 0: i/o port mode 1: to01 output mode 2 pmc12 port mode control specifies operation mode of p12 pin. 0: i/o port mode 1: external interrupt request (intp011) input mode 1 pmc11 port mode control specifies operation mode of p11 pin. 0: i/o port mode 1: external interrupt request (intp010) input mode/ti010 input mode there is no register that switches between the external interrupt request (intp010) input mode and ti010 input mode. ? when the ti010 input mode is selected: mask the external interrupt (intp010) or specify the ccc10 register as compare register. ? when external interrupt request (intp 010) input mode (including timer capture input) is selected: set the eti1 bit of the tmcc11 register to 0. 0 pmc10 port mode control specifies operation mode of p10 pin. 0: i/o port mode 1: pwm1 output mode chapter 14 port functions user?s manual u14359ej5v1ud 479 14.3.3 port 2 port 2 is an i/o port that can be set to the input or output mode in 1-bit units except for p20, which is an input-only pin. caution p20 is fixed to nmi input. the level of th e nmi input can be read regardless of the pm2 and pmc2 registers? values. 7 6 5 4 3 2 1 0 address after reset p2 p27 p26 p25 p24 p23 p22 p21 p20 fffff404h undefined bit position bit name function 7 to 1 p2n (n = 7 to 1) port 2 i/o port in addition to their function as port pins, the port 2 pins can also operate as the real-time pulse unit (rpu) i/o, external interrupt request inputs, and the dma end (te rminal count) signal outputs in the control mode. (1) operation in control mode port alternate function remark block type p20 nmi non-maskable interrupt request input f p21 intp020/ti020 external interrupt request input/ real-time pulse unit (rpu) input p22 intp021 external interrupt request input b p23 to02 real-time pulse unit (rpu) output a port 2 p24 to 27 tc0/intp110 to tc3/intp113 dma end signal outputs/external interrupt request inputs n chapter 14 port functions user?s manual u14359ej5v1ud 480 (2) i/o mode/control mode setting the port 2 i/o mode setting is performed by the port 2 mode register (pm2), and t he control mode setting is performed by the port 2 mode control register (pmc2) and the port 2 function control register (pfc2). (a) port 2 mode register (pm2) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 1 fffff424h ffh bit position bit name function 7 to 1 pm2n (n = 7 to 1) port mode specifies input/output mode for p2n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 481 (b) port 2 mode control register (pmc2) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmc2 pmc27 pmc26 pmc25 pmc24 pmc23 pmc22 pmc21 1 fffff444h 01h bit position bit name function 7 to 4 pmc2n (n = 7 to 4) port mode control specifies operation mode of p2n pin in combination with the pfc2 register. 0: i/o port mode 1: external input request (intp113 to intp110) input mode/ dma end signal (tc3 to tc0) output mode 3 pmc23 port mode control specifies operation mode of p23 pin. 0: i/o port mode 1: to02 output mode 2 pmc22 port mode control specifies operation mode of p22 pin. 0: i/o port mode 1: external interrupt request (intp021) input mode 1 pmc21 port mode control specifies operation mode of p21 pin. 0: i/o port mode 1: external interrupt request (intp020) input mode/ ti020 input mode there is no register that switches between the external interrupt request (intp020) input mode and ti020 input mode. ? when the ti020 input mode is selected: mask the external interrupt request (intp020) or specify the ccc20 register as a compare register. ? when the external interrupt request (intp020) input mode (including timer capture input) is selected: set the eti2 bit of the tmcc21 register to 0. chapter 14 port functions user?s manual u14359ej5v1ud 482 (c) port 2 function control register (pfc2) this register can be read/written in 8-bit or 1-bit units. bits 3 to 0, however, are fixed to 0 by hardware, so writing 1 to these bits is ignored. caution when the port mode is specified by the port 2 mode control register (pmc2), the pfc2 setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfc2 pfc27 pfc26 pfc25 pfc24 0 0 0 0 fffff464h 00h bit position bit name function 7 to 4 pfc2n (n = 7 to 4) port function control specifies operation mode of p2n pin in control mode. 0: external interrupt request (intp113 to intp110) input mode 1: dma end signal (tc3 to tc0) output mode chapter 14 port functions user?s manual u14359ej5v1ud 483 14.3.4 port 3 port 3 is an 8-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset p3 p37 p36 p35 p34 p33 p32 p31 p30 fffff406h undefined bit position bit name function 7 to 0 p3n (n = 7 to 0) port 3 i/o port in addition to their function as port pins, the port 3 pins can also operate as the serial interface (csi2, uart2) i/o, external interrupt request inputs, and a/d converte r external trigger input in the control mode. (1) operation in control mode port alternate function remark block type p30 so2/intp130 l p31 si2/intp131 h p32 sck2/intp132 serial interface (csi2) i/o/ external interrupt request inputs i p33 txd2/intp133 l p34 rxd2/intp120 serial interface (uart2) i/o/ external interrupt request inputs h p35 intp121 p36 intp122 external interrupt request inputs port 3 p37 adtrg/intp123 a/d converter external trigger input/ external interrupt request input b (2) i/o mode/control mode setting the port 3 i/o mode setting is performed by the port 3 mode register (pm3), and t he control mode setting is performed by the port 3 mode control register (pmc3) and the port 3 function control register 3 (pfc3). (a) port 3 mode register (pm3) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pm3 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 fffff426h ffh bit position bit name function 7 to 0 pm3n (n = 7 to 0) port mode specifies input/output mode for p3n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 484 (b) port 3 mode control register (pmc3) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmc3 pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 fffff446h 00h bit position bit name function 7 pmc37 port mode control specifies operation mode of p37 pin. 0: i/o port mode 1: a/d converter exter nal trigger (adtrg) input mode/ external interrupt request (intp123) input mode there is no register that switches between the a/d converter external trigger (adtrg) input mode and external interrupt request (intp123) input mode. ? when the a/d converter external trigger (adtrg) input mode is selected: set to external trigger mode using the adm1 register. ? when the external interrupt request (intp123) input mode is selected: set to the mode other than external tr igger mode using the adm1 register. 6 pmc36 port mode control specifies operation mode of p36 pin. 0: i/o port mode 1: external interrupt request (intp122) input mode 5 pmc35 port mode control specifies operation mode of p35 pin. 0: i/o port mode 1: external interrupt request (intp121) input mode 4 pmc34 port mode control specifies operation mode of p34 pin. 0: i/o port mode 1: rxd2 input mode/external interrupt request (intp120) input mode 3 pmc33 port mode control specifies operation mode of p33 pin. 0: i/o port mode 1: txd2 output mode/external interrupt request (intp133) input mode 2 pmc32 port mode control specifies operation mode of p32 pin. 0: i/o port mode 1: sck2 input/output mode/external interrupt request (intp132) input mode 1 pmc31 port mode control specifies operation mode of p31 pin. 0: i/o port mode 1: si2 input mode/external interrupt request (intp131) input mode 0 pmc30 port mode control specifies operation mode of p30 pin. 0: i/o port mode 1: so2 output mode/external interrupt request (intp130) input mode chapter 14 port functions user?s manual u14359ej5v1ud 485 (c) port 3 function control register (pfc3) this register can be read/written in 8-bit or 1-bit units. bits 5 to 7, however, are fixed to 0, so writing 1 to these bits is ignored. caution when the port mode is specified by the port 3 mode control register (pmc3), the pfc3 setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfc3 0 0 0 pfc34 pfc33 pfc32 pfc31 pfc30 fffff466h 00h bit position bit name function 4 pfc34 port function control specifies operation mode of p34 pin in control mode. 0: rxd2 input mode 1: external interrupt request (intp120) input mode 3 pfc33 port function control specifies operation mode of p33 pin in control mode. 0: txd2 output mode 1: external interrupt request (intp133) input mode 2 pfc32 port function control specifies operation mode of p32 pin in control mode. 0: sck2 i/o mode 1: external interrupt request (intp132) input mode 1 pfc31 port function control specifies operation mode of p31 pin in control mode. 0: si2 input mode 1: external interrupt request (intp131) input mode 0 pfc30 port function control specifies operation mode of p30 pin in control mode. 0: so2 output mode 1: external interrupt request (intp130) input mode chapter 14 port functions user?s manual u14359ej5v1ud 486 14.3.5 port 4 port 4 is a 6-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset p4 ? ? p45 p44 p43 p42 p41 p40 fffff408h undefined bit position bit name function 5 to 0 p4n (n = 5 to 0) port 4 i/o port in addition to their function as port pins, the port 4 pi ns can also operate as the serial interface (uart0/csi0, uart1/csi1) i/o in the control mode. (1) operation in control mode port alternate function remark block type p40 txd0/so0 g p41 rxd0/si0 h p42 sck0 serial interface (uart0/csi0) i/o m p43 txd1/so1 g p44 rxd1/si1 h port 4 p45 sck1 serial interface (uart1/csi1) i/o m (2) i/o mode/control mode setting the port 4 i/o mode setting is performed by the port 4 mode register (pm4), and t he control mode setting is performed by the port 4 mode control register (pmc4) and the port 4 function control register (pfc4). (a) port 4 mode register (pm4) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pm4 1 1 pm45 pm44 pm43 pm42 pm41 pm40 fffff428h ffh bit position bit name function 5 to 0 pm4n (n = 5 to 0) port mode specifies input/output mode for p4n pin 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 487 (b) port 4 mode control register (pmc4) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmc4 0 0 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 fffff448h 00h bit position bit name function 5 pmc45 port mode control specifies operation mode of p45 pin. 0: i/o port mode 1: sck1 i/o mode 4 pmc44 port mode control specifies operation mode of p44 pin. 0: i/o port mode 1: rxd1/si1 input mode 3 pmc43 port mode control specifies operation mode of p43 pin. 0: i/o port mode 1: txd1/so1 output mode 2 pmc42 port mode control specifies operation mode of p42 pin. 0: i/o port mode 1: sck0 i/o mode 1 pmc41 port mode control specifies operation mode of p41 pin. 0: i/o port mode 1: rxd0/si0 input mode 0 pmc40 port mode control specifies operation mode of p40 pin. 0: i/o port mode 1: txd0/so0 output mode chapter 14 port functions user?s manual u14359ej5v1ud 488 (c) port 4 function control register (pfc4) this register can be read/written in 8-bit or 1-bit units. bits 7 to 5 and 2, however, are fixed to 0, so writing 1 to these bits is ignored. caution when the port mode is specified by the port 4 mode control register (pmc4), the pfc4 register setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfc4 0 0 0 pfc44 pfc43 0 pfc41 pfc40 fffff468h 00h bit position bit name function 4 pfc44 port function control specifies operation mode of p44 pin in control mode. 0: si1 input mode 1: rxd1 input mode 3 pfc43 port function control specifies operation mode of p43 pin in control mode. 0: so1 output mode 1: txd1 output mode 1 pfc41 port function control specifies operation mode of p41 pin in control mode. 0: si0 input mode 1: rxd0 input mode 0 pfc40 port function control specifies operation mode of p40 pin in control mode. 0: so0 output mode 1: txd0 output mode chapter 14 port functions user?s manual u14359ej5v1ud 489 14.3.6 port 5 port 5 is a 3-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset p5 ? ? ? ? ? p52 p51 p50 fffff40ah undefined bit position bit name function 2 to 0 p5n (n = 2 to 0) port 5 i/o port in addition to their function as port pins, the port 5 pins can also operate as the real-time puls e unit (rpu) i/o and external interrupt request inputs in the control mode. (1) operation in control mode port alternate function remark block type p50 intp030/ti030 external interrupt request input/ real-time pulse unit (rpu) input p51 intp031 external interrupt request input b port 5 p52 to03 real-time pulse unit (rpu) output a (2) i/o mode/control mode setting the port 5 i/o mode setting is performed by the port 5 mode register (pm5), and t he control mode setting is performed by the port 5 mode control register (pmc5). (a) port 5 mode register (pm5) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pm5 1 1 1 1 1 pm52 pm51 pm50 fffff42ah ffh bit position bit name function 2 to 0 pm5n (n = 2 to 0) port mode specifies input/output mode for p5n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 490 (b) port 5 mode control register (pmc5) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmc5 0 0 0 0 0 pmc52 pmc51 pmc50 fffff44ah 00h bit position bit name function 2 pmc52 port mode control specifies operation mode of p52 pin. 0: i/o port mode 1: to03 output mode 1 pmc51 port mode control specifies operation mode of p51 pin. 0: i/o port mode 1: external input request (intp031) input mode 0 pmc50 port mode control specifies operation mode of p50 pin. 0: i/o port mode 1: external interrupt request (intp030) input mode/ti030 input mode there is no register that switches between the external interrupt request (intp030) input mode and ti030 input mode. ? when the ti030 input mode is selected: mask the external interrupt request (intp030) or specify the ccc30 register as a compare register. ? when the external interrupt request (intp030) input mode (including timer capture input) is selected: set the eti3 bit of the tmcc31 register to 0. chapter 14 port functions user?s manual u14359ej5v1ud 491 14.3.7 port 7 port 7 is an 8-bit input-only port whose pins are fixed to input. 7 6 5 4 3 2 1 0 address after reset p7 p77 p76 p75 p74 p73 p72 p71 p70 fffff40eh undefined bit position bit name function 7 to 0 p7n (n = 7 to 0) port 7 input-only port in addition to their function as port pins, the port 7 pins can also operate as the analog inputs to the a/d converter in the control mode. (1) operation in control mode port alternate function remark block type port 7 p77 to p70 ani7 to ani0 analog input to a/d converter c caution when performing a/d conversion by selecting a pin from ani0 to ani7, the resolution of the a/d conversion may drop when port 7 (p7) is read during a/d conversion (adcs bit of adm0 register = 1). if a digital pulse is applied to the pin adjacent to the pin executing a/d conversion, the a/d conversion value may not be obt ained as expected due to coupl ing noise. do not apply a digital pulse to the pi n adjacent to the pin executing a/d conversion. chapter 14 port functions user?s manual u14359ej5v1ud 492 14.3.8 port al port al (pal) is a 16-bit i/o port that can be set to the input or output mode in 1-bit units. when the higher 8 bits of port al are used as port alh (palh) and the lower 8 bits as port all (pall), port al becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. 15 14 13 12 11 10 9 8 address after reset pal pal15 pal14 pal13 pal12 pal11 pal10 pal9 pal8 fffff001h undefined 7 6 5 4 3 2 1 0 address pal7 pal6 pal5 pal4 pal3 pal2 pal1 pal0 fffff000h bit position bit name function 15 to 0 paln (n = 15 to 0) port al i/o port in addition to their functions as port pins, in the control mode, the port al pins operate as an address bus for when the memory is externally expanded. (1) operation in control mode port alternate function remark block type port al pal15 to pal0 a15 to a0 address bus when memory expanded j (2) i/o mode/control mode setting the port al i/o mode setting is perform ed by the port al mode register (pmal), and control mode setting is performed by the port al mode control register (pmcal). (a) port al mode register (pmal) the port al mode register (pmal) c an be read/written in 16-bit units. if the higher 8 bits of pmal are used as port al m ode register h (pmalh), and the lower 8 bits as port al mode register l (pmall), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit units. 15 14 13 12 11 10 9 8 address after reset pmal pmal15 pmal14 pmal13 pmal12 pma l11 pmal10 pmal9 pmal8 fffff021h ffffh 7 6 5 4 3 2 1 0 address pmal7 pmal6 pmal5 pmal4 pmal3 pmal2 pmal1 pmal0 fffff020h bit position bit name function 15 to 0 pmaln (n = 15 to 0) port mode specifies input/output mode for paln pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 493 (b) port al mode control register (pmcal) the port al mode control register (pmcal ) can be read/written in 16-bit units. if the higher 8 bits of pmcal are used as port al mode control register h (pmcalh), and the lower 8 bits as port al mode control register l (pmcall), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit units. 15 14 13 12 11 10 9 8 address after reset note pmcal pmcal15 pmcal14 pmcal13 pmcal12 pmcal11 pmcal10 pmcal9 pmcal8 fffff041h ffffh/0000h 7 6 5 4 3 2 1 0 address pmcal7 pmcal6 pmcal5 pmcal4 pmcal3 pmcal2 pmcal1 pmcal0 fffff040h note in romless modes 0 and 1, and single-chip mode 1: ffffh in single-chip mode 0: 0000h bit position bit name function 15 to 0 pmcaln (n = 15 to 0) port mode control specifies operation mode of paln pin. 0: i/o port mode 1: a15 to a0 output mode chapter 14 port functions user?s manual u14359ej5v1ud 494 14.3.9 port ah port ah (pah) is a 10-bit i/o port that can be se t in the input or output mode in 1-bit units. when the higher 8 bits of port ah are used as port ahh (p ahh) and the lower 8 bits as port ahl (pahl), port ah becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. bits 15 to 10 of port ah (bits 7 to 2 of port ahh) are undefined. 15 14 13 12 11 10 9 8 address after reset pah ? ? ? ? ? ? pah9 pah8 fffff003h undefined 7 6 5 4 3 2 1 0 address pah7 pah6 pah5 pah4 pah3 pah2 pah1 pah0 fffff002h bit position bit name function 9 to 0 pahn (n = 9 to 0) port ah i/o port in addition to their functions as port pins, in the control mode, the port ah pins operate as an address bus for when the memory is externally expanded. (1) operation in control mode port alternate function pin name remark block type port ah pah9 to pah0 a25 to a16 address bus when memory expanded j chapter 14 port functions user?s manual u14359ej5v1ud 495 (2) i/o mode/control mode setting the port ah i/o mode setting is performed by the por t ah mode register (pmah), and the control mode setting is performed by the port ah mode control register (pmcah). (a) port ah mode register (pmah) the port ah mode register (pmah) c an be read/written in 16-bit units. if the higher 8 bits of pmah are used as port ah mo de register h (pmahh), and the lower 8 bits as port ah mode register l (pmahl), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit units. bits 15 to 10 of pmah (bits 7 to 2 of pmahh) are fixed to 1. 15 14 13 12 11 10 9 8 address after reset pmah 1 1 1 1 1 1 pmah9 pmah8 fffff023h ffffh 7 6 5 4 3 2 1 0 address pmah7 pmah6 pmah5 pmah4 pmah3 pmah2 pmah1 pmah0 fffff022h bit position bit name function 9 to 0 pmahn (n = 9 to 0) port mode specifies input/output mode for pahn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port ah mode control register (pmcah) the port ah mode control register (pmcah ) can be read/written in 16-bit units. if the higher 8 bits of pmcah are used as port ah mode control register h (pmcahh), and the lower 8 bits as port ah mode control register l (pmcahl), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit units. bits 15 to 10 of pmcah (bits 7 to 2 of pmcahh) are fixed to 0. 15 14 13 12 11 10 9 8 address after reset note pmcah 0 0 0 0 0 0 pmcah9 pmcah8 fffff043h 0000h/03ffh 7 6 5 4 3 2 1 0 address pmcah7 pmcah6 pmcah5 pmcah4 pm cah3 pmcah2 pmcah1 pmcah0 fffff042h note in romless modes 0 and 1, and single-chip mode 1: 03ffh in single-chip mode 0: 0000h bit position bit name function 9 to 0 pmcahn (n = 9 to 0) port mode control specifies operation mode of pahn pin. 0: i/o port mode 1: a25 to a16 output mode chapter 14 port functions user?s manual u14359ej5v1ud 496 14.3.10 port dl port dl (pdl) is a 16-bit i/o port that can be se t in the input or output mode in 1-bit units. when the higher 8 bits of port dl are used as port dlh (pdlh), and the lower 8 bits as port dll (pdll), port dl becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. 15 14 13 12 11 10 9 8 address after reset pdl pdl15 pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 fffff005h undefined 7 6 5 4 3 2 1 0 address pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 fffff004h bit position bit name function 15 to 0 pdln (n = 15 to 0) port dl i/o port in addition to their functions as port pins, in the control mode, the port dl pins operate as a data bus for when the memory is externally expanded. (1) operation in control mode port alternate function pin name remark block type port dl pdl15 to pdl0 d15 to d0 data bus when memory expanded o (2) i/o mode/control mode setting the port dl i/o mode setting is performed by the port dl mode register (pmdl) , and the control mode setting is performed by the port dl mode control register (pmcdl). (a) port dl mode register (pmdl) the port dl mode register (pmdl) can be read/written in 16-bit units. if the higher 8 bits of pmdl are used as port dl m ode register h (pmdlh), and the lower 8 bits as port dl mode register l (pmdll), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit units. 15 14 13 12 11 10 9 8 address after reset pmdl pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 fffff025h ffffh 7 6 5 4 3 2 1 0 address pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 fffff024h bit position bit name function 15 to 0 pmdln (n = 15 to 0) port mode specifies input/output mode for pdln pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 497 (b) port dl mode control register (pmcdl) the port dl mode control register (pmcdl ) can be read/written in 16-bit units. if the higher 8 bits of pmcdl are used as port dl mode control register h (pmcdlh), and the lower 8 bits as port dl mode control register l (pmcdll), these two 8-bi t port mode registers can be read/written in 8-bit or 1-bit units. 15 14 13 12 11 10 9 8 address after reset note pmcdl pmcdl15 pmcdl14 pmcdl13 pmcdl12 pmcdl11 pmcdl10 pmcdl9 pmcdl8 fffff045h ffffh/0000h 7 6 5 4 3 2 1 0 address pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 fffff044h note in romless modes 0 and 1, and single-chip mode 1: ffffh in single-chip mode 0: 0000h bit position bit name function 15 to 0 pmcdln (n = 15 to 0) port mode control specifies operation mode of pdln pin. 0: i/o port mode 1: d15 to d0 output mode caution the d8 to d15 pins are in the input status in romless mode 1. chapter 14 port functions user?s manual u14359ej5v1ud 498 14.3.11 port cs port cs is an 8-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset pcs pcs7 pcs6 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 fffff008h undefined bit position bit name function 7 to 0 pcsn (n = 7 to 0) port cs i/o port in addition to their function as port pins, in the control mo de, the port pins can also operate as the chip select signal outputs when memory is externally ex panded, the row address strobe signal outputs to dram, and the read/write strobe signal output to an external i/o. (1) operation in control mode port alternate function pin name remark block type pcs0 cs0 chip select signal output pcs1 cs1/ras1 chip select signal output/ row address signal output j pcs2 cs2/iowr chip select signal output/ write strobe signal output k pcs3 cs3/ras3 pcs4 cs4/ras4 chip select signal output/ row address signal output j pcs5 cs5/iord chip select signal output/ read strobe signal output k pcs6 cs6/ras6 chip select signal output/ row address signal output port cs pcs7 cs7 chip select signal output j chapter 14 port functions user?s manual u14359ej5v1ud 499 (2) i/o mode/control mode setting the port cs i/o mode setting is performed by the por t cs mode register (pmcs), and the control mode setting is performed by the port cs mode control register (pmccs) and the port cs function control register (pfccs). (a) port cs mode register (pmcs) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmcs pmcs7 pmcs6 pmcs5 pmcs4 pmcs 3 pmcs2 pmcs1 pmcs0 fffff028h ffh bit position bit name function 7 to 0 pmcsn (n = 7 to 0) port mode specifies input/output mode for pcsn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 500 (b) port cs mode control register (pmccs) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset note pmccs pmccs7 pmccs6 pmccs5 pmccs4 pmccs3 p mccs2 pmccs1 pmccs0 fffff048h 00h/ffh note in romless modes 0 and 1, and single-chip mode 1: ffh in single-chip mode 0: 00h bit position bit name function 7 pmccs7 port mode control specifies operation mode of pcs7 pin. 0: i/o port mode 1: cs7 output mode 6 pmccs6 port mode control specifies operation mode of pcs6 pin. 0: i/o port mode 1: cs6/ras6 output mode (cs6/ras6 signal automatically switched by accessing the targeted memory of each signal) 5 pmccs5 port mode control specifies operation mode of pcs5 pin. 0: i/o port mode 1: cs5 output mode/iord output mode 4 pmccs4 port mode control specifies operation mode of pcs4 pin. 0: i/o port mode 1: cs4/ras4 output mode (cs4/ras4 signal automatically switched by accessing the targeted memory of each signal) 3 pmccs3 port mode control specifies operation mode of pcs3 pin. 0: i/o port mode 1: cs3/ras3 output mode (cs3/ras3 signal automatically switched by accessing the targeted memory of each signal) 2 pmccs2 port mode control specifies operation mode of pcs2 pin. 0: i/o port mode 1: cs2 output mode/iowr output mode 1 pmccs1 port mode control specifies operation mode of pcs1 pin. 0: i/o port mode 1: cs1/ras1 output mode (cs1/ras1 signal automatically switched by accessing the targeted memory of each signal) 0 pmccs0 port mode control specifies operation mode of pcs0 pin. 0: i/o port mode 1: cs0 output mode chapter 14 port functions user?s manual u14359ej5v1ud 501 (c) port cs function control register (pfccs) this register can be read/written in 8-bit or 1-bit units. bits 7, 6, 4, 3, 1, and 0, however, are fixed to 0, so writing 1 to these bits is ignored. caution when the port mode is specified by th e port cs mode control register (pmccs), the pfccs setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfccs 0 0 pfccs5 0 0 pfccs2 0 0 fffff049h 00h bit position bit name function 5 pfccs5 port function control specifies operation mode of pcs5 pin in control mode. 0: cs5 output mode 1: iord output mode note 2 pfccs2 port function control specifies operation mode of pcs2 pin in control mode. 0: cs2 output mode 1: iowr output mode note note to output the iord and iowr sig nals during access to the external i/o other than by a dma flyby transfer, the ioen bit of the bcp register must be set. chapter 14 port functions user?s manual u14359ej5v1ud 502 14.3.12 port ct port ct is a 6-bit i/o port that can be set to input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset pct pct7 pct6 pct5 pct4 ? ? pct1 pct0 fffff00ah undefined bit position bit name function 7 to 4, 1, 0 pctn (n = 7 to 4, 1, 0) port ct i/o port in addition to their function as port pins, in the control mo de, the port ct pins operate as control signal outputs for when the memory is externally expanded. (1) operation in control mode port alternate function pin name remark block type pct0 lcas/lwr/ldqm column address signal output/ write strobe signal output/ output disable/write mask signal pct1 ucas/uwr/udqm column address signal output/ write strobe signal output/ output disable/write mask signal pct4 rd read strobe signal output pct5 we write enable signal output pct6 oe output enable signal output port ct pct7 bcyst bus cycle status signal output j (2) i/o mode/control mode setting the port ct i/o mode setting is performed by the po rt ct mode register (pmct), and the control mode setting is performed by the port ct mode control register (pmcct). (a) port ct mode register (pmct) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmct pmct7 pmct6 pmct5 pmct4 1 1 pmct1 pmct0 fffff02ah ffh bit position bit name function 7 to 4, 1, 0 pmctn (n = 7 to 4, 1, 0) port mode specifies input/output mode for pctn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 503 (b) port ct mode control register (pmcct) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset note pmcct pmcct7 pmcct6 pmcct5 pmcct4 0 0 pmcct1 pmcct0 fffff04ah 00h/f3h note in romless modes 0 and 1, and single-chip mode 1: f3h in single-chip mode 0: 00h bit position bit name function 7 pmcct7 port mode control specifies operation mode of pct7 pin. 0: i/o port mode 1: bcyst output mode 6 pmcct6 port mode control specifies operation mode of pct6 pin. 0: i/o port mode 1: oe output mode 5 pmcct5 port mode control specifies operation mode of pct5 pin. 0: i/o port mode 1: we output mode 4 pmcct4 port mode control specifies operation mode of pct4 pin. 0: i/o port mode 1: rd output mode 1 pmcct1 port mode control specifies operation mode of pct1 pin. 0: i/o port mode 1: ucas/uwr/udqm output mode (ucas/uwr/udqm signal automatically switched by accessing the targeted memory of each signal) 0 pmcct0 port mode control specifies operation mode of pct0 pin. 0: i/o port mode 1: lcas/lwr/ldqm output mode (lcas/lwr/ldqm signal automatically switched by accessing the targeted memory of each signal) chapter 14 port functions user?s manual u14359ej5v1ud 504 14.3.13 port cm port cm is a 6-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset pcm ? ? pcm5 pcm4 pcm3 pcm2 pcm1 pcm0 fffff00ch undefined bit position bit name function 5 to 0 pcmn (n = 5 to 0) port cm i/o port in addition to their function as port pins, in the control mode , the port cm pins operate as the wait insertion signal input, internal system clock output/bus clock output, bus hold control signal output, and refresh request signal output from dram. (1) operation in control mode port alternate function pin name remark block type pcm0 wait note wait insertion signal input d pcm1 clkout/busclk internal system clock output/bus clock output k pcm2 hldak bus hold acknowledge signal output j pcm3 hldrq note bus hold request signal input d pcm4 refrq refresh request signal output j port cm pcm5 selfref note self-refresh request signal input e note the default assumption of the wait, hldrq, and selfr ef signals is the control mode in romless modes 0 and 1, and single-chip mode 1. fix these pins to the inac tive level when they are not used. when these pins are used as port pins, they function in the control mode until they are set in the port mode by the port cm mode control register (pmccm). therefor e, be sure to set these pins to the inactive level until they are set in the port mode. (2) i/o mode/control mode setting the port cm i/o mode setting is performed by the port cm mode register (pmcm), and the c ontrol mode setting is performed by the port cm mode control regist er (pmccm) and the port cm function control register (pfccm). (a) port cm mode register (pmcm) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmcm 1 1 pmcm5 pmcm4 pmcm3 pmcm2 pmcm1 pmcm0 fffff02ch ffh bit position bit name function 5 to 0 pmcmn (n = 5 to 0) port mode specifies input/output mode for pcmn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 505 (b) port cm mode control register (pmccm) this register can be read/written in 8-bit or 1-bit units. caution if the mode of the pcm1/clkout/busclk pin is changed from th e i/o port mode to the clkout/busclk mode, a glitch may be generated in the clkout/busclk output immediately after the change. therefore, pull up the clkout/bus clk pin when using it. in the pll mode (cksel = 0), change the mode to the clkout/busclk mode at a multiple of 1 (ckdiv2 to ckdiv0 bits of ckc register = 000b). 7 6 5 4 3 2 1 0 address after reset note pmccm 0 0 pmccm5 pmccm4 pmccm3 pmccm2 pmccm1 pmccm0 fffff04ch 00h/3fh note in romless modes 0 and 1, and single-chip mode 1: 3fh in single-chip mode 0: 00h bit position bit name function 5 pmccm5 port mode control specifies operation mode of pcm5 pin. 0: i/o port mode 1: selfref input mode 4 pmccm4 port mode control specifies operation mode of pcm4 pin. 0: i/o port mode 1: refrq output mode 3 pmccm3 port mode control specifies operation mode of pcm3 pin. 0: i/o port mode 1: hldrq input mode 2 pmccm2 port mode control specifies operation mode of pcm2 pin. 0: i/o port mode 1: hldak output mode 1 pmccm1 port mode control specifies operation mode of pcm1 pin. 0: i/o port mode 1: clkout output mode/busclk output mode 0 pmccm0 port mode control specifies operation mode of pcm0 pin. 0: i/o port mode 1: wait input mode chapter 14 port functions user?s manual u14359ej5v1ud 506 (c) port cm function control register (pfccm) this register can be read/written in 8-bit or 1-bit units. bits 7 to 2 and 0, however, are fixed to 0, so writing 1 to these bits is ignored. to output the half clock of the internal system clock from the busclk pin, the bcp bit of the bcp register must be set to 1. if the bcp bit of the bcp register is set to 1 with the clkout output mode selected, the external bus operates at half the frequency of t he internal system clock frequency, but the clkout pin outputs the internal operating frequency. caution when the port mode is specified by th e port cm mode control register (pmccm), the pfccm setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfccm 0 0 0 0 0 0 pfccm1 0 fffff04dh 00h bit position bit name function 1 pfccm1 port function control specifies operation mode of pcm1 pin in control mode. 0: clkout output mode 1: busclk output mode chapter 14 port functions user?s manual u14359ej5v1ud 507 14.3.14 port cd port cd is a 4-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset pcd ? ? ? ? pcd3 pcd2 pcd1 pcd0 fffff00eh undefined bit position bit name function 3 to 0 pcdn (n = 3 to 0) port cd i/o port in addition to their function as port pins, the port cd pi ns operate as the clock enable signal output to sdram, synchronous clock output, column address strobe signal output, row address strobe signal output, and byte enable signal output to sdram upon byte access, in the control mode. (1) operation in control mode port alternate function pin name remark block type pcd0 sdcke clock enable signal output pcd1 sdclk synchronous clock output j pcd2 lbe/sdcas byte enable signal output/ column address strobe signal output port cd pcd3 ube/sdras byte enable signal output/ row address strobe signal output k (2) i/o mode/control mode setting the port cd i/o mode setting is performed by the por t cd mode register (pmcd), and the control mode setting is performed by the port cd mode control regist er (pmccd) and the port cd function control register (pfccd). (a) port cd mode register (pmcd) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmcd 1 1 1 1 pmcd3 pmcd2 pmcd1 pmcd0 fffff02eh ffh bit position bit name function 3 to 0 pmcdn (n = 3 to 0) port mode specifies input/output mode for pcdn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 508 (b) port cd mode control register (pmccd) this register can be read/written in 8-bit or 1-bit units. cautions 1. do not perform the sdclk and s dcke output mode setting simultaneously. be sure to perform the sdclk output mode setting before the sdcke output mode setting. 2. when in single-chip mode 1, and in romless modes 0 and 1, bits 1 and 0 of the pmccd register become sdclk output m ode and sdcke output mode after the reset is released, however, bits 3 and 2 become ube output mode and lbe output mode. when using sdram be sure to set the sdras output mode and sdcas output mode using the pfccd register. 7 6 5 4 3 2 1 0 address after reset note pmccd 0 0 0 0 pmccd3 pmccd2 pmccd1 pmccd0 fffff04eh 00h/0fh note in romless modes 0 and 1, and single-chip mode 1: 0fh in single-chip mode 0: 00h bit position bit name function 3 pmccd3 port mode control specifies operation mode of pcd3 pin. 0: i/o port mode 1: ube/sdras output mode 2 pmccd2 port mode control specifies operation mode of pcd2 pin. 0: i/o port mode 1: lbe/sdcas output mode 1 pmccd1 port mode control specifies operation mode of pcd1 pin. 0: i/o port mode 1: sdclk output mode 0 pmccd0 port mode control specifies operation mode of pcd0 pin. 0: i/o port mode 1: sdcke output mode chapter 14 port functions user?s manual u14359ej5v1ud 509 (c) port cd function control register (pfccd) this register can be read/written in 8-bit or 1-bit units. bits 7 to 4, 1, and 0, however, are fixed to 0, so writing 1 to these bits is ignored. caution when the port mode is specified by the port cd mode control register (pmccd), the pfccd setting becomes invalid. 7 6 5 4 3 2 1 0 address after reset pfccd 0 0 0 0 pfccd3 pfccd2 0 0 fffff04fh 00h bit position bit name function 3 pfccd3 port function control specifies operation mode of pcd3 pin in control mode. 0: ube output mode 1: sdras output mode 2 pfccd2 port function control specifies operation mode of pcd2 pin in control mode. 0: lbe output mode 1: sdcas output mode chapter 14 port functions user?s manual u14359ej5v1ud 510 14.3.15 port bd port bd is a 4-bit i/o port that can be set to the input or output mode in 1-bit units. 7 6 5 4 3 2 1 0 address after reset pbd ? ? ? ? pbd3 pbd2 pbd1 pbd0 fffff012h undefined bit position bit name function 3 to 0 pbdn (n = 3 to 0) port bd i/o port in addition to their function as port pins, the port bd pins operate as the dma acknowledge signal outputs in the control mode. (1) operation in control mode port alternate function pin name remark block type port bd pbd0 to pbd3 dmaak0 to dmaak3 dma acknowledge signal output j (2) i/o mode/control mode setting the port bd i/o mode setting is performed by the por t bd mode register (pmbd), and the control mode setting is performed by the port bd mode control register (pmcbd). (a) port bd mode register (pmbd) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmbd 1 1 1 1 pmbd3 pmbd2 pmbd1 pmbd0 fffff032h ffh bit position bit name function 3 to 0 pmbdn (n = 3 to 0) port mode specifies input/output mode for pbdn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions user?s manual u14359ej5v1ud 511 (b) port bd mode control register (pmcbd) this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 address after reset pmcbd 0 0 0 0 pmcbd3 pmcbd2 pmcbd1 pmcbd0 fffff052h 00h bit position bit name function 3 to 0 pmcbdn (n = 3 to 0) port mode control specifies operation mode of pbdn pin. 0: i/o port mode 1: dmaakn output mode 14.4 setting to use alternate function of port pin set the port pins as shown in table 14-1 to use their alternate function. 512 user?s manual u14359ej5v1ud chapter 14 port functions table 14-1. settings when port pins are used for alternate functions (1/8) alternate function pin name function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) p00 pwm0 output p00 = setting not required pm00 = setting not required pmc00 = 1 ? p01 intp000 note 1 input p01 = setting not required pm01 = setting not required pmc01 = 1 ? ies0001 (sesc0), ies0000 (sesc0) ti000 note 1 input p01 = setting not required pm01 = setting not required pmc01 = 1 ? tes01 (sesc0), tes00 (sesc0) p02 intp001 input p02 = setting not required pm02 = setting not required pmc02 = 1 ? ies0011 (sesc0), ies0010 (sesc0) p03 to00 output p03 = setting not required pm03 = setting not required pmc03 = 1 ? p04 intp100 input p04 = setting not required pm04 = setting not required pmc04 = 1 pfc04 = 0 es1001 (intm1), es1000 (intm1) dmarq0 input p04 = setting not required pm04 = setting not required pmc04 = 1 pfc04 = 1 p05 intp101 input p05 = setting not required pm05 = setting not required pmc05 = 1 pfc05 = 0 es1011 (intm1), es1010 (intm1) dmarq1 input p05 = setting not required pm05 = setting not required pmc05 = 1 pfc05 = 1 p06 intp102 input p06 = setting not required pm06 = setting not required pmc06 = 1 pfc06 = 0 es1021 (intm1), es1020 (intm1) dmarq2 input p06 = setting not required pm06 = setting not required pmc06 = 1 pfc06 = 1 p07 intp103 input p07 = setting not required pm07 = setting not required pmc07 = 1 pfc07 = 0 es1031 (intm1), es1030 (intm1) dmarq3 input p07 = setting not required pm07 = setting not required pmc07 = 1 pfc07 = 1 p10 pwm1 output p10 = setting not required pm10 = setting not required pmc10 = 1 ? p11 intp010 note 2 input p11 = setting not required pm11 = setting not required pmc11 = 1 ? ies0101 (sesc1), ies0100 (sesc1) ti010 note 2 input p11 = setting not required pm11 = setting not required pmc11 = 1 ? tes11 (sesc1), tes10 (sesc1) p12 intp011 input p12 = setting not required pm12 = setting not required pmc12 = 1 ? ies0111 (sesc1), ies0110 (sesc1) p13 to01 output p13 = setting not required pm13 = setting not required pmc13 = 1 ? notes 1. there is no register that selects the in tp000 pin or ti000 pin. to use the intp000 or ti000 pin, make the following setting. ? to use intp000 pin: clear the eti0 bit of the tmcc01 register to 0. ? to use ti000 pin: mask the intp000 interrupt request or set the ccc00 register as a compare register. 2. there is no register that selects the in tp010 pin or ti010 pin. to use the intp010 or ti010 pin, make the following setting. ? to use intp010 pin: clear the eti1 bit of the tmcc11 register to 0. ? to use ti010 pin: mask the intp010 interrupt request or set the ccc10 register as a compare register. chapter 14 port functions user?s manual u14359ej5v1ud 513 table 14-1. settings when port pins are used for alternate functions (2/8) alternate function pin name function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) p20 nmi input p20 = setting not required pm20 = setting not required pmc20 = 1 ? p21 intp020 note input p21 = setting not required pm21 = setting not required pmc21 = 1 ? ies0201 (sesc2 , ies0200 (sesc2) ti020 note input p21 = setting not required pm21 = setting not required pmc21 = 1 ? tes21 (sesc2), tes20 (sesc2) p22 intp021 input p22 = setting not required pm22 = setting not required pmc22 = 1 ? ies0211 (sesc2), ies0210 (sesc2) p23 to02 output p23 = setting not required pm23 = setting not required pmc23 = 1 ? p24 intp110 input p24 = setting not required pm24 = setting not required pmc24 = 1 pfc24 = 0 es1101 (intm2), es1100 (intm2) tc0 output p24 = setting not required pm24 = setting not required pmc24 = 1 pfc24 = 1 p25 intp111 input p25 = setting not required pm25 = setting not required pmc25 = 1 pfc25 = 0 es1111 (intm2), es1110 (intm2) tc1 output p25 = setting not required pm25 = setting not required pmc25 = 1 pfc25 = 1 p26 intp112 input p26 = setting not required pm26 = setting not required pmc26 = 1 pfc26 = 0 es1121 (intm2), es1120 (intm2) tc2 output p26 = setting not required pm26 = setting not required pmc26 = 1 pfc26 = 1 p27 intp113 input p27 = setting not required pm27 = setting not required pmc27 = 1 pfc27 = 0 es1131 (intm2), es1130 (intm2) tc3 output p27 = setting not required pm27 = setting not required pmc27 = 1 pfc27 = 1 p30 so2 output p30 = setting not required pm30 = setting not required pmc30 = 1 pfc30 = 0 intp130 input p30 = setting not required pm30 = setting not required pmc30 = 1 pfc30 = 1 es1301 (intm4), es1300 (intm4) p31 si2 input p31 = setting not required pm31 = setting not required pmc31 = 1 pfc31 = 0 intp131 input p31 = setting not required pm31 = setting not required pmc31 = 1 pfc31 = 1 es1311 (intm4), es1310 (intm4) p32 sck2 i/o p32 = setting not required pm32 = setting not required pmc32 = 1 pfc32 = 0 intp132 input p32 = setting not required pm32 = setting not required pmc32 = 1 pfc32 = 1 es1321 (intm4), es1320 (intm4) note there is no register that selects the in tp020 pin or ti020 pin. to use the intp020 or ti020 pin, make the following setting. ? to use intp020 pin: clear the eti2 bit of the tmcc21 register to 0. ? to use ti020 pin: mask the intp020 interrupt request or set the ccc20 register as a compare register. 514 user?s manual u14359ej5v1ud chapter 14 port functions table 14-1. settings when port pins are used for alternate functions (3/8) alternate function pin name function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) p30 txd2 output p33 = setting not required pm33 = setting not required pmc33 = 1 pfc33 = 0 intp133 input p33 = setting not required pm33 = setting not required pmc33 = 1 pfc33 = 1 es1331 (intm4), es1330 (intm4) p34 rxd2 input p34 = setting not required pm34 = setting not required pmc34 = 1 pfc34 = 0 intp120 input p34 = setting not required pm24 = setting not required pmc34 = 1 pfc34 = 1 es1201 (intm3), es1200 (intm3) p35 intp121 input p35 = setting not required pm35 = setting not required pmc35 = 1 ? es1211 (intm3), es1210 (intm3) p36 intp122 input p36 = setting not required pm36 = setting not required pmc36 = 1 ? es1221 (intm3), es1220 (intm3) p37 intp123 note input p37 = setting not required pm37 = setting not required pmc37 = 1 ? es1231 (intm3), es1230 (intm3) adtrg note input p37 = setting not required pm37 = setting not required pmc37 = 1 ? es1231 (intm3), es1230 (intm3) p40 so0 output p40 = setting not required pm40 = setting not required pmc40 = 1 pfc40 = 0 txd0 output p40 = setting not required pm40 = setting not required pmc40 = 1 pfc40 = 1 p41 si0 input p41 = setting not required pm41 = setting not required pmc41 = 1 pfc41 = 0 rxd0 input p41 = setting not required pm41 = setting not required pmc41 = 1 pfc41 = 1 p42 sck0 i/o p42 = setting not required pm42 = setting not required pmc42 = 1 ? p43 so1 output p43 = setting not required pm43 = setting not required pmc43 = 1 pfc43 = 0 txd1 output p43 = setting not required pm43 = setting not required pmc43 = 1 pfc43 = 1 p44 si1 input p44 = setting not required pm44 = setting not required pmc44 = 1 pfc44 = 0 rxd1 input p44 = setting not required pm44 = setting not required pmc44 = 1 pfc44 = 1 p45 sck1 i/o p45 = setting not required pm45 = setting not required pmc45 = 1 ? note there is no register that selects the in tp123 pin or adtrg pin. to use the intp123 or adtrg pin, make the following setting. ? to use intp123 pin: set a mode other than the ex ternal trigger mode by using the adm1 register. ? to use adtrg pin: set the external trigger mode by using the adm1 register. chapter 14 port functions user?s manual u14359ej5v1ud 515 table 14-1. settings when port pins are used for alternate functions (4/8) alternate function pin name function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) p50 intp030 note input p50 = setting not required pm50 = setting not required pmc50 = 1 ? ies0301 (sesc3), ies0300 (sesc3) ti030 note input p50 = setting not required pm50 = setting not required pmc50 = 1 ? tes31 (sesc3), tes30 (sesc3) p51 intp031 input p51 = setting not required pm51 = setting not required pmc51 = 1 ? ies0311 (sesc3), ies0310 (sesc3) p52 to03 output p52 = setting not required pm52 = setting not required pmc52 = 1 ? p70 ani0 input p70 = setting not required ? ? ? p71 ani1 input p71 = setting not required ? ? ? p72 ani2 input p72 = setting not required ? ? ? p73 ani3 input p73 = setting not required ? ? ? p74 ani4 input p74 = setting not required ? ? ? p75 ani5 input p75 = setting not required ? ? ? p76 ani6 input p76 = setting not required ? ? ? p77 ani7 input p77 = setting not required ? ? ? pal0 a0 output pal0 = setting not required pm42 = setting not required pmcal0 = 1 ? pal1 a1 output pal1 = setting not required pm43 = setting not required pmcal1 = 1 ? pal2 a2 output pal2 = setting not required pm43 = setting not required pmcal2 = 1 ? pal3 a3 output pal3 = setting not required pm44 = setting not required pmcal3 = 1 ? pal4 a4 output pal4 = setting not required pm44 = setting not required pmcal4 = 1 ? pal5 a5 output pal5 = setting not required pm45 = setting not required pmcal5 = 1 ? note there is no register that selects the in tp030 pin or ti030 pin. to use the intp030 or ti030 pin, make the following setting. ? to use intp030 pin: clear the eti3 bit of the tmcc31 register to 0. ? to use ti030 pin: mask the intp030 interrupt request or set the ccc30 register as a compare register. 516 user?s manual u14359ej5v1ud chapter 14 port functions table 14-1. settings when port pins are used for alternate functions (5/8) alternate function pin name function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) pal6 a6 output pal6 = setting not required pmal6 = setting not required pmcal6 = 1 ? pal7 a7 output pal7 = setting not required pmal7 = setting not required pmcal7 = 1 ? pal8 a8 output pal8 = setting not required pmal8 = setting not required pmcal8 = 1 ? pal9 a9 output pal9 = setting not required pmal9 = setting not required pmcal9 = 1 ? pal10 a10 output pal10 = setting not required pmal10 = setting not required pmcal10 = 1 ? pal11 a11 output pal11 = setting not required pmal11 = setting not required pmcal11 = 1 ? pal12 a12 output pal12 = setting not required pmal12 = setting not required pmcal12 = 1 ? pal13 a13 output pal13 = setting not required pmal13 = setting not required pmcal13 = 1 ? pal14 a14 output pal14 = setting not required pmal14 = setting not required pmcal14 = 1 ? pal15 a15 output pal15 = setting not required pmal15 = setting not required pmcal5 = 1 ? pah0 a16 output pah0 = setting not required pmah0 = setting not required pmcah0 = 1 ? pah1 a17 output pah1 = setting not required pmah1 = setting not required pmcah1 = 1 ? pah2 a18 output pah2 = setting not required pmah2 = setting not required pmcah2 = 1 ? pah3 a19 output pah3 = setting not required pmah3 = setting not required pmcah3 = 1 ? pal4 a20 output pah4 = setting not required pmah4 = setting not required pmcah4 = 1 ? pal5 a21 output pah5 = setting not required pmah5 = setting not required pmcah5 = 1 ? pal6 a22 output pah6 = setting not required pmah6 = setting not required pmcah6 = 1 ? chapter 14 port functions user?s manual u14359ej5v1ud 517 table 14-1. settings when port pins are used for alternate functions (6/8) alternate function pin name function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) pah7 a23 output pah7 = setting not required pmah7 = setting not required pmcah7 = 1 ? pah8 a24 output pah8 = setting not required pmah8 = setting not required pmcah8 = 1 ? pah9 a25 output pah9 = setting not required pmah9 = setting not required pmcah9 = 1 ? pdl0 d0 i/o pdl0 = setting not required pmdl0 = setting not required pmcdl0 = 1 ? pdl1 d1 i/o pdl1 = setting not required pmdl1 = setting not required pmcdl1 = 1 ? pdl2 d2 i/o pdl2 = setting not required pmdl2 = setting not required pmcdl2 = 1 ? pdl3 d3 i/o pdl3 = setting not required pmdl3 = setting not required pmcdl3 = 1 ? pdl4 d4 i/o pdl4 = setting not required pmdl4 = setting not required pmcdl4 = 1 ? pdl5 d5 i/o pdl5 = setting not required pmdl5 = setting not required pmcdl5 = 1 ? pdl6 d6 i/o pdl6 = setting not required pmdl6 = setting not required pmcdl6 = 1 ? pdl7 d7 i/o pdl7 = setting not required pmdl7 = setting not required pmcdl7 = 1 ? pdl8 d8 i/o pdl8 = setting not required pmdl8 = setting not required pmcdl8 = 1 ? pdl9 d9 i/o pdl9 = setting not required pmdl9 = setting not required pmcdl9 = 1 ? pdl10 d10 i/o pdl10 = setting not required pmdl10 = setting not required pmcdl10 = 1 ? pdl11 d11 i/o pdl11 = setting not required pmdl11 = setting not required pmcdl11 = 1 ? pdl12 d12 i/o pdl12 = setting not required pmdl12 = setting not required pmcdl12 = 1 ? pdl13 d13 i/o pdl13 = setting not required pmdl13 = setting not required pmcdl13 = 1 ? pdl14 d14 i/o pdl14 = setting not required pmdl14 = setting not required pmcdl14 = 1 ? pdl15 d15 i/o pdl15 = setting not required pmdl15 = setting not required pmcdl15 = 1 ? 518 user?s manual u14359ej5v1ud chapter 14 port functions table 14-1. settings when port pins are used for alternate functions (7/8) alternate function pin name function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) pcs0 cs0 output pcs0 = setting not required pmcs0 = setting not required pmccs0 = 1 ? pcs1 cs1 note 1 output pcs1 = setting not required pmcs1 = setting not required pmccs1 = 1 ? ras1 note 1 output pcs1 = setting not required pmcs1 = setting not required pmccs1 = 1 ? pcs2 cs2 output pcs2 = setting not required pmcs2 = setting not required pmccs2 = 1 pfccs2 = 0 iowr output pcs2 = setting not required pmcs 2= setting not required pmccs2 = 1 pfccs2 = 1 pcs3 cs3 note 1 output pcs3 = setting not required pmcs3 = setting not required pmccs3 = 1 ? ras3 note 1 output pcs3 = setting not required pmcs3 = setting not required pmccs3 = 1 ? pcs4 cs4 note 1 output pcs4 = setting not required pmcs4 = setting not required pmccs4= 1 ? ras4 note 1 output pcs4 = setting not required pmcs4 = setting not required pmccs4 = 1 ? pcs5 cs5 output pcs5 = setting not required pmcs5 = setting not required pmccs5 = 1 pfccs5 = 0 iord output pcs5 = setting not required pmcs5 = setting not required pmccs5 = 1 pfccs5 = 1 pcs6 cs6 note 1 output pcs6 = setting not required pmcs6 = setting not required pmccs6 = 1 ? ras6 note 1 output pcs6 = setting not required pmcs6= setting not required pmccs6= 1 ? pcs7 cs7 output pcs7 = setting not required pmcs7 = setting not required pmcct7 = 1 ? pct0 lcas note 2 output pct0 = setting not required pmct0 = setting not required pmcct0 = 1 ? lwr note 2 output pct0 = setting not required pmct0 = setting not required pmcct0 = 1 ? ldqm note 2 output pct0 = setting not required pmct0 = setting not required pmcct0 = 1 ? pct1 ucas note 2 output pct1 = setting not required pmct1 = setting not required pmcct1 = 1 ? uwr note 2 output pct1 = setting not required pmct1 = setting not required pmcct1 = 1 ? udqm note 2 output pct1 = setting not required pmct1 = setting not required pmcct1 = 1 ? notes 1. the csm or rasm signal is automatically se lected when the memory to be controlled by each signal is accessed (m = 1, 3, 4, or 6). 2. the kcas, kwr, or kdqm signal is automatically selected when the memory to be controlled by each signal is accessed (k = l or u). chapter 14 port functions user?s manual u14359ej5v1ud 519 table 14-1. settings when port pins are used for alternate functions (8/8) alternate function pin name function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) pct4 rd output pct4 = setting not required pmct4 = setting not required pmcct4 = 1 ? pct5 we output pct5 = setting not requir ed pmct5 = setting not required pmcct5 = 1 ? pct6 oe output pct6 = setting not required pmct6 = setting not required pmcct6 = 1 ? pct7 bcyst output pct7 = setting not requi red pmct7 = setting not required pmcct7 = 1 ? pcm0 wait input pcm0 = setting not required pmcm0 = setting not required pmccm0 = 1 ? pcm1 clkout output pcm1 = setting not required pmcm1 = setting not required pmccm1= 1 pfccm1 = 0 busclk output pcm1 = setting not required pmcm1 = setting not required pmccm1 = 1 pfccm1 = 1 pcm2 hldak output pcm2 = setting not required pmcm2 = setting not required pmccm2= 1 ? pcm3 hldrq input pcm3 = setting not required pmcm3 = setting not required pmccm3 = 1 ? pcm4 refrq output pcm4 = setting not required pmcm4 = setting not required pmccm4 = 1 ? pcm5 selfref input pcm5 = setting not required pmcm5 = setting not required pmccm5 = 1 ? pcd0 sdcke output pcd0 = setting not required pmcd0 = setting not required pmccd0 = 1 ? pcd1 sdclk output pcd1 = setting not required pmcd1= setting not required pmccd1 = 1 pcd2 lbe output pcd2 = setting not required pmcd2 = setting not required pmccd2 = 1 pfccd2 = 0 sdcas output pcd2 = setting not required pmcd2 = setting not required pmccd2 = 1 pfccd2 = 1 pcd3 ube output pcd3 = setting not required pmcd3 = setting not required pmccd3 = 1 pfccd2 = 0 sdras output pcd3 = setting not required pmcd3 = setting not required pmccd3 = 1 pfccd2 = 1 pbd0 dmaak0 output pbd0 = setting not required pmbd0 = setting not required pmcbd0 = 1 ? pbd1 dmaak1 output pbd1 = setting not required pmbd1 = setting not required pmcbd1 = 1 ? pbd2 dmaak2 output pbd2 = setting not required pmbd2 = setting not required pmcbd2 = 1 ? pbd3 dmaak3 output pbd3 = setting not required pmbd3 = setting not required pmcbd3 = 1 ? chapter 14 port functions user?s manual u14359ej5v1ud 520 14.5 operation of port function the operation of a port differs depending on whether the port is in the input or output mode, as described below. 14.5.1 writing data to i/o port (1) in output mode a value can be written to the output la tch (pn) by writing data to the port n register (pn). the contents of the output latch are output from the pin. once data has been written to the output latch, it is retained until new data is wri tten to the output latch. (2) in input mode a value can be written to the output latch (pn) by writi ng data to the port n register (pn). because the output buffer is off, however, the stat us of the pin does not change. once data has been written to the output latch, it is retained until new data is wri tten to the output latch. caution a bit manipulation instruction (clr1, set 1, not1) manipulates 1 bit but accesses a port in 8-bit units. the contents of the output latch of a pin set in the input mode, in addition to the bit to be manipulated, are overwritten to the current status of the input pin and become undefined in a port that has a mixture of input and output bits. 14.5.2 reading data from i/o port (1) in output mode the contents of the output latch (pn) c an be read by reading data to the port n register (pn). the contents of the output latch do not change. (2) in input mode the status of the pin can be read by reading data to the port n regist er (pn). the contents of the output latch (pn) do not change. 14.5.3 output status of alternate function in control mode the status of a port pin is not dependent upon the setting of the pmcn register, but can be read by setting the port n mode register (pmn) to the input mode. when the pmn regi ster is set to the output m ode, the value of the port n register (pn) can be read in the port mode and the output st atus of the alternate function can be read in the control mode. chapter 14 port functions user?s manual u14359ej5v1ud 521 14.6 cautions (1) procedure to change mode from port mode to control mode change the mode of a port pin that f unctions as an output or i/o pin in the control mode to the control mode using the following procedure (except port 7). <1> set the inactive level of the signal to be output in the control mode to the corresponding bit of port n (n = 0 to 5, al, ah, dl, cs, ct, cm, cd, bd). <2> select the control mode by using the port n mode control register (pmcn). if <1> is not performed, the contents of port n may be momentarily output when the mode is changed from the port mode to the control mode. (2) manipulating port with bit manipul ation instruction (set1, clr1, not1) to manipulate a port by using a bit manipulation inst ruction (set1, clr1, not1), read the byte data of the port, process the data of only the bit to be manipulated, and write back the converted byte data to the port. the output latch of the input pin of a port that has a mixture of input/ output pins becomes undefined because the contents of the output latc h are overwritten to the other bits in addition to the one to be manipulated (in the input mode, however, the pin status does no t change because the output buffer is off). to change the port mode from input to output mode, ther efore, set an expected output value to the bit to be manipulated, and then change the mode to the output mode. the same appl ies to a port that has a control mode and output pins. user?s manual u14359ej5v1ud 522 chapter 15 reset functions when a low-level signal is input to the reset pin, a system reset is effected and the hardware is initialized. when the reset signal level changes from low to high, the reset state is rel eased and cpu starts program execution. register contents must be in itialized as required in the program. 15.1 features the reset pin (reset) incorpor ates a noise elim inator that uses analog delay ( ? 60 ns) to prevent malfunction due to noise. 15.2 pin functions during a system reset, most pins (all but the clkout note , reset, x2, v dd , v ss , cv dd , cv ss , av dd /av ref , and av ss pins) enter the high-impedance state. therefore, when memory is connec ted externally, a pull-up or pull-down resistor must be connected to the spec ified pins of ports al, ah, dl, cs, ct, cm, cd, and bd. if no resistor is connected, external memory may be destroyed when these pins enter the high-impedance state. for the same reason, the output pins of the on-chip peripheral i/o functi ons and other output ports should be handled in the same manner. note in romless modes 0 and 1, and in single-chip mode 1, the clkout signal is output even during reset. in single-chip mode 0, the clkout signal is not output until the pmccm register is set. the operation status of eac h pin during reset is shown below (table 15-1). table 15-1. operation status of each pin during reset pin state pin name single-chip mode 0 single-chip mode 1 romless mode 0 romless mode 1 a0 to a15, a16 to a25, d0 to d15, cs0 to cs7, ras1, ras3, ras4, ras6, lwr, uwr, lcas, ucas, ldqm, udqm, rd, we, oe, bcyst, wait, hldak, hldrq, refreq, selfref, sdcke, sdclk, lbe, ube, sdcas, sdras (port mode) high impedance clkout (port mode) operating ports 0 to 5, 7, bd (input) port pin ports al, ah, dl, cm, ct, cs, cd (input) (control mode) chapter 15 reset functions user?s manual u14359ej5v1ud 523 (1) acknowledging the reset signal reset (input) internal system reset signal eliminated as noise ?? reset acknowledgement reset release analog delay analog delay analog delay note note the internal system reset signal continues in the active state for at least 4 system clock cycles after reset clear timing by the reset signal. (2) reset when turning on the power in a reset operation when the power is turned on, because of the low-level width of the reset signal, it is necessary to secure the oscillation stabilization time between when the power is turned on and when the reset is acknowledged. reset (input) v dd ? reset release analog delay oscillation stabilization time chapter 15 reset functions user?s manual u14359ej5v1ud 524 15.3 initialization initialize the contents of each regist er as necessary while programming. the initial values of the cpu, inte rnal ram, and on-chip peripheral i/o afte r a reset are shown in table 15-2. table 15-2. initial value of cpu, internal ram, and on-chip periphera l i/o after reset (1/3) internal hardware register name initial value after reset general-purpose register (r0) 00000000h general-purpose registers (r1 to r31) undefined program registers program counter (pc) 00000000h status saving registers during in terrupt (eipc, eipsw) undefined status saving registers during nmi (fepc, fepsw) undefined interrupt source register (ecr) 00000000h program status word (psw) 00000020h status saving registers during callt execution (ctpc, ctpsw) undefined status saving registers during exception/debug trap (dbpc, dbpsw) undefined cpu system registers callt base pointer (ctbp) undefined internal ram ? undefined ports (p0 to p5, p7, pal, pah, pdl, pcs, pct, pcm, pcd, pbd) undefined mode registers (pm0 to pm5, pmcs, pmct, pmcm, pmcd, pmbd) ffh mode registers (pmal, pmah, pmdl) ffffh mode control registers (pmc0, pmc1, pmc3 to pmc5, pmcbd) 00h mode control register (pmc2) 01h mode control registers (pmcal, pmcdl) 0000h/ffffh mode control register (pmcah) 0000h/03ffh mode control register (pmccs) 00h/ffh mode control register (pmcct) 00h/f3h mode control register (pmccm) 00h/3fh mode control register (pmccd) 00h/0fh port functions function control registers (pfc0, pfc2 to pfc4, pfccs, pfccm, pfccd) 00h timer cn (tmcn) (n = 0 to 3) 0000h capture/compare registers cn0 and cn1 (cccn0 and cccn1) (n = 0 to 3) 0000h timer mode control register cn0 (tmccn0) (n = 0 to 3) 00h timer mode control register cn1 (tmccn1) (n = 0 to 3) 20h timer dn (tmdn) (n = 0 to 3) 0000h compare register (cmdn) (n = 0 to 3) 0000h on-chip peripheral i/o timer/counter functions timer mode control register dn (n = 0 to 3) 00h chapter 15 reset functions user?s manual u14359ej5v1ud 525 table 15-2. initial value of cpu, internal ram, and on-chip periphera l i/o after reset (2/3) internal hardware register name initial value after reset clocked serial interfac e mode register n (csimn) (n = 0 to 2) 00h clocked serial interface clock select register n (csicn) (n = 0 to 2) 00h clocked serial interface transmit buffer register n (sotbn) (n = 0 to 2) 00h serial i/o shift register n (sion) (n = 0 to 2) 00h receive-only serial i/o shift register n (sioen) (n = 0 to 2) 00h receive buffer register n (rxbn) (n = 0 to 2) ffh transmit buffer register n (txbn) (n = 0 to 2) ffh asynchronous serial interface mode register n (asimn) (n = 0 to 2) 01h asynchronous serial interface status re gister n (asisn) (n = 0 to 2) 00h asynchronous serial interface tran smit status register n (asifn) (n = 0 to 2) 00h clock select register n (cksrn) (n = 0 to 2) 00h serial interface functions baud rate generator control register n (brgcn) (n = 0 to 2) ffh a/d converter mode registers 0 and 2 (adm0 and adm2) 00h a/d converter mode register 1 (adm1) 07h a/d conversion result register n (10 bits) (n = 0 to 7) 0000h a/d converter a/d conversion result register nh (8 bits) (n = 0 to 7) 00h pwm control register n (pwmcn) (n = 0, 1) 40h pwm pwm buffer register n (pwmbn) (n = 0, 1) 0000h in-service priority register (ispr) 00h external interrupt mode register n (intmn) (n = 0 to 4) 00h interrupt mask register n (imrn) (n = 0 to 3) ffffh valid edge select register cn (sescn) (n = 0 to 3) 00h interrupt/exceptio n control functions interrupt control registers (ovic00 to ovic03, p00ic0, p00ic1, p01ic0, p01ic1, p02ic0, p02ic1, p03ic0, p03ic1, p10ic0 to p10ic3, p11ic0 to p11ic3, p12ic0 to p12ic3, p13ic0 to p13ic3, cmicd0 to cmicd3, dmaic0 to dmaic3, csiic0 to csiic2, seic0 to seic2, sric0 to sric2, stic0 to stic2, adic) 47h page rom configuration register (prc) 7000h dram configuration register n (scrn) (n = 1, 3, 4, 6) 3fc1h sdram configuration register n (scrn) (n = 1, 3, 4, 6) 0000h refresh control register n (rfsn) (n = 1, 3, 4, 6) 0000h sdram refresh control register n (rfsn) (n = 1, 3, 4, 6) 0000h on-chip peripheral i/o memory control functions refresh wait control register (rwc) 00h chapter 15 reset functions user?s manual u14359ej5v1ud 526 table 15-2. initial value of cpu, internal ram, and on-chip periphera l i/o after reset (3/3) internal hardware register name initial value after reset dma addressing control register n (dadcn) (n = 0 to 3) 0000h dma byte count register n (dbcn) (n = 0 to 3) undefined dma channel control register n (dchcn) (n = 0 to 3) 00h dma destination address register nh (ddanh) (n = 0 to 3) undefined dma destination address register nl (ddanl) (n = 0 to 3) undefined dma disable status register (ddis) 00h dma restart register (drst) 00h dma source address register nh (dsanh) (n = 0 to 3) undefined dma source address register nl (dsanl) (n = 0 to 3) undefined dma terminal count output control register (dtoc) 01h dma functions dma trigger source register n (dtfrn) (n = 0 to 3) 00h address setup wait control register (asc) ffffh bus cycle control register (bcc) ffffh bus cycle period control register (bcp) 00h bus cycle type configuration regi ster n (bctn) (n = 0, 1) 8888h endian configuration register (bec) 0000h bus size configuration register (bsc) 0000h/5555h chip area select control register n (cscn) (n = 0, 1) 2c11h bus control functions data wait control register n (dwcn) (n = 0, 1) 7777h command register (prcmd) undefined power-save control register (psc) 00h clock control register (ckc) 00h power-save control functions power-save mode register (psmr) 00h peripheral command register (phcmd) undefined peripheral status register (phs) 00h system wait control register (vswc) 77h flash programming mode control register (flpmc) 08h/0ch/00h on-chip peripheral i/o system control lock register (lockr) 0 h caution ?undefined? in the above table is undefined after power-on-r eset, or undefined as a result of data destruction when reset is input and the data write timing has been synchronized. for other reset signals, data is held in the same stat e it was in before the reset operation. 527 user?s manual u14359ej5v1ud chapter 16 flash memory ( pd70f3107a) the pd70f3107a is the flash memory version of the v850e/ma1 and it has an on-chip 256 kb flash memory configured as two 128 kb areas. caution there are differences in noise immunity and noise radiati on between the flash memory and mask rom versions. when prep roducing an application set with the flash memory version and then mass producing it with the mask rom version, be sure to conduc t sufficient evaluations on the commercial samples (cs) (not engineer ing samples (es)) of the mask rom versions. writing to flash memory can be performed with memory m ounted on the target system (on board). a dedicated flash programmer is connected to t he target system to perform writing. the following can be considered as the development env ironment and the applications using flash memory. software can be changed after the v850e/ma1 is solder mounted on the target system. small scale production of various models is made easier by differentiating software. data adjustment in starting mass production is made easier. 16.1 features all area batch erase, or er ase in block units (128 kb) communication through serial interface from the dedicated flash programmer erase/write voltage: v pp = 7.8 v on-board programming flash memory programming by self-program ming in block units (128 kb) is possible 16.2 writing with flash programmer writing can be performed either on-board or off-board by the dedicated flash programmer. (1) on-board programming the contents of the flash memory ar e rewritten after the v850e/ma1 is mounted on the target system. mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) off-board programming writing to flash memory is performed by the dedicate d program adapter (fa series), etc., before mounting the v850e/ma1 on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. chapter 16 flash memory ( pd70f3107a) 528 user?s manual u14359ej5v1ud figure 16-1. wiring example of adapter (fa-144gj-uen) for v850e/ma1 flash memory programming pd70f3107a so sck si x1 /reset v pp reserve/hs x2 vdd gnd gnd vdd gnd vdd vdd gnd 112 113 124 134 135 143 connect to vdd connect to gnd 28 18 9 82 81 99 98 27 8 58 59 72 64 70 69 68 63 60 57 38 37 71 61 125 48 47 46 remarks 1. pins whose connections are not indicated shoul d be connected according to the recommended connections of unused pins (refer to 2.4 pin i/o circuits and recommended connection of unused pins ). when connecting to v dd via a resistor, it is recommended to use a resistor of 1 k ? to 10 k ? . 2. this adapter is for the 144-pin plastic lqfp package. 3. this figure shows the wiring for handshake supporting csi. caution to write to the flash memory by using th e flash programmer, the flash memory always operates in the pll mode at a frequency 10 times higher than that in the normal mode. therefore, keep the frequency that is input to the x1 pin to 4 to 5 mhz. chapter 16 flash memory ( pd70f3107a) 529 user?s manual u14359ej5v1ud table 16-1. wiring of adap ter for v850e/ma1 flash memo ry programming (fa-144gj-uen) pin configuration of flash programmer (p g-fp4) with csi0 + hs with csi0 signal name input/output pin function pin name pin no. pin name pin no. si/rxd input receive signal p40/so0 70 p40/so0 70 so/txd output transmit signal p41/si0 69 p41/si0 69 sck output transfer clock p42/sck0 68 p42/sck0 68 clk output clock to v850e/ma1 x1 63 x1 63 cksel input cg mode setting cksel 60 cksel 60 /reset output reset signal reset 59 reset 59 vpp output write voltage v pp /mode2 18 v pp /mode2 18 hs input handshake signal for csi0 + hs communication pal0/a0 143 not needed not needed v dd note 1 v dd note 1 cv dd 61 cv dd 61 vdd ? vdd voltage generation/ voltage monitor av dd /av ref 71 av dd /av ref 71 v ss note 2 v ss note 2 cv ss 64 cv ss 64 av ss 72 av ss 72 gnd ? ground p20/nmi 46 p20/nmi 46 mode0 58 mode0 58 mode ? flash write mode setting mode1 57 mode1 57 notes 1. 8, 27, 37, 47, 81, 98, 112, 124, 134 2. 9, 28, 38, 48, 82, 99, 113, 125, 135 chapter 16 flash memory ( pd70f3107a) 530 user?s manual u14359ej5v1ud figure 16-2. wiring example of adapter (fa-161f1-en4) for v850e /ma1 flash memory programming pd70f3107a si so sck /reset v pp reserve/hs clkout vdd gnd gnd vdd gnd vdd vdd gnd leave open connect to vdd connect to gnd b14 c14 a12 c11 a10 c8 c6 e14 f12 k14 n12 m14 n14 p14 k13 n13 n11 m11 p11 p13 a5 e5 a1 f4 k2 b1 b3 c1 d1 p1 l6 l9 p10 p8 p9 l1 n1 m1 p5 p2 m6 m8 m9 g1 j3 d14 b8 b5 n5 n10 remarks 1. pins whose connections are not indicated should be connected according to the recommended connections of unused pins (refer to 2.4 pin i/o circuits and recommended connection of unused pins ). when connecting to v dd via a resistor, it is recommended to use a resistor of 1 k ? to 10 k ? . 2. this adapter is for the 161-pin plastic fbga package. 3. this figure shows the wiring for handshake supporting csi. caution to write the flash memory by using the fl ash programmer, the flash memory always operates in the pll mode at a frequency 10 times higher than that in the normal mode. therefore, keep the frequency that is input to the x1 pin to 4 to 5 mhz. chapter 16 flash memory ( pd70f3107a) 531 user?s manual u14359ej5v1ud table 16-2. wiring of adap ter for v850e/ma1 flash memo ry programming (fa-161f1-en4) pin configuration of flash programmer (p g-fp4) with csi0 + hs with csi0 signal name input/output pin function pin name pin no. pin name pin no. si/rxd input receive signal p40/so0 m11 p40/so0 m11 so/txd output transmit signal p41/si0 p13 p41/si0 p13 sck output transfer clock p42/sck0 n11 p42/sck0 n11 clk output clock to v850e/ma1 x1 p10 x1 p10 cksel input cg mode setting cksel m9 cksel m9 /reset output reset signal reset l9 reset l9 vpp output write voltage v pp /mode2 g1 v pp /mode2 g1 hs input handshake signal for csi0 + hs communication pal0/a0 b3 not needed not needed v dd note 1 v dd note 1 cv dd p9 cv dd p9 vdd ? vdd voltage generation/ voltage monitor av dd /av ref n12 av dd /av ref n12 v ss note 2 v ss note 2 cv ss n10 cv ss n10 av ss n13 av ss n13 gnd ? ground p20/nmi n5 p20/nmi n5 mode0 m8 mode0 m8 mode ? flash write mode setting mode1 p8 mode1 p8 notes 1. a12, c6, c8, f4, f12, j3, k14, l6, p1 2. b5, b8, c11, d1, e14, k2, k13, m6, p2 chapter 16 flash memory ( pd70f3107a) 532 user?s manual u14359ej5v1ud 16.3 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850e/ma1. v850e/ma1 dedicated flash programmer v pp v dd v ss csi0 reset host machine rs-232-c usb pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve a host machine is required for controlling the dedicated flash programmer. csi0 is used for the interface between the dedicated flash programmer and the v850e/ma1 to perform writing, erasing, etc. a dedicated pr ogram adapter (fa series) is required for off-board writing. 16.4 communication mode (1) csi0 transfer rate: up to 2 mhz (msb first) v850e/ma1 v pp1 v dd v pp v dd v ss gnd reset so si sck clk dedicated flash programmer x1 sck0 so0 si0 reset pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x xx x x y y y y statve the dedicated flash programmer outputs the transfe r clock and the v850e/ma1 operates as a slave. (2) handshake-supported csi communication transfer rate: up to 2 mhz (msb first) v850e/ma1 dedicated flash programmer v pp1 v pp v dd v dd v ss gnd reset reset so si so0 si0 x1 pal0 sck sck0 clk hs pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xx x y yy x x x x x x x x x x x x x x x xx xx y yyy s tat v e chapter 16 flash memory ( pd70f3107a) 533 user?s manual u14359ej5v1ud 16.5 pin connection when performing on-board writing, instal l a connector on the target system to connect to the dedicated flash programmer. also, install a function to switch from t he normal operation mode (single- chip modes 0, 1 or romless modes 0, 1) to the flash memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming enter the same status as they were immediately after reset in single-chi p mode 0. therefore, because all the ports become output high-impedance, pin connection is required when the external device does not acknowledge the output high- impedance status. 16.5.1 mode2/v pp pin in the normal operation mode, 0 v is input to the mode2/v pp pin. in the flash memory programming mode, a 7.8 v writing voltage is supplied to the mode2/v pp pin. the following shows an ex ample of the connection of the mode2/v pp pin. v850e/ma1 mode2/v pp pull-down resistor (r vpp ) dedicated flash programmer connection pin 16.5.2 serial interface pin the following shows the pins used by each serial interface. serial interface pins used csi0 so0, si0, sck0 when connecting a dedicated flash programmer to a serial interface pin that is connected to other devices on- board, care should be taken to avoid the conflict of signals and the malfunction of other devices, etc. (1) conflict of signals when connecting a dedicated flash programmer (output) to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to av oid the conflict of signals, isolate the connection to the other device or set the other dev ice to the output high-impedance status. chapter 16 flash memory ( pd70f3107a) 534 user?s manual u14359ej5v1ud v850e/ma1 input pin output pin other device dedicated flash programmer connection pin conflict of signals in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs. therefore, isolate the signals on the other device side. (2) malfunction of other device when connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output) connected to another device (input), the signal output to the other device may cause the device to malfunction. to avoid this, isolate the connection to t he other device or set so that the input signal to the other device is ignored. v850e/ma1 output pin input pin other device dedicated flash programmer connection pin in the flash memory programming mode, if the signal the v850e/ma1 outputs affects the other device, isolate the signal on the other device side. v850e/ma1 input pin input pin other device dedicated flash programmer connection pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. chapter 16 flash memory ( pd70f3107a) 535 user?s manual u14359ej5v1ud 16.5.3 reset pin when connecting the reset signals of the dedicated flash programmer to the reset pin, which is connected to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of signal s, isolate the connection to the reset signal generator. when the reset signal is input from the user system in flash memory programming mode, the programming operations will not be performed correct ly. therefore, do not input signals other than the reset signal from the dedicated flash programmer. v850e/ma1 reset output pin reset signal generator dedicated flash programmer connection pin conflict of signals in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. 16.5.4 nmi pin do not change the signal input to the nmi pin in flash me mory programming mode. if it is changed in flash memory programming mode, programming may not be performed correctly. 16.5.5 mode0 to mode2 pins if mode0 is set as a high-level or low-level input and mode1 is set as a high-level input, a write voltage (7.8 v) is applied to the mode2/v pp pin and when reset is released, these pins change to the flash memory programming mode. 16.5.6 port pins when the flash memory programming mode is set, all the port pins except the pins that communicate with the dedicated flash programmer become output high-impedance. these pins must be connected according to the recommended connection of unused pins (refer to 2.4 pin i/o circuits and reco mmended connection of unused pins ). 16.5.7 other signal pins connect x1 and x2 in the same status as in the normal operation mode. 16.5.8 power supply supply the power (v dd , v ss , av dd , av ref , av ss , cv dd , and cv ss ) the same as when in normal operation mode. connect v dd and gnd of the dedicated flash programmer to v dd and v ss . (v dd of the dedicated flash programmer is provided with a power supply monitoring function.) chapter 16 flash memory ( pd70f3107a) 536 user?s manual u14359ej5v1ud 16.6 programming method 16.6.1 flash memory control the following shows the procedure for manipulating the flash memory. start switch to flash memory programming mode supply reset pulse select communication mode manipulate flash memory end? end no yes chapter 16 flash memory ( pd70f3107a) 537 user?s manual u14359ej5v1ud 16.6.2 flash memory programming mode when rewriting the contents of flash memory using the dedicated flash programmer, set the v850e/ma1 in the flash memory programming mode. to switch to this mode, set the mode0 to mode1 and mode2/v pp pins before releasing reset. when performing on-board writing, swit ch modes using a jumper, etc. ? mode0: high-level or low-level input ? mode1: high-level input ? mode2/v pp : 7.8 v ... n 1 flash memory programming mode mode0, mode1 1, 0 1, 1 7.8 v mode2/v pp 3 v 0 v reset 2 16.6.3 selection of communication mode in the v850e/ma1, the communication mode is select ed by inputting pulses (16 pulses max.) to the v pp pin after switching to the flash memory programming mode. the v pp pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. table 16-3. list of communication modes v pp pulse communication mode remarks 0 csi0 3 handshake-supporting csi v850e/ma1 performs slave operation, msb first other rfu (reserved) setting prohibited chapter 16 flash memory ( pd70f3107a) 538 user?s manual u14359ej5v1ud 16.6.4 communication commands the v850e/ma1 communicates with the dedicated flash programmer by means of commands. a command sent from the dedicated flash programmer to the v850e/ma1 is ca lled the ?command?. the response signal sent from the v850e/ma1 to the dedicated flash prog rammer is called the ?response command?. v850e/ma1 dedicated flash programmer command response command pg-fp4 (flash p ro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve the following shows the commands for controlling the flas h memory of the v850e/ma1. all of these commands are issued from the dedicated flash programmer, and the v850e/ma1 performs the various processing corresponding to the commands. category command name function batch verify command compares the contents of the entire memory and the input data. verify block verify command compares the contents of the specified memory block and the input data. batch erase command erases the c ontents of the entire memory. block erase command erases the cont ents of the specified memory block. erase write back command writes back the contents which were erased. batch blank check command checks the erase state of the entire memory. blank check block blank check command checks the er ase state of the specified memory block. high-speed write command writes data by the specification of the write address and the number of bytes to be written, and executes verify check. data write continuous write command writes data from the address following the high- speed write command executed immediately before, and executes verify check. status read out command acquires the status of operations. oscillating frequency setting command sets the oscillation frequency. erasure time setting command sets the erasing time of batch erase. write time setting command sets the writing time of data write. write back time setting command sets the write back time. silicon signature command reads outs the silicon signature information. system setting and control reset command escapes from each state. the v850e/ma1 sends back response commands for the comm ands issued from the dedicated flash programmer. the following shows the response commands the v850e/ma1 sends out. response command name function ack (acknowledge) acknowledges command/data, etc. nak (not acknowledge) acknowledges illegal command/data, etc. chapter 16 flash memory ( pd70f3107a) 539 user?s manual u14359ej5v1ud 16.7 flash memory programming by self-programming the pd70f3107a supports a self-programming function to re write the flash memory using a user program. by using this function, the flash memory can be rewritten with a user application. this se lf-programming function can be also used to upgrade the program in the field. 16.7.1 outline of self-programming self-programming implements erasure and writing of the flash memory by calling the self-programming function (device?s internal processi ng) on the program placed in the block 0 space (000000h to 1fffffh) and areas other than internal rom area. to place the program in the bl ock 0 space and internal rom area, copy the program to areas other than 000000h to 1fffffh (e.g. internal ram area) and execute the program to call the self- programming function. to call the self-programming function, change the operating mode from normal mode to self-programming mode using the flash programming mode control register (flpmc). figure 16-3. outline of self-programming 256 kb flash memory 00000h 3ffffh erase area note (128 kb) erase area note (128 kb) flash memory normal operation mode self-programming mode 00000h 3ffffh flpmc 02h flpmc 00h self-programming function (delete/write routine incorporated) note data is deleted in area units (128 kb). chapter 16 flash memory ( pd70f3107a) 540 user?s manual u14359ej5v1ud 16.7.2 self-programming function the pd70f3107a provides self-programming functions, as shown below. by combining these functions, erasing/writing flash memory becomes possible. table 16-4. function list type function name function erase area erase erases the specified area. continuous write in word units continuously writes the specified memory contents from the specified flash memory address, for the number of words specified in 4-byte units. write prewrite writes 0 to flash memory before erasure. erase verify checks whether an ov er erase occurred after erasure. erase byte verify checks whether erasure is complete. check internal verify checks whether the signal level of the post-write data in flash memory is appropriate. write back area write back writes back t he flash memory area in which an over erase occurred. acquire information flash memory information read reads out information about flash memory. 16.7.3 outline of sel f-programming interface to execute self-programming using t he self-programming interface, the envi ronmental conditions of the hardware and software for manipulating the flash memory must be satisfied. it is assumed that the self-programming interface is used in an assembly language. (1) entry program this program is to call the inter nal processing of the device. it is a part of the application program, and must be executed in memory other than the block 0 space and internal rom area (flash memory). (2) device internal processing this is manipulation of the flash memory executed inside the device. this processing manipulates the flash memory after it has been called by the entry program. (3) ram parameter this is a ram area to which the parameters necessary for self-programming, such as write time and erase time, are written. it is set by the application pr ogram and referenced by the device internal processing. chapter 16 flash memory ( pd70f3107a) 541 user?s manual u14359ej5v1ud the self-programming interface is outlined below. figure 16-4. outline of self-programming interface application program entry program ram parameter device internal processing flash memory self-programming interface flash-memory manipulation 16.7.4 hardware environment to write or erase the flash memory, a high voltage must be applied to the v pp pin. to execute self-programming, a circuit that can generate a write voltage (v pp ) and that can be controlled by software is necessary on the application system. an example of a circuit that can select a voltage to be applied to the v pp pin by manipulating a port is shown below. figure 16-5. example of self-p rogramming circuit configuration v dd = 3.3 0.3 v pd70f3107a v dd v ss v pp output port ic for power supply output input on/off v ss 10 k ? 10 k ? v in (v pp = 7.8 0.3 v) chapter 16 flash memory ( pd70f3107a) 542 user?s manual u14359ej5v1ud the voltage applied to the v pp pin must satisfy the following conditions: ? hold the voltage applied to the v pp pin at 0 v in the normal operation mode and hold the v pp voltage only while the flash memory is being manipulated. ? the v pp voltage must be stable from before manipulation of the flash memory star ts until manipulation is complete. cautions 1. apply 0 v to the v pp pin when reset is released. 2. implement self-programming in single-chip mode 0 or 1. 3. apply the voltage to the v pp pin in the entry program. 4. if both writing and erasing are executed by using the self-programming function and flash memory programmer on the target board, be sure to communicate with the programmer using csi0 (do not use the handshake-supporting csi). figure 16-6. timing to apply voltage to v pp pin flash memory manipulation reset signal v pp signal v pp 0 v v dd 0 v chapter 16 flash memory ( pd70f3107a) 543 user?s manual u14359ej5v1ud 16.7.5 software environment the following conditions must be satisfie d before using the entry program to call the device internal processing. table 16-5. software en vironmental conditions item description location of entry program execute the entry program in memory other than the block 0 space and flash memory area. the device internal processing cannot be directly ca lled by the program that is executed on the flash memory. execution status of program the device internal processing cannot be called while an interrupt is being serviced (np bit of psw = 0, id bit of psw = 1). masking interrupts mask all the maskable interrupts used. mask each interrupt by using the corresponding interrupt control register. to mask a maskable interrupt, be sure to specif y masking by using the corresponding interrupt control register. mask the maskable interrupt ev en when the id bit of the psw = 1 (interrupts are disabled). manipulation of v pp voltage stabilize the voltage applied to the v pp pin (v pp voltage) before starting m anipulation of the flash memory. after completion of the manipulation, return the voltage of the v pp pin to 0 v. initialization of internal timer do not use the internal timer while the flash memory is being manipulated. because the internal timer is initialized after the fl ash memory has been used, initialize the timer with the application program to use the timer again. stopping reset signal input do not input the reset signal while t he flash memory is being manipulated. if the reset signal is input while the flash memory is being manipulated, the contents of the flash memory under manipulation become undefined. stopping nmi signal input do not input the nmi signal while the flash memory is being manipulated. if the nmi signal is input while the flash memory is being manipulated, the flash memory may not be correctly manipulated by the device internal processing. if an nmi occurs while the device internal processing is in progress, the occurrence of the nmi is reflected in the nmi flag of the ram parameter. if manipulation of the flash memory is affected by the occurrence of the nmi, the function of each self-programming function is reflected in the return value. reserving stack area the device internal processing takes over the stack used by t he user program. it is necessary that an area of 300 bytes be reserved for the stack size of the user program when the device internal processing is called. r3 is used as the stack pointer. saving general-purpose registers the device internal processing rewrites the co ntents of r6 to r14, r20, and r31 (lp). save and restore these register contents as necessary. chapter 16 flash memory ( pd70f3107a) 544 user?s manual u14359ej5v1ud 16.7.6 self-programming function number to identify a self-programming function, the following numbers are assigned to the respective functions. these function numbers are used as parameters when the device internal processing is called. table 16-6. self-programming function number function no. function name 0 acquiring flash information 1 erasing area 2 to 4 rfu 5 area write back 6 to 8 rfu 9 erase byte verify 10 erase verify 11 to 15 rfu 16 successive write in word units 17 to 19 rfu 20 pre-write 21 internal verify other prohibited remark rfu: reserved for future use chapter 16 flash memory ( pd70f3107a) 545 user?s manual u14359ej5v1ud 16.7.7 calling parameters the arguments used to call the self-programming function are shown in the table below. in addition to these arguments, parameters such as the write time and erase ti me are set to the ram parameters indicated by ep (r30). table 16-7. calling parameters function name first argument (r6) function no. second argument (r7) third argument (r8) fourth argument (r9) return value (r10) acquiring flash information 0 option number note 1 ? ? note 1 erasing area 1 area erase start address ? ? 0: normal completion other than 0: error area write back 5 none (acts on erase manipulation area immediately before) ? ? none erase byte verify 9 verify star t address number of bytes to be verified ? 0: normal completion other than 0: error erase verify 10 none (acts on erase manipulation area immediately before) ? ? 0: normal completion other than 0: error successive write in word units note 2 16 write start address note 3 start address of write source data note 3 number of words to be written (word units) 0: normal completion other than 0: error pre-write 20 write start address number of bytes to be written ? 0: normal completion other than 0: error internal verify 21 verify star t address number of bytes to be verified ? 0: normal completion other than 0: error notes 1. see 16.7.10 flash information for details. 2. prepare write source data in memory other than the flash memory when data is written successively in word units. 3. this address must be at a 4-byte boundary. caution for all the functions, ep (r30) must in dicate the first address of the ram parameter. chapter 16 flash memory ( pd70f3107a) 546 user?s manual u14359ej5v1ud 16.7.8 contents of ram parameters reserve the following 48-byte area in the internal ram or external ram for the ram parameters, and set the parameters to be input. set the base addresses of these parameters to ep (r30). table 16-8. description of ram parameter address size i/o description ep+0 4 bytes ? for internal operations ep+4:bit 5 note 1 1 bit input operation flag. (be sure to set this flag to 1 before calling the device internal processing) 0: normal operation in progress 1: self-programming in progress ep+4:bit 7 notes 2, 3 1 bit output nmi flag 0: nmi not detected 1: nmi detected ep+8 4 bytes input erase time (unsigned 4 bytes) expressed as 1 count value in units of the internal operation unit time (100 s). set value = erase time ( s)/internal operation unit time ( s) example: if erase time is 0.4 s 0.4 1,000,000/100 = 4,000 (integer operation) ep+0xc 4 bytes input write bac k time (unsigned 4 bytes) expressed as 1 count value in units of the internal operation unit time (100 s). set value = write back time ( s)/internal operation unit time ( s) example: if write back time is 1 ms 1 1,000/100 = 10 (integer operation) ep+0x10 2 bytes input timer set value for creating internal operation unit time (unsigned 2 bytes) write a set value that makes the value of timer d the internal operation unit time (100 s). set value = operating frequency (hz)/1,000,000 internal operation unit time ( s)/ timer division ratio (4) + 1 note 4 example: if the operating frequency is 50 mhz 50,000,000/1,000,000 100/4 + 1 = 1,251 (integer operation) ep+0x12 2 bytes input timer set value for creating write time (unsigned 2 bytes) write a set value that makes the value of timer d the write time. set value = operating frequency (hz)/write time ( s)/timer division ratio (4) + 1 note 4 example: if the operating frequency is 50 mhz and the write time is 20 s 50,000,000/1,000,000 20/4 + 1 = 251 (integer operation) ep+0x14 28 bytes ? for internal operations notes 1. fifth bit of address of ep+4 (least significant bit is bit 0). 2. seventh bit of address of ep+4 (least significant bit is bit 0). 3. clear the nmi flag by the user program because it is not cleared by the device internal processing. 4. the device internal processing sets this value minus 1 to the timer. because th e fraction is rounded up, add 1 as indicated by the ex pression of the set value. caution be sure to reserve the ram parameter area at a 4-byte boundary. chapter 16 flash memory ( pd70f3107a) 547 user?s manual u14359ej5v1ud 16.7.9 errors during self-programming the following errors related to manipulation of the flas h memory may occur during self-programming. an error occurs if the return value (r10) of each function is not 0. table 16-9. errors during self-programming error function description overerase error erase verify excessive erasure occurs. undererase error (blank check error) erase byte verify erasure is insuffi cient. additional erase operation is needed. verify error successi ve writing in word units the written data cannot be correctly read. either an attempt has been made to write to flash memory that has not been erased, or writing is not sufficient. internal verify error internal verify the wr itten data is not at the correct signal level. caution the overerase error and undererase error may simultaneously occur in the entire flash memory. 16.7.10 flash information for the flash information acquisition function (function no. 0), the option number (r7) to be specified and the contents of the return value (r10) are as follows. to acqui re all flash information, call the function as many times as required in accordance with the format shown below. table 16-10. flash information option no. (r7) return value (r10) 0 specification prohibited 1 specification prohibited 2 bit representation of return value (msb: bi t 31) fffffffffff fffffaaaaaaaaffffffff (lsb: bit 0) bits 31 to 16: ffffffffffffffff (reserved for future use) mask bits 31 to 16 because they are not normally 0. bits 15 to 8: aaaaaaaa (number of areas) (unsigned 8 bits) bits 7 to 0: ffffffff (reserved for future use) mask bits 7 to 0 because they are not normally 0. 3+0 end address of area 0 3+1 end address of area 1 cautions 1. the start address of area 0 is 0. the ?end address + 1? of the preceding area is the start address of the next area. 2. the flash information acquisition functi on does not check values su ch as the maximum number of areas specified by the argument of an option. if an illegal value is specified, an undefined value is returned. chapter 16 flash memory ( pd70f3107a) 548 user?s manual u14359ej5v1ud 16.7.11 area number the area numbers and memory map of the pd70f3107a are shown below. figure 16-7. area configuration area 1 (128 kb) area 0 (128 kb) 0 x 3 f f f f (end address of area 1) 0 x 0 0 0 0 0 (start address of area 0) 0 x 2 0 0 0 0 (start address of area 1) 0 x 1 f f f f (end address of area 0) chapter 16 flash memory ( pd70f3107a) 549 user?s manual u14359ej5v1ud 16.7.12 flash programming mode control register (flpmc) the flash memory mode control register (flpmc) is a register used to enable/disable writing to flash memory and to specify the self-programming mode. this register can be read/written in 8-bit or 1- bit units (the vpp bit (bit 2) is read-only). cautions 1. be sure to transfer control to th e internal ram or external memory beforehand to manipulate the flspm bit. however, in on- board programming mode set by the flash programmer, the specification of flspm bit is ignored. 2. do not change the initial value of bits 0 and 4 to 7. flpmc address fffff8d4h after reset note 08h/0ch/00h 7 6 5 4 <3> <2> <1> 0 0 flspm vpp vppdis 0 0 0 0 note 08h: when writing voltage is not applied to the v pp pin 0ch: when writing voltage is applied to the v pp pin 00h: product not provided with flash memory ( pd703103a, 703105a, 703106a, 703107a) bit position bit name function 3 vppdis v pp disable enables/disables writing/deleting on-chip flash memory. when this bit is 1, writing/deleting on-chip flash memory is disabled even if a high voltage is applied to the v pp pin. 0: enables writing/deleting flash memory 1: disables writing/deleting flash memory 2 vpp v pp indicates the voltage applied to the v pp pin reaches the writing-enabled level. this bit is used to check whether writing is pos sible or not in the self-programming mode. 0: indicates high-voltage application is not detected. (the voltage has not reached the writing voltage enable level) 1: indicates high-voltage application is detected. (the voltage has reached the writing voltage enable level) 1 flspm flash self programming mode controls switching between internal rom and the self-programming interface. this bit can switch the mode between the normal mode set by the mode pin on the application system and the self-programming mo de. the setting of this bit is valid only if the voltage applied to the v pp pin reaches the writing voltage enable level. 0: normal mode (for all addresses, instruction fetch is performed from on-chip flash memory) 1: self-programming mode (device internal processing is started) chapter 16 flash memory ( pd70f3107a) 550 user?s manual u14359ej5v1ud setting data to the flash programming mode control regist er (flpmc) is performed in the following sequence. <1> disable interrupts (set the np bit and id bit of the psw to 1) <2> prepare the data to be set in the specif ic register in a general-purpose register <3> write data to the peripheral command register (phcmd) <4> set the flash memory programming mode control regi ster (flpmc) by executing the following instructions ? store instruction (st/sst instructions) ? bit manipulation instruction (set1/clr1/not1 instructions) <5> insert nop instructions (5 instructions <5> to <9>) <10> cancel the interrupt disabled stat e (reset the np bit of the psw to 0) [description example] <1> ldsr rx, 5 <2> mov 0x02, r10 <3> st.b r10, phcmd [r0] <4> st.b r10, flpmc [r0] <5> nop <6> nop <7> nop <8> nop <9> nop <10> ldsr ry, 5 remark rx: value written to the psw ry: value returned to the psw no special sequence is required for reading a specific register. cautions 1. if an interrupt is acknowledged between when phcmd is issued (<3>) and writing to a specific register (<4>) immediat ely after issuing phcmd, writi ng to the specific register may not be performed and a protection error may occu r (the prerr bit of the phs register = 1). therefore, set the np bit of the psw to 1 (<1>) to disable interrupt acknowledgment. similarly, disable acknowledgement of interr upts when a bit manipulation instruction is used to set a specific register. 2. use the same general-purpose register used to set a specific register (<3>) for writing to the phcmd register (<4>) even though the data wri tten to the phcmd register is dummy data. this is the same as when a general-purpo se register is used for addressing. 3. do not use dma transfer for writing to the phcmd register and a specific register. chapter 16 flash memory ( pd70f3107a) 551 user?s manual u14359ej5v1ud 16.7.13 calling device internal processing this section explains the procedure to call the dev ice internal processing from the entry program. before calling the device internal processing, make sure that all the conditions of the hardware and software environments are satisfied and that the necessary argum ents and ram parameters have been set. call the device internal processing by setting the flspm bit of the flas h programming mode control register (flpmc) to 1 and then executing the trap 0x1f instruction. th e processing is always called using the same procedure. it is assumed that the program of this interface is described in an assembly language. <1> set the flpmc register as follows: ? vppdis bit = 0 (to enable writing/erasing flash memory) ? flspm bit = 1 (to select self-programming mode) <2> clear the np bit of the psw to 0 (to enable nmis (only when nmis are used on the application)). <3> execute trap 0x1f to transfer the cont rol to the device?s internal processing. <4> set the np bit and id bit of the psw to 1 (to disable all interrupts). <5> set the value to the peripheral command register (phcmd) that is to be set to the flpmc register. <6> set the flpmc register as follows: ? vppdis bit = 1 (to disable writing/erasing flash memory) ? flspm bit = 0 (to select normal operation mode) <7> wait for the internal manipulation setup time (see 16.7.13 (5) internal ma nipulation setup parameter ). (1) parameter r6: first argument (sets a self-programming function number) r7: second argument r8: third argument r9: fourth argument ep: first address of ram parameter (2) return value r10: return value (return value from device internal processing of 4 bytes) ep+4:bit 7: nmi flag (flag indicating whether an nmi occurred while the device internal processing was being executed) 0: nmi did not occur while device internal processing was being executed. 1: nmi occurred while device internal processing was being executed. if an nmi occurs while control is being transfe rred to the device internal processing, the nmi request may never be reflected. because the nmi flag is not internally reset, this bit must be cleared before calling the device internal processi ng. after the control returns from the device internal processing, nmi dummy processing can be executed by checking the status of this flag using software. (3) description transfer control to the device internal processing specif ied by a function number using the trap instruction. to do this, the hardware and software environmental conditi ons must be satisfied. even if trap 0x1f is used in the user application program, trap 0x1f is treated as another operation afte r the flpmc register has been set. therefore, use of the tr ap instruction is not rest ricted on the application. chapter 16 flash memory ( pd70f3107a) 552 user?s manual u14359ej5v1ud (4) program example an example of a program in which the entry program is executed as a subroutine is shown below. in this example, the return address is saved to the stack and then the device internal processing is called. this program must be located in memory other th an the block 0 space and flash memory area. isetup 130 -- internal manipulation setup parameter entryprogram: add -4, sp -- prepare st.w lp, 0[sp] -- save return address movea lo(0x00a0), r0, r10 -- ldsr r10, 5 -- psw = np, id mov lo(0x0002), r10 -- st.b r10, phcmd[r0] -- phcmd = 2 st.b r10, flpmc[r0] -- vppdis = 0, flspm = 1 nop nop nop nop nop movea lo(0x0020), r0, r10 -- ldsr r10, 5 -- psw = id trap 0x1f -- device internal process movea lo(0x00a0), r0, r6 -- ldsr r6, 5 -- psw = np, id mov lo(0x08), r6 st.b r6, phcmd[r0] -- phcmd = 8 st.b r6, flpmc[r0] -- vppdis = 1, flspm = 0 nop nop nop nop nop mov isetup, lp -- loop time = 130 loop: divh r6, r6 -- to kill time add -1, lp -- decrement counter jne loop -- ld.w 0[sp], lp -- reload lp add 4, sp -- dispose jmp [lp] -- return to caller chapter 16 flash memory ( pd70f3107a) 553 user?s manual u14359ej5v1ud (5) internal manipulation setup parameter if the self-programming mode is switc hed to the normal operation mode, the pd70f3107a must wait for 100 s before it accesses the flash memory. in the program exam ple in (4) above, the elapse of this wait time is ensured by setting isetup to ?130? (@ 50 mhz operatio n). the total number of execution clocks in this example is 39 clocks (divh instruction (35 clocks) + add instruction (1 clo ck) + jne instruction (3 clocks)). ensure that a wait time of 100 s elapses by using the following expression. 39 clocks (total number of execution clocks) 20 ns (@ 50 mhz operation) 130 (isetup) = 101.4 s (wait time) chapter 16 flash memory ( pd70f3107a) 554 user?s manual u14359ej5v1ud 16.7.14 erasing flash memory flow the procedure to erase the flash memory is illustrated bel ow. the processing of each function number must be executed in accordance with the specified calling procedure. figure 16-8. erasing flash memory flow ... function no. 20 ... function no. 1 ... function no. 9 ... function no. 10 ... function no. 5 ... function no. 10 ... function no. 9 erase write error undererase error set ram parameter. mask interrupts. pre-write erase area. erase byte verify erase verify area write back erase verify clear number of times write-back is repeated. erase byte verify write error? undererase? maximum number of times of repeating erasure is exceeded? maximum number of times of repeating write-back is exceeded? overerase? overerase? undererase? set v pp voltage. clear v pp voltage. unmask interrupts. clear v pp voltage. unmask interrupts. normal completion clear v pp voltage. unmask interrupts. overerase error clear v pp voltage. unmask interrupts. normal completion clear v pp voltage. unmask interrupts. yes yes yes yes no no no yes no no no yes no yes chapter 16 flash memory ( pd70f3107a) 555 user?s manual u14359ej5v1ud 16.7.15 successive writing flow the procedure to write data all at once to the flash memory by using the function to successively write data in word units is illustrated below. the processing of each functi on number must be executed in accordance with the specified calling procedure. figure 16-9. successive writing flow ... function no. 16 yes no successive writing mask interrupts. set v pp voltage. successive writing error? clear v pp voltage. unmask interrupts. write error clear v pp voltage. unmask interrupts. normal completion set ram parameter. chapter 16 flash memory ( pd70f3107a) 556 user?s manual u14359ej5v1ud 16.7.16 internal verify flow the procedure of internal verificati on is illustrated below. the processing of each function number must be executed in accordance with the specified calling procedure. figure 16-10. internal verify flow ... function no. 21 yes no internal verify mask interrupts. set v pp voltage. internal verify error? clear v pp voltage. unmask interrupts. internal verify error clear v pp voltage. unmask interrupts. normal completion set ram parameter. chapter 16 flash memory ( pd70f3107a) 557 user?s manual u14359ej5v1ud 16.7.17 acquiring flash information flow the procedure to acquire the flash info rmation is illustrated below. the proce ssing of each function number must be executed in accordance with t he specified calling procedure. figure 16-11. acquiring flash information flow ... function no. 0 acquiring flash information mask interrupts. set v pp voltage. acquiring flash information clear v pp voltage. unmask interrupts. end set ram parameter. chapter 16 flash memory ( pd70f3107a) 558 user?s manual u14359ej5v1ud 16.7.18 self-programming library v850 series user?s manual flash me mory self programming library is available for reference when executing self-programming. in this manual, the library uses the self-programming inte rface of the v850 series and can be used in c as a utility and as part of the application program . to use the library, thoroughly evaluate it on the application system. (1) functional outline figure 16-12 outlines the function of the self-programming library. in this figure, a rewriting module is located in area 0 and the data in area 1 is rewritten or erased. the rewriting module is a user program to rewrite the flash memory. the other areas can be also rewritten by using the flash functions included in this self-progr amming library. the flash functions expand the entry program in the external memory or internal ram and call the device internal processing. when using the self-programming library, make sure that the hardware conditions, such as the write voltage, and the software conditions, such as interrupts, are satisfied. figure 16-12. functional outlin e of self-programming library rewriting module flash rewriting program self-programming library flash function flash environment erase/write flash memory rewriting module area 1 area 0 chapter 16 flash memory ( pd70f3107a) 559 user?s manual u14359ej5v1ud the configuration of the self-programming library is outlined below. figure 16-13. outline of self-p rogramming library configuration application program entry program ram parameter device internal processing flash memory self-programming interface self-programming library flash memory manipulation c interface chapter 16 flash memory ( pd70f3107a) 560 user?s manual u14359ej5v1ud 16.8 how to distinguish flash memory and mask rom versions it is possible to distinguish a flash memory version ( pd70f3107a) and mask rom versions ( pd703105a, 703106a, 703107a) by means of software, using the methods shown below. <1> disable interrupts (set the np bit of psw to 1). <2> write data to the peripheral command register (phcmd). <3> set the vppdis bit of the flash progra mming mode control register (flpmc) to 1. <4> insert nop instructions (5 instructions (<4> to <8>)). <9> cancel the interrupt disabled state (reset the np bit of the psw to 0). <10> read the vppdis bit of the flash prog ramming mode control register (flpmc). ? if the value read is 0: mask rom version ( pd703105a, 703106a, 703107a) ? if the value read is 1: flash memory version ( pd70f3107a) [description example] <1> ldsr rx, 5 <2> st.b r10, phcmd [r0] <3> set1 3, flpmc [r0] <4> nop <5> nop <6> nop <7> nop <8> nop <9> ldsr ry, 5 <10> tst1 3, flpmc [r0] bnz user's manual u14359ej5v1ud 561 chapter 17 electrical specifications 17.1 normal operation mode absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v dd pin ? 0.5 to +4.6 v cv dd cv dd pin ? 0.5 to +4.6 v cv ss cv ss pin ? 0.5 to +0.5 v av dd av dd pin ? 0.5 to +4.6 v power supply voltage av ss av ss pin ? 0.5 to +0.5 v x1 pin, except mode2/v pp pin notes 1, 2 v 1 < v dd + 3.0 v ? 0.5 to +6.0 v input voltage v i mode2/v pp pin ? 0.5 to +8.5 note 1 v clock input voltage v k x1, v dd = 3.3 v 0.3 v ? 0.5 to v dd + 1.0 v per pin 4.0 ma output current, low i ol total of all pins 100 ma per pin ? 4.0 ma output current, high i oh total of all pins ? 100 ma output voltage v o v dd = 3.3 v 0.3 v ? 0.5 to v dd + 0.5 v analog input voltage v wasn ani0 to ani7, v dd = 3.3 v 0.3 v, av dd < v dd + 0.5 v ? 0.3 to av dd + 0.3 v operating ambient temperature t a ? 40 to +85 c lqfp package ? 60 to +150 c storage temperature t stg fbga package ? 40 to +125 c notes 1. pd70f3107a and 70f3107a(a) only 2. make sure that the following conditions of the v pp voltage application timing are satisfied when programming flash memory. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd reached the lower-limit val ue (3.0 v) of the operating voltage range (see ?a? in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (3.0 v) of the operating voltage range of v dd (see ?b? in the figure below). 3.0 v v dd 0 v 0 v v pp 3.0 v a b chapter 17 electrical specifications user's manual u14359ej5v1ud 562 cautions 1. avoid direct connections among th e ic device output (or i/o) pins and between v dd or v cc and gnd. however, direct connections among open-drain and open-collector pins are possible, as are direct conn ections to external circuits th at have timing designed to prevent output conflict with pins that become high-impedance. 2. product quality may suffer if the ab solute maximum rati ng is exceeded even momentarily for any parameter. that is, th e absolute maximum ra tings are rated values at which the product is on the verge of su ffering physical damage, and therefore the product must be used under conditions that en sure that the absolu te maximum ratings are not exceeded. the ratings and conditi ons shown below for dc characteristics and ac characteristics are within the range fo r normal operation and quality assurance. capacitance (t a = 25 c, v dd = cv dd = av dd = v ss = cv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v. 15 pf operating conditions operation mode internal operation clock frequency (f xx ) operating ambient temperature (t a ) power supply voltage (v dd ) direct mode 4 to 25 mhz ? 40 to +85 c v dd = 3.3 v 0.3 v pll mode 4 to 50 mhz ? 40 to +85 c v dd = 3.3 v 0.3 v chapter 17 electrical specifications user's manual u14359ej5v1ud 563 recommended oscillator caution for the resonator selection and oscillator constant of the pd703106a(a), 703107a(a), and 70f3107a(a), customers are re quested to apply to the resonator manufacturer for evaluation. (a) ceramic resonator (i) murata mfg. co., ltd. (t a = ?40 to +85 c) x1 x2 c1 c2 r d oscillation frequency recommended circuit constant oscillation voltage range oscillation stabilization time (max.) type product f x (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) t ost (ms) cstcr4m00g55-r0 4.0 on-chip on-chip 0 3.0 3.6 0.07 surface mount cstcr5m00g55-r0 5.0 on-chip on-chip 0 3.0 3.6 0.07 cstcr6m60g55-r0 6.6 on-chip on-chip 0 3.0 3.6 0.06 cautions 1. connect the oscillator as clo sely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd703103a, 703105a, 703106a, 703107a, 70f3107a and the resonator. chapter 17 electrical specifications user's manual u14359ej5v1ud 564 (ii) kyocera corporation (t a = ?20 to +80 c) x1 x2 c1 c2 r d oscillation frequency recommended circuit constant oscillation voltage range oscillation stabilization time (max.) type product f x (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) t ost (ms) pbrc4.00ar-a 4.0 33 33 0 3.0 3.6 0.11 pbrc4.00br-a 4.0 on-chip on-chip 0 3.0 3.6 0.11 pbrc5.00ar-a 5.0 33 33 0 3.0 3.6 0.08 surface mount pbrc5.00br-a 5.0 on-chip on-chip 0 3.0 3.6 0.08 kbr-4.0msb 4.0 33 33 0 3.0 3.6 0.11 kbr-4.0mkc 4.0 on-chip on-chip 0 3.0 3.6 0.11 kbr-5.0msb 5.0 33 33 0 3.0 3.6 0.08 lead kbr-5.0mkc 5.0 on-chip on-chip 0 3.0 3.6 0.08 cautions 1. connect the oscillator as clo sely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd703103a, 703105a, 703106a, 703107a, 70f3107a and the resonator. (b) external clock input (t a = ?40 to +85 c) x1 x2 open external clock chapter 17 electrical specifications user's manual u14359ej5v1ud 565 dc characteristics (t a = ?40 to +85 c, v dd = cv dd = av dd = 3.3 v 0.3 v, v ss = cv ss = av ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit except for note 1 2.0 5.5 v input voltage, high v ih note 1 0.75v dd 5.5 v except for note 1 ?0.5 0.8 v input voltage, low v il note 1 ?0.5 0.2v dd v direct mode 0.8v dd v dd + 0.3 v clock input voltage, high v xh x1 pin pll mode 0.8v dd v dd + 0.3 v direct mode ?0.5 0.15v dd v clock input voltage, low v xl x1 pin pll mode ?0.5 0.15v dd v v t + note 1 , rising edge 2.0 v schmitt- triggered input threshold voltage v t ? note 1 , falling edge 1.0 v schmitt- triggered input hysteresis width v t + ? v t ? note 1 0.3 v i oh = ?2.5 ma 0.8v dd v output voltage, high v oh i oh = ?100 a v dd ? 0.4 v output voltage, low v ol i ol = 2.5 ma 0.45 v input leakage current, high i lih v i = v dd , except for note 2 10 a input leakage current, low i lil v i = 0 v, except for note 2 ? 10 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ? 10 a analog pin input leakage current i lwasn note 2 10 a v pp supply voltage note 3 v pp0 during normal operation 0 0.2v dd v notes 1. p01/ti000/intp000, p02/intp001, p04/dmarq0/intp100 to p07/dmarq3/intp103, p11/ti010/intp010, p12/intp011, p20/nmi, p21/ ti020/intp020, p22/intp021, p24/tc0/intp110 to p27/tc3/intp113, p30/so2/intp130, p31/si2 /intp131, p32/sck2/intp132, p33/txd2/intp133, p34/rxd2/intp120, p35/intp121, p36/intp122, p37/adtrg/intp123, p41/rxd0/si0, p42/sck0, p44/rxd1/si1, p45/sck1, p50/ti030/intp030, p51/intp031, mode0, mode1, mode2/v pp (v pp is available in pd70f3107a and 70f3107a(a) only, reset, cksel 2. p70/ani0 to p77/ani7 3. pd70f3107a and 70f3107a(a) only remark typ. values are reference values for when t a = 25 c and v dd = 3.3 v. chapter 17 electrical specifications user's manual u14359ej5v1ud 566 dc characteristics (t a = ?40 to +85 c, v dd = cv dd = av dd = 3.3 v 0.3 v, v ss = cv ss = av ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit direct mode note 1 2.6 f xx + 30 3.9 f xx + 45 ma note 2 3.2 f xx + 30 4.8 f xx + 45 ma pll mode note 1 2.6 f xx + 30 3.9 f xx + 45 ma during normal operation i dd1 note 2 3.2 f xx + 30 4.8 f xx + 45 ma direct mode 1.6 f xx + 20 2.4 f xx + 30 ma in halt mode i dd2 pll mode 1.6 f xx + 20 2.4 f xx + 30 ma direct mode 10 30 ma in idle mode i dd3 pll mode 10 30 ma ?40 c t a +40 c 10 60 a note 1 250 a power supply current (v dd + cv dd ) in stop mode i dd4 40 c < t a 85 c note 2 600 a notes 1. pd703103a, 703105a, 703106a, 703106a(a), 703107a, 703107a(a) 2. pd70f3107a, 70f3107a(a) remarks 1. typ. values are reference values for when t a = 25 c and v dd = 3.3 v. the current does not include the current flowing through pull-up resistors. 2. f xx : cpu operation frequency chapter 17 electrical specifications user's manual u14359ej5v1ud 567 data retention characteristics (t a = ?40 to + 85 c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode and v dd = v dddr 1.5 3.6 v ?40 c t a +40 c 10 60 a note 1 250 a data retention current i dddr v dd = v dddr 40 c < t a 85 c note 2 600 a power supply voltage rise time t rvd 200 s power supply voltage fall time t fvd 200 s power supply voltage hold time (from stop mode setting) t hvd 0 ms stop release signal input time t drel 0 ns data retention input voltage, high v ihdr note 3 0.8v dddr v dddr v data retention input voltage, low v ildr note 3 ?0.5 0.2v dddr v notes 1. pd703103a, 703105a, 703106a, 703106a(a), 703107a, 703107a(a) 2. pd70f3107a, 70f3107a(a) 3. p01/ti000/intp000, p02/intp001, p04/dmarq0/intp100 to p07/dmarq3/intp103, p11/ti010/intp010, p12/intp011, p20/nmi, p21/ ti020/intp020, p22/intp021, p24/tc0/intp110 to p27/tc3/intp113, p30/so2/intp130, p31/si2/in tp131, p32/sck2/intp132, p33/txd2/intp133, p34/rxd2/intp120, p35/intp121, p36/intp122, p37/adtrg/intp123, p41/rxd0/si0, p42/sck0, p44/rxd1/si1, p45/sck1, p50/ti030/intp030, p51/intp031, mode0, mode1, mode2/v pp (v pp is available in pd70f3107a and 70f3107a(a) only), reset, cksel remark typ. values are reference values for when t a = 25 c. v dd 3.0 v setting stop mode t hvd t fvd reset (input) stop mode release interrupt (nmi, etc.) (when stop mode is released at falling edge) stop mode release interrupt (nmi, etc.) (when stop mode is released at rising edge) t rvd t drel v dddr v ihdr v ildr v ihdr caution shifting to stop mode and restori ng from stop mode must be performed at v dd = 3.0 v min. chapter 17 electrical specifications user's manual u14359ej5v1ud 568 ac characteristics (t a = ?40 to + 85 c, v dd = cv dd = av dd = 3.3 v 0.3 v, v ss = cv ss = av ss = 0 v, output pin load capacitance: c l = 50 pf) ac test input test points (a) p01/ti000/intp000, p02/intp001, p04/dmarq0/in tp100 to p07/dmarq3/intp103, p11/ti010/intp010, p12/intp011, p20/nmi, p21/ti020/intp020, p22/in tp021, p24/tc0/intp110 to p27/tc3/intp113, p30/so2/intp130, p31/si2/intp131, p32/sck2/in tp132, p33/txd2/intp133, p34/rxd2/intp120, p35/intp121, p36/intp122, p37/adtrg/intp123, p41/ rxd0/si0, p42/sck0, p44/rxd1/si1, p45/sck1, p50/ti030/intp030, p51/intp031, mode0, mode1, mode2/v pp (v pp is available in pd70f3107a and 70f3107a(a) only), reset, cksel v dd 0.75v input signal dd 0.2v dd 0.75v dd 0.2v dd 0 v test points (b) other than (a) above 2.0 v 0.8 v 2.0 v 0.8 v v dd input signal 0 v test points ac test output test points 0.7v dd 0.2v dd 0.7v dd 0.2v dd output signal test points load condition caution in cases where the lo ad capacitance is greater than 50 pf due to the circuit configuration, insert a buffer or other elemen t to reduce the devi ce?s load capacitance to 50 pf or lower. c l = 50 pf dut (device under test) chapter 17 electrical specifications user's manual u14359ej5v1ud 569 (1) clock timing (1/2) parameter symbol conditions min. max. unit direct mode 20 125 ns 10 200 250 ns x1 input cycle <1> t cyx pll mode other than 10 150 250 ns direct mode 5 ns x1 input high-level width <2> t wxh pll mode 50 ns direct mode 5 ns x1 input low-level width <3> t wxl pll mode 50 ns direct mode 4 ns x1 input rise time <4> t xr pll mode 10 ns direct mode 4 ns x1 input fall time <5> t xf pll mode 10 ns clkout output cycle <6> t cyk1 20 250 ns clkout high-level width <7> t wkh1 0.5t ? 5 ns clkout low-level width <8> t wkl1 0.5t ? 6 ns clkout rise time <9> t kr1 5 ns clkout fall time <10> t kf1 4 ns delay time from x1 to clkout <11> t dkx 40 ns delay time from x1 to sdclk <12> t dsx 40 ns sdclk output cycle <13> t cyk2 20 250 ns sdclk high-level width <14> t wkh2 0.5t ? 5 ns sdclk low-level width <15> t wkl2 0.5t ? 6 ns sdclk rise time <16> t kr2 5 ns sdclk fall time <17> t kf2 4 ns busclk rise time <18> t kr3 5 ns busclk fall time <19> t kf3 4 ns remarks 1. t = t cyk 2. the phase difference between clkout and sdcl k, and between clkout and busclk cannot be defined. chapter 17 electrical specifications user's manual u14359ej5v1ud 570 (1) clock timing (2/2) remark the cycle of busclk vari es depending on the bus cycle. (2) output waveform (other than x1 and clkout) parameter symbol conditions min. max. unit output rise time <20> t or 5 ns output fall time <21> t of 4 ns <21> <20> signals other than x1 and clkout x1 <2> <1> <3> <5> <4> x1 (direct mode) (pll mode) <5> <1> <2> <3> <4> <11> <11> <12> clkout (output) <8> <9> <7> <10> <6> sdclk (output) <15> <16> <14> <17> <13> busclk (output) <18> <19> chapter 17 electrical specifications user's manual u14359ej5v1ud 571 (3) reset timing parameter symbol conditions min. max. unit reset pin high-level width <22> t wrsh 500 ns at power-on and at stop mode release 500 + t ost ns reset pin low-level width <23> t wrsl other than at power-on and at stop mode release 500 ns remark t ost : oscillation stabilization time caution thoroughly evaluate the oscillation stabilization time. <22> <23> reset (input) chapter 17 electrical specifications user's manual u14359ej5v1ud 572 (4) sram, external rom, and external i/o access timing (when bcp bit of bcp register = 0) (a) access timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit address, csn output delay time (from clkout ) 2 13 ns address, csn output delay time (from sdclk ) <24> t dka1 0 13 ns address, csn output hold time (from clkout ) 2 13 ns address, csn output hold time (from sdclk ) <25> t hka 0 13 ns rd, iord delay time (from clkout ) 2 13 ns rd, iord delay time (from sdclk ) <26> t dkrdl 0 13 ns rd, iord delay time (from clkout ) 2 13 ns rd, iord delay time (from sdclk ) <27> t hkrdh 0 13 ns uwr, lwr, iowr delay time (from clkout ) 2 13 ns uwr, lwr, iowr delay time (from sdclk ) <28> t dkwrl 0 13 ns uwr, lwr, iowr delay time (from clkout ) 2 13 ns uwr, lwr, iowr delay time (from sdclk ) <29> t hkwrh 0 13 ns bcyst delay time (from clkout ) 2 13 ns bcyst delay time (from sdclk ) <30> t dkbsl 0 13 ns bcyst delay time (from clkout ) 2 13 ns bcyst delay time (from sdclk ) <31> t hkbsh 0 13 ns wait setup time (to clkout ) 8 ns wait setup time (to sdclk ) <32> t swk 10 ns wait hold time (from clkout ) 2 ns wait hold time (from sdclk ) <33> t hkw 2 ns data input setup time (to clkout ) 8 ns data input setup time (to sdclk ) <34> t skid 10 ns data input hold time (from clkout ) 2 ns data input hold time (from sdclk ) <35> t hkid 2 ns data output delay time (from clkout ) 2 13 ns data output delay time (from sdclk ) <36> t dkod1 0 13 ns data output delay time (from clkout ) 2 13 ns data output delay time (from sdclk ) <37> t dkod2 0 13 ns data float delay time (from clkout ) 2 13 ns data float delay time (from sdclk ) <38> t hkod 0 13 ns remarks 1. maintain at least one of the data input hold times, t hrdid or t hkid . 2. n = 0 to 7 chapter 17 electrical specifications user's manual u14359ej5v1ud 573 (a) access timing (sram, external rom, external i/o) (2/2) clkout (output) [ read ] [ write ] [ write ] [ read ] rd, iord (output) t1 tw t2 <24> <25> <30> <26> <28> <29> <27> <35> <34> <37> <38> <32> <33> <32> <33> a0 to a25 (output) uwr, lwr, iowr (output) d0 to d15 (i/o) d0 to d15 (i/o) <31> <29> <38> <27> <30> <26> <28> <36> <36> sdclk (output) csn (output) wait (input) bcyst (output) ube, lbe (output) remarks 1. this is the timing when the number of waits based on the dwc0 and dwc1 registers is zero. 2. broken lines indicate high impedance. 3. n = 0 to 7 chapter 17 electrical specifications user's manual u14359ej5v1ud 574 (b) read timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit data input setup time (from address) <39> t said (2 + w + w d + w as )t ? 19 ns data input setup time (from rd) <40> t srdid (1.5 + w + w d )t ? 19 ns rd, iord low-level width <41> t wrdl (1.5 + w + w d )t ? 10 ns rd, iord high-level width <42> t wrdh (0.5 + w as + i)t ? 10 ns delay time from address, csn, to rd, iord <43> t dard (0.5 + w as )t ? 10 ns delay time from rd, iord to address <44> t drda it ns data input hold time (from rd, iord ) <45> t hrdid 0 ns delay time from rd, iord to data output <46> t drdod (0.5 + i)t ? 10 ns wait setup time (to address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (to bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note t ? 10 ns wait high-level width <50> t wwh t ? 10 ns data output hold time (from uwr, lwr, iowr ) <57> t hwrod (0.5 + i)t ? 8 ns note for the first wait sampling when the wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. maintain at least one of the data input hold times t hrdid or t hkid 5. n = 0 to 7 6. i: idle state count 7. w as : address setup wait count based on the asc register 8. for the number of w and w d to be inserted, refer to 4.6.3 relationship be tween programmable wait and external wait . chapter 17 electrical specifications user's manual u14359ej5v1ud 575 (b) read timing (sram, external rom, external i/o) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait coun t based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7 clkout (output) csn (output) a0 to a25 (output) uwr, lwr, iowr rd, iord (output) d0 to d15 (i/o) t1 tw t2 <45> <42> <41> <44> <46> <39> <40> <43> <47> <48> ti tasw <49> <57> <50> wait (input) bcyst (output) (output) ube, lbe (output) chapter 17 electrical specifications user's manual u14359ej5v1ud 576 (c) write timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit wait setup time (from address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (from bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note t ? 10 ns wait high-level width <50> t wwh t ? 10 ns delay time from address, csn to uwr, lwr, iowr <51> t dawr (0.5 + w as )t ? 10 ns address setup time (to uwr, lwr, iowr ) <52> t sawr (1.5 + w + w d + w as )t ? 10 ns delay time from uwr, lwr, iowr to address <53> t dwra (0.5 + i)t ? 10 ns uwr, lwr, iowr high-level width <54> t wwrh (0.5 + i + w as )t ? 10 ns uwr, lwr, iowr low-level width <55> t wwrl (1 + w + w d )t ? 10 ns data output setup time (to uwr, lwr, iowr ) <56> t sodwr (0.5 + w + w d )t ? 10 ns data output hold time (from uwr, lwr, iowr ) <57> t hwrod (0.5 + i)t ? 8 ns note for the first wait sampling when the wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. n = 0 to 7 5. i: idle state count 6. w as : address setup wait count based on the asc register 7. for the number of w and w d to be inserted, refer to 4.6.3 relationship between programmable wait and external wait . chapter 17 electrical specifications user's manual u14359ej5v1ud 577 (c) write timing (sram, externa l rom, external i/o) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait coun t based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7 <54> <52> <53> write write <51> <55> <56> csn (output) a0 to a25 (output) uwr, lwr, iowr rd, iord (output) <57> clkout (output) t1 tw t2 ti tasw <47> <48> wait (input) bcyst (output) <49> <50> (output) d0 to d15 (i/o) read write d0 to d15 (i/o) ube, lbe (output) chapter 17 electrical specifications user's manual u14359ej5v1ud 578 (d) dma flyby transfer timing (sram external i/o transfer) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8 ns wait hold time (from clkout ) <33> t hkw 0 ns rd low-level width <41> t wrdl (1.5 + w + w d )t ? 10 ns rd high-level width <42> t wrdh (0.5 + w as + i)t ? 10 ns delay time from address, csn to rd <43> t dard (0.5 + w as )t ? 10 ns delay time from rd to address <44> t drda it ns delay time from rd to data output <46> t drdod (0.5 + i)t ? 10 ns wait setup time (to address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (to bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note t ? 10 ns wait high-level width <50> t wwh t ? 10 ns delay time from address to iowr <51> t dawr (0.5 + w as )t ? 10 ns address setup time (to iowr ) <52> t sawr (1.5 + w + w d + w as )t ? 10 ns delay time from iowr to address <53> t dwra (1.5 + i)t ? 10 ns iowr high-level width <54> t wwrh (0.5 + i + w as )t ? 10 ns iowr low-level width <55> t wwrl (1 + w + w d )t ? 10 ns delay time from iowr to rd <58> t diwrrd 1.5t ? 10 ns delay time from dmaakm to iowr <59> t ddawr (0.5 + w as )t ? 10 ns delay time from iowr to dmaakm <60> t dwrda (1.5 + i)t ? 10 ns note for the first wait sampling when the number of wait s based on the dwc0 and dwc1 registers is zero. remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. n = 0 to 7, m = 0 to 3 5. i: idle state count 6. w as : address setup wait count based on the asc register 7. for the number of w and w d to be inserted, refer to 4.6.3 relationship be tween programmable wait and external wait . chapter 17 electrical specifications user's manual u14359ej5v1ud 579 (d) dma flyby transfer timing (sram external i/o transfer) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait coun t based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 <42> <41> <54> <51> <52> <43> <59> <55> <32> <33> <32> <33> <47> dmaakm (output) iord (output) iowr (output) rd (output) uwr, lwr (output) wait (input) bcyst (output) <48> csn (output) a0 to a25 (output) <49> clkout (output) t1 tw t2 tasw <44> <60> <53> <46> ti tf <58> <50> d0 to d15 (i/o) ube, lbe (output) chapter 17 electrical specifications user's manual u14359ej5v1ud 580 (e) dma flyby transfer timing (external i/o sram transfer) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8 ns wait hold time (from clkout ) <33> t hkw 0 ns iord low-level width <41> t wrdl (2 + w + w d )t ? 10 ns iord high-level width <42> t wrdh (1 + i + w as )t ? 10 ns delay time from address, csn to iord <43> t dard (0.5 + w as )t ? 10 ns delay time from iord to address <44> t drda (0.5 + i) t ? 10 ns delay time from iord to data output <46> t drdod (1 + i)t ? 10 ns wait setup time (to address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (to bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note t ? 10 ns wait high-level width <50> t wwh t ? 10 ns delay time from address to uwr, lwr <51> t dawr (0.5 + w as )t ? 10 ns address setup time (to uwr, lwr ) <52> t sawr (1.5 + w + w d + w as )t ? 10 ns delay time from uwr, lwr to address <53> t dwra (0.5 + i)t ? 10 ns uwr, lwr high-level width <54> t wwrh (0.5 + i + w as )t ? 10 ns uwr, lwr low-level width <55> t wwrl (1 + w + w d )t ? 10 ns delay time from uwr, lwr to iord <61> t dwrird t ? 10 ns delay time from dmaakm to iord <62> t ddard (0.5 + w as )t ? 10 ns delay time from iord to dmaakm <63> t drdda (0.5 + i)t ? 10 ns note for first wait sampling when wait count bas ed on the dwc0 and dwc1 registers is zero. remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. n = 0 to 7, m = 0 to 3 5. i: count of idle states insert ed when a write cycle follows a read cycle 6. w as : address setup wait count based on the asc register 7. for the number of w and w d to be inserted, refer to 4.6.3 relationship between programmable wait and external wait . chapter 17 electrical specifications user's manual u14359ej5v1ud 581 (e) dma flyby transfer timing (external i/o sram transfer) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait coun t based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 <54> <55> <53> <42> <63> <44> <41> <46> d0 to d15 (i/o) <51> <52> <62> <43> rd (output) dmaakm (output) iowr (output) iord (output) csn (output) a0 to a25 (output) uwr, lwr (output) <32> <33> <32> <33> <47> wait (input) bcyst (output) <48> <49> clkout (output) t1 tw t2 ti tasw tf <61> <50> ube, lbe (output) chapter 17 electrical specifications user's manual u14359ej5v1ud 582 (5) sram, external rom, and external i/o access timi ng (vis--vis busclk signal) (when bcp bit of bcp register = 1) (a) access timing (sram, external rom, external i/o) parameter symbol conditions min. max. unit wait setup time (to busclk ) <32> t swk 8 ns wait hold time (from busclk ) <33> t hkw 0.5t ? 4 ns wait hold time (from busclk ) <172> t hkw1 t + 2 ns data input setup time (to busclk ) <34> t skid 8 ns data input hold time (from busclk ) <35> t hkid 0.5t ? 4 ns data output delay time (from busclk ) <36> t dkod1 t ? 5 t + 8 ns data output delay time (from busclk ) <37> t dkod2 ? 5 +8 ns data float delay time (from busclk ) <38> t hkod 0.5t ? 4 0.5t + 8 ns remarks 1. maintain at least one of the data input hold times, t hrdid or t hkid . 2. t = internal system clock cycle (this does not mean x2 bus cycle). remarks 1. this is the timing when the number of waits based on the dwc0 and dwc1 registers is zero. 2. broken lines indicate high impedance. internal system clock t1 tw t2 t1 tw t2 wait (input) <32> <33> <32> <172> <37> busclk (output) <38> <34> <35> <36> <37> [ when read ] d0 to d15 (i/o) [when written] d0 to d15 (i/o) chapter 17 electrical specifications user's manual u14359ej5v1ud 583 (b) read timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit data input setup time (to address) <39> t said (2 + w + w d + w as )t ? 19 ns data input setup time (to rd) <40> t srdid (1.5 + w + w d )t ? 19 ns rd, iord low-level width <41> t wrdl (1.25 + w + w d )t ? 10 ns rd, iord high-level width <42> t wrdh (0.75 + w as + i)t ? 10 ns delay time from address, csn, to rd, iord <43> t dard (0.75 + w as )t ? 10 ns delay time from rd, iord to address <44> t drda it ns data input hold time (from rd, iord ) <45> t hrdid 0 ns delay time from rd, iord to data output <46> t drdod (0.25 + i)t ? 10 ns wait setup time (to address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (to bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note 0.5t ? 10 ns wait high-level width <50> t wwh t ? 10 ns data output hold time (from uwr, lwr, iowr ) <57> t hwrod (0.25 + i)t ? 8 ns note for the first wait sampling when the wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = busclk cycle (internal system clock/2) 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. maintain at least one of the data input hold times t hrdid or t hkid 5. n = 0 to 7 6. i: idle state count 7. w as : address setup wait count based on the asc register 8. for the number of w and w d to be inserted, refer to 4.6.3 relationship be tween programmable wait and external wait . chapter 17 electrical specifications user's manual u14359ej5v1ud 584 (b) read timing (sram, external rom, external i/o) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait coun t based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7 clkout (output) csn (output) a0 to a25 (output) uwr, lwr, iowr rd, iord (output) d0 to d15 (i/o) t1 tw t2 <45> <42> <41> <44> <46> <39> <40> <43> <47> <48> ti tasw <49> <57> <50> wait (input) bcyst (output) (output) ube, lbe (output) chapter 17 electrical specifications user's manual u14359ej5v1ud 585 (c) write timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit wait setup time (to address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (to bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note 0.5t ? 10 ns wait high-level width <50> t wwh t ? 10 ns delay time from address, csn to uwr, lwr, iowr <51> t dawr (0.75 + w as )t ? 10 ns address setup time (to uwr, lwr, iowr ) <52> t sawr (1.75 + w + w d + w as )t ? 10 ns delay time from uwr, lwr, iowr to address <53> t dwra (0.25 + i)t ? 10 ns uwr, lwr, iowr high-level width <54> t wwrh (1 + i + w as )t ? 10 ns uwr, lwr, iowr low-level width <55> t wwrl (1 + w + w d )t ? 10 ns data output setup time (to uwr, lwr, iowr ) <56> t sodwr (1.25 + w + w d )t ? 10 ns data output hold time (from uwr, lwr, iowr ) <57> t hwrod (0.25 + i)t ? 8 ns note for the first wait sampling when the wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = busclk cycle (internal system clock/2) 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. n = 0 to 7 5. i: idle state count 6. w as : address setup wait count based on the asc register 7. for the number of w and w d to be inserted, refer to 4.6.3 relationship between programmable wait and external wait . chapter 17 electrical specifications user's manual u14359ej5v1ud 586 (c) write timing (sram, externa l rom, external i/o) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait coun t based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7 <54> <52> <53> write write <51> <55> <56> csn (output) a0 to a25 (output) uwr, lwr, iowr rd, iord (output) <57> clkout (output) t1 tw t2 ti tasw <47> <48> wait (input) bcyst (output) <49> <50> (output) d0 to d15 (i/o) read write d0 to d15 (i/o) ube, lbe (output) chapter 17 electrical specifications user's manual u14359ej5v1ud 587 (6) page rom access timing (a) 8-bit bus width (halfword/word access) and 16-bit bus width (word access) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8 ns wait hold time (from clkout ) <33> t hkw 0 ns data input setup time (to clkout ) <34> t skid 8 ns data input hold time (from clkout ) <35> t hkid 0 ns off-page data input setup time (to address) <39> t said (2 + w + w d + w as )t ? 21 ns off-page data input setup time (to rd) <40> t srdid (1.5 + w + w d )t ? 21 ns data input hold time (from rd ) <45> t hrdid 0 ns delay time from rd to data output <46> t drdod (0.5 + i)t ? 10 ns on-page data input setup time (to address) <64> t soaid (2 + w + w pr + w as )t ? 21 ns remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. w pr : wait count based on the prc register 5. i: count of idle states insert ed when a write cycle follows a read cycle 6. w as : address setup wait count based on the asc register 7. maintain at least one of the data input hold times t hkid or t hrdid 8. for the number of w and w d to be inserted, refer to 4.6.3 relationship betw een programmable wait and external wait . chapter 17 electrical specifications user's manual u14359ej5v1ud 588 (a) 8-bit bus width (halfword/word access) and 16-bit bus width (word access) (2/2) note on-page and off-page addresses are as follows. prc register ma6 ma5 ma4 ma3 on-page address off-page address 0 0 0 0 a0 to a2 a3 to a25 0 0 0 1 a0 to a3 a4 to a25 0 0 1 1 a0 to a4 a5 to a25 0 1 1 1 a0 to a5 a6 to a25 1 1 1 1 a0 to a6 a7 to a25 remarks 1. this is the timing for the following case. wait count based on the dwc0 and dwc1 registers (tdw): 1 wait count based on the prc register (tprw): 1 wait count based on the asc register (tasw): 1 2. broken lines indicate high impedance. 3. n = 0 to 7 csn (output) clkout (output) t1 tdw tw t2 <39> <40> <35> <33> <32> <32> <33> d0 to d15 (i/o) uwr, lwr (output) rd (output) wait (input) bcyst (output) <34> to1 tprw tw to2 <64> <34> <35> <45> <33> <32> <33> <32> tasw tasw <46> address (output) note chapter 17 electrical specifications user's manual u14359ej5v1ud 589 (b) 8-bit bus width (byte access) and 16-bi t bus width (byte/halfword access) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8 ns wait hold time (from clkout ) <33> t hkw 0 ns data input setup time (to clkout ) <34> t skid 8 ns data input hold time (from clkout ) <35> t hkid 0 ns off-page data input setup time (to address) <39> t said (2 + w + w d + w as )t ? 21 ns off-page data input setup time (to rd) <40> t srdid (1.5 + w + w d )t ? 21 ns off-page rd low-level width <180> t wrdl (1.5 + w + w d )t ? 10 ns rd high-level width <181> t wrdh (0.5 + w as )t ? 10 ns data input hold time (from rd ) <45> t hrdid 0 ns delay time from rd to data output <46> t drdod (0.5 + i)t ? 10 ns on-page rd low-level width <182> t wordl (1.5 + w + w pr )t ? 10 ns on-page data input setup time (to address) <64> t soaid (2 + w + w pr + w as )t ? 21 ns on-page data input setup time (to rd) <183> t sordid (1.5 + w + w pr )t ? 21 ns remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. w pr : wait count based on the prc register 5. i: count of idle states insert ed when a write cycle follows a read cycle 6. w as : address setup wait count based on the asc register 7. maintain at least one of the data input hold times t hkid or t hrdid 8. for the number of w and w d to be inserted, refer to 4.6.3 relationship betw een programmable wait and external wait . chapter 17 electrical specifications user's manual u14359ej5v1ud 590 (b) 8-bit bus width (byte access) and 16-bi t bus width (byte/halfword access) (2/2) csn (output) clkout (output) t1 tdw tw t2 <39> <40> <35> <33> <32> <32> <33> d0 to d15 (i/o) uwr, lwr (output) rd (output) wait (input) bcyst (output) <34> to1 tprw tw to2 <64> <34> <35> <45> <33> <32> <33> <32> tasw tasw <46> address (output) note <180> <181> <183> <182> note on-page and off-page addresses are as follows. prc register ma6 ma5 ma4 ma3 on-page address off-page address 0 0 0 0 a0 to a2 a3 to a25 0 0 0 1 a0 to a3 a4 to a25 0 0 1 1 a0 to a4 a5 to a25 0 1 1 1 a0 to a5 a6 to a25 1 1 1 1 a0 to a6 a7 to a25 remarks 1. this is the timing for the following case. wait count based on the dwc0 and dwc1 registers (tdw): 1 wait count based on the prc register (tprw): 1 wait count based on the asc register (tasw): 1 2. broken lines indicate high impedance. 3. n = 0 to 7 chapter 17 electrical specifications user's manual u14359ej5v1ud 591 (7) dram access timing (a) read timing (edo dram) (1/3) parameter symbol conditions min. max. unit data input setup time (to clkout ) <34> t skid 8 ns data input hold time (from clkout ) <35> t hkid 0 ns delay time from oe to data output <46> t drdod (1 + i)t ? 10 ns read/write cycle time <65> t hpc (1 + w da + w cp )t ? 10 ns row address setup time <66> t asr 0.5t ? 10 ns row address hold time <67> t rah (0.5 + w rh )t ? 10 ns column address setup time <68> t asc 0.5t ? 10 ns column address hold time <69> t cah (0.5 + w da )t ? 10 ns w rp = 0 t ? 10 ns ras precharge time <70> t rp w rp 1 w rp t ? 10 ns column address read time (to ras ) <71> t ral (1.5 + w cp + w da )t ? 10 ns cas hold time <72> t csh (1.5 + w rh + w da )t ? 10 ns delay time from ras to column address <73> t rad (0.5 + w rh )t ? 10 ns delay time from ras to cas <74> t rcd (1 + w rh )t ? 10 ns w rp = 0 1.5t ? 10 ns cas to ras precharge time <75> t crp w rp 1 (0.5 + w rp )t ? 10 ns ras hold time from cas precharge <76> t rhcp (1.5 + w cp + w da )t ? 10 ns w rp = 0 (3 + w rh )t ? 10 ns we setup time (to cas ) <77> t rcs w rp 1 (2 + w rp + w rh )t ? 10 ns we hold time (from ras ) <78> t rrh (1 + i)t ? 10 ns we hold time (from cas ) <79> t rch (1.5 + i)t ? 10 ns ras pulse width off-page <80> t rasp (2 + w rh + w da )t ? 10 ns cas pulse width <81> t hcas (0.5 + w da )t ? 10 ns cas precharge time <82> t cp (0.5 + w cp )t ? 10 ns w rp = 0 (2.5 + w rh + w da )t ? 10 ns off-page <83> t och1 w rp 1 (1.5 + w rp + w rh + w da )t ? 10 ns cas hold time from oe on-page <84 > t och2 (0.5 + w cp + w da )t ? 10 ns access time to cas precharge <85> t acp (1.5 + w cp + w da )t ? 21 ns data input hold time (from cas ) <86> t dhc 0 ns cas access time <87> t cac (1 + w da )t ? 21 ns access time from column address <88> t aa (1.5 + w da )t ? 21 ns chapter 17 electrical specifications user's manual u14359ej5v1ud 592 (a) read timing (edo dram) (2/3) parameter symbol conditions min. max. unit w rp = 0 (3 + w rp + w rh + w da )t ? 21 ns off-page <89> t oea1 w rp 1 (2 + w rp + w rh + w da )t ? 21 ns output enable access time on-page <90> t oea2 (1 + w cp + w da )t ? 21 ns ras access time <91> t rac (2 + w rh + w da ) t ? 21 ns output buffer turn-off delay time (from oe) <92> t oez 0 ns cautions 1. at least one clock is inserted in w rp by default regardless of the setting of the rpc1n and rpc0n bits in the scrn regi ster (n = 1, 3, 4, or 6) 2. the wait signal cannot be controlled using the bcyst signal when using edo dram. remarks 1. t = t cyk 2. w da : wait count based on the dac1n and dac0n bits of the scrn register (n = 1, 3, 4, 6) 3. w cp : wait count based on the cpc1n and cpc0n bits of the scrn register (n = 1, 3, 4, 6) 4. w rp : wait count based on the rpc1n and rpc0n bits of the scrn register (n = 1, 3, 4, 6) 5. w rh : wait count based on the rhc1n and rhc0n bits of the scrn register (n = 1, 3, 4, 6) 6. i: idle state count chapter 17 electrical specifications user's manual u14359ej5v1ud 593 (a) read timing (edo dram) (3/3) clkout (output) <67> <66> <70> <80> <73> <71> <68> <69> <82> <75> <74> <72> <81> <76> a0 to a25 (output) d0 to d15 (i/o) trpw note 1 t1 trhw t2 tdaw tcpw tb tdaw te <88> <79> <81> <65> <77> <85> <87> <84> <83> <46> <34> <35> <34> <88> <91> <89> <90> <35> <92> rasn (output) lcas (output) ucas (output) we (output) oe (output) bcyst (output) wait (input) <78> <87> <86> data data row address column address column address note 2 notes 1. at least one clock is inserted in trpw. 2. during on-page access from other cycles while ras is low level. remarks 1. this is the timing for the following case. wait count based on the rpc1n and rpc0n bits of the scrn register (trpw): 1 wait count based on the rhc1n and rhc0n bits of the scrn register (trhw): 1 wait count based on the dac1n and dac0n bits of the scrn register (tdaw): 1 wait count based on the cpc1n and cpc0n bits of the scrn register (tcpw): 1 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6 chapter 17 electrical specifications user's manual u14359ej5v1ud 594 (b) write timing (edo dram) (1/2) parameter symbol conditions min. max. unit w cp = 0 (2 + w da )t ? 10 ns read/write cycle time <65> t hpc w cp 1 (1 + w da + w cp )t ? 10 ns row address setup time <66> t asr 0.5t ? 10 ns row address hold time <67> t rah (0.5 + w rh )t ? 10 ns column address setup time <68> t asc 0.5t ? 10 ns column address hold time <69> t cah (0.5 + w da )t ? 10 ns w rp = 0 t ? 10 ns ras precharge time <70> t rp w rp 1 w rp t ? 10 ns w cp = 0 (2.5 + w da )t ? 10 ns column address read time (to ras ) <71> t ral w cp 1 (1.5 + w cp + w da )t ? 10 ns cas hold time <72> t csh (1.5 + w rh + w da )t ? 10 ns delay time from ras to column address <73> t rad (0.5 + w rh )t ? 10 ns delay time from ras to cas <74> t rcd (1 + w rh )t ? 10 ns w rp = 0 1.5t ? 10 ns cas to ras precharge time <75> t crp w rp 1 (0.5 + w rp )t ? 10 ns w cp = 0 (2.5 + w da )t ? 10 ns ras hold time from cas precharge <76> t rhcp w cp 1 (1.5 + w cp + w da )t ? 10 ns ras pulse width off-page <80> t rasp (2 + w rh + w da )t ? 10 ns cas pulse width <81> t hcas (0.5 + w da )t ? 10 ns w cp = 0 1.5t ? 10 ns cas precharge time <82> t cp w cp 1 (0.5 + w cp )t ? 10 ns ras hold time <93> t rsh (1 + w da )t ? 10 ns w rp = 0 (2 + w rh )t ? 10 ns off-page <94> t wcs1 w rp 1 (1 + w rp + w rh )t ? 10 ns w cp = 0 t ? 10 ns we setup time (to cas ) on-page <95> t wcs2 w cp 1 w cp t ? 10 ns we hold time (from cas ) <96> t wch (1 + w da )t ? 10 ns off-page <97> t ds1 (1.5 + w rh )t ? 10 ns w cp = 0 1.5t ? 10 ns data setup time (to cas ) on-page <98> t ds2 w cp 1 (0.5 + w cp )t ? 10 ns data hold time (from cas ) <99> t dh (0.5 + w da )t ? 10 ns w cp = 0 (2 + w da )t ? 10 ns we pulse width on-page <100> t wp w cp 1 (1 + w da + w cp )t ? 10 ns w cp = 0 (2 + w da )t ? 10 ns we read time (to ras ) on-page <101> t rwl w cp 1 (1 + w da + w cp )t ? 10 ns w cp = 0 (1.5 + w da )t ? 10 ns we read time (to cas ) on-page <102> t cwl w cp 1 (0.5 + w da + w cp )t ? 10 ns chapter 17 electrical specifications user's manual u14359ej5v1ud 595 cautions 1. at least one clock is inserted in w rp by default regardless of the setting of the rpc1n and rpc0n bits in the scrn regi ster (n = 1, 3, 4, 6). 2. at least one clock is inserted in w cp by default regardless of the setting of the cpc1n and cpc0n bits in the scrn regi ster (n = 1, 3, 4, 6). 3. the wait signal cannot be controlled using the bcyst signal when using edo dram. remarks 1. t = t cyk 2. w da : wait count based on the dac1n and dac0n bits of the scrn register (n = 1, 3, 4, 6) 3. w cp : wait count based on the cpc1n and cpc0n bits of the scrn register (n = 1, 3, 4, 6) 4. w rp : wait count based on the rpc1n and rpc0n bits of the scrn register (n = 1, 3, 4, 6) 5. w rh : wait count based on the rhc1n and rhc0n bits of the scrn register (n = 1, 3, 4, 6) chapter 17 electrical specifications user's manual u14359ej5v1ud 596 (b) write timing (edo dram) (2/2) clkout (output) <67> <70> <80> <73> <71> <68> <69> <68> <82> <69> <75> <74> <72> <81> <93> <76> a0 to a25 (output) <101> <81> <102> <65> <94> <95> <96> <96> <100> <99> <98> <99> <97> d0 to d15 (i/o) trpw t1 trhw t2 tdaw tcpw tb tdaw te rasn (output) lcas (output) ucas (output) we (output) oe (output) rd (output) bcyst ( output) wait (input) <66> note 2 read write d0 to d15 (i/o) write write data data data data note 1 note 1 row address column address column address notes 1. at least one clock is inserted in trpw and tcpw. 2. during on-page access from other cycles while ras is low level. remarks 1. this is the timing for the following case. wait count based on the rpc1n and rpc0n bits of the scrn register (trpw): 1 wait count based on the rhc1n and rhc0n bits of the scrn register (trhw): 1 wait count based on the dac1n and dac0n bits of the scrn register (tdaw): 1 wait count based on the cpc1n and cpc0n bits of the scrn register (tcpw): 1 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6 chapter 17 electrical specifications user's manual u14359ej5v1ud 597 (c) dma flyby transfer timing (edo dram external i/o transfer) (1/3) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8 ns wait hold time (from clkout ) <33> t hkw 0 ns delay time from oe to data output <46> t drdod (1 + i)t ? 10 ns delay time from iowr to address <53> t dwra 1.5t ? 10 ns w rp = 0 (3 + w rh + w da + w)t ? 10 ns iowr low-level width <55> t wwrl w rp 1 (2 + w rp + w da + w rh + w)t ? 10 ns delay time from iowr to oe <58> t dwrrd t ? 10 ns row address setup time <66> t asr 0.5t ? 10 ns row address hold time <67> t rah (0.5 + w rh )t ? 10 ns column address setup time <68> t asc 0.5t ? 10 ns column address hold time <69> t cah (2.5 + w da + w)t ? 10 ns w rp = 0 t ? 10 ns ras precharge time <70> t rp w rp 1 w rp t ? 10 ns column address read time (to ras) <71> t ral (3.5 + w cp + w da + w)t ? 10 ns cas hold time <72> t csh (3 + w rh + w da + w)t ? 10 ns delay time from ras to column address <73> t rad (0.5 + w rh )t ? 10 ns delay time from ras to cas <74> t rcd (1 + w rh )t ? 10 ns w rp = 0 2t ? 10 ns cas to ras precharge time <75> t crp w rp 1 (1 + w rp )t ? 10 ns ras hold time from cas precharge <76> t rhcp (4 + w cp + w da + w)t ? 10 ns w rp = 0 (3 + w rh )t ? 10 ns we setup time (to cas ) <77> t rcs w rp 1 (2 + w rp + w rh )t ? 10 ns we hold time (from ras ) <78> t rrh 0 ns we hold time (from cas ) <79> t rch t ? 10 ns ras pulse width off-page <80> t rasp (4 + w rh + w da + w) t ? 10 ns cas precharge time <82> t cp (1 + w cp )t ? 10 ns w rp = 0 (4 + w rh + w da + w)t ? 10 ns off-page <83> t och1 w rp 1 (3 + w rp + w rh + w da + w)t ? 10 ns oe to cas hold time on-page <84> t och2 (2 + w cp + w da + w)t ? 10 ns output buffer turn-off delay time (from oe ) <92> t oez 0 ns ras hold time <93> t rsh (3 + w da + w) t ? 10 ns w rp = 0 (5.5 + w rh + w da + w)t ? 10 ns read/write cycle time <103> t rc w rp 1 (4.5 + w rp + w rh + w da + w)t ? 10 ns cas pulse width <104> t cas (2 + w da + w)t ? 10 ns w rp = 0 (3 + w rh )t ? 10 ns cas precharge time <105> t cpn w rp 1 (2 + w rp + w rh )t ? 10 ns high-speed page mode cycle time <106> t pc (3 + w cp + w da + w)t ? 10 ns chapter 17 electrical specifications user's manual u14359ej5v1ud 598 (c) dma flyby transfer timing (edo dram external i/o transfer) (2/3) parameter symbol conditions min. max. unit w rp = 0 (2.5 + w rh )t ? 10 ns delay time from dmaakm to cas <107> t ddacs w rp 1 (1.5 + w rp + w rh )t ? 10 ns w rp = 0 (2 + w rh )t ? 10 ns delay time from iowr to cas <108> t drdcs w rp 1 (1 + w rp + w rh )t ? 10 ns output buffer turn-off delay time (from cas ) <109> t off 0 ns cautions 1. at least one clock is inserted in w rp by default regardless of the setting of the rpc1n and rpc0n bits in the scrn regi ster (n = 1, 3, 4, 6). 2. the wait signal cannot be controlled using the bcyst signal when using edo dram. remarks 1. t = t cyk 2. w: wait count based on wait 3. w da : wait count based on the dac1n and dac0n bits of the scrn register (n = 1, 3, 4, 6) 4. w cp : wait count based on the cpc1n and cpc0n bits of the scrn register (n = 1, 3, 4, 6) 5. w rp : wait count based on the rpc1n and rpc0n bits of the scrn register (n = 1, 3, 4, 6) 6. w rh : wait count based on the rhc1n and rhc0n bits of the scrn register (n = 1, 3, 4, 6) 7. i: idle state count 8. m = 0 to 3 chapter 17 electrical specifications user's manual u14359ej5v1ud 599 (c) dma flyby transfer timing (edo dram external i/o transfer) (3/3) clkout (output) t1 trhw t2 tdaw tw tf te tcpw tb tdaw tw tf <66> <69> a0 to a23 (output) <70> <80> d0 to d15 (i/o) <71> <103> <72> <74> <104> <82> <76> <93> <78> <75> <105> <83> <106> <84> <58> <107> <77> <109> <55> <32> <32> <32> <33> <33> <92> <46> <33> <108> <79> <67> <68> <73> rasn (output) lcas (output) ucas (output) oe (output) dmaakm (output) we (output) iord (output) iowr (output) bcyst (output) wait (input) <53> te trpw note row address column address column address data data note at least one clock is inserted in trpw. remarks 1. this is the timing for the following case. wait count based on the rpc1n and rpc0n bi ts of the scrn register (trpw): 1 wait count based on the rhc1n and rhc0n bi ts of the scrn register (trhw): 1 wait count based on the dac1n and dac0n bi ts of the scrn register (tdaw): 1 wait count based on the cpc1n and cpc0n bi ts of the scrn register (tcpw): 1 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6, m = 0 to 3 chapter 17 electrical specifications user's manual u14359ej5v1ud 600 (d) dma flyby transfer timing (external i/o edo dram transfer) (1/3) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8 ns wait hold time (from clkout ) <33> t hkw 0 ns iord low-level width <41> t wrdl (2 + w rh + w da + w) t ? 10 ns iord high-level width <42> t wrdh t ? 10 ns delay time from iord to address <44> t drda (0.5 + i) t ? 10 ns row address setup time <66> t asr 0.5t ? 10 ns row address hold time <67> t rah (0.5 + w rh )t ? 10 ns column address setup time <68> t asc 0.5t ? 10 ns column address hold time <69> t cah (1.5 + w da )t ? 10 ns w rp = 0 t ? 10 ns ras precharge time <70> t rp w rp 1 w rp t ? 10 ns column address read time (to ras) <71> t ral (2.5 + w cp + w da + w)t ? 10 ns cas hold time <72> t csh (2 + w rh + w da + w)t ? 10 ns delay time from ras to column address <73> t rad (0.5 + w rh ) t ? 10 ns delay time from ras to cas <74> t rcd (1 + w rh + w)t ? 10 ns w rp = 0 2t ? 10 ns cas to ras precharge time <75> t crp w rp 1 (1 + w rp )t ? 10 ns ras hold time from cas precharge <76> t rhcp (4 + w cp + w da + w)t ? 10 ns ras pulse width off-page <80> t rasp (3 + w rh + w da + w)t ? 10 ns cas precharge time <82> t cp (1 + w cp + w)t ? 10 ns ras hold time <93> t rsh (2 + w da )t ? 10 ns w rp = 0 (4.5 + w rh + w da + w)t ? 10 ns read/write cycle time <103> t rc w rp 1 (3.5 + w rp + w rh + w da + w)t ? 10 ns cas pulse width <104> t cas (1 + w da )t ? 10 ns w rp = 0 (3 + w rh + w)t ? 10 ns cas precharge time <105> t cpn w rp 1 (2 + w rp + w rh + w)t ? 10 ns high-speed page mode cycle <106> t pc (2 + w cp + w da + w)t ? 10 ns w rp = 0 (2.5 + w rh + w)t ? 10 ns delay time from dmaakm to cas <107> t ddacs w rp 1 (1.5 + w rp + w rh + w)t ? 10 ns w rp = 0 (2 + w rh + w)t ? 10 ns delay time from iord to cas <108> t drdcs w rp 1 (1 + w rp + w rh + w)t ? 10 ns we read time (to ras ) <110> t rwl (3 + w da + w)t ? 10 ns we read time (to cas ) <111> t cwl (2 + w da + w)t ? 10 ns we pulse width <112> t wp (2 + w da + w)t ? 10 ns off-page <113> t wcs1 (2 + w rh + w)t ? 10 ns we setup time (to cas ) on-page <114> t wcs2 t ? 10 ns chapter 17 electrical specifications user's manual u14359ej5v1ud 601 (d) dma flyby transfer timing (external i/o edo dram transfer) (2/3) parameter symbol conditions min. ma x. u nit we hold time (from cas ) <115> t wch (1 + w da )t ? 10 ns delay time from we to iord <116> t dwerd 0 ns cautions 1. at least one clock is inserted in w rp by default regardless of the setting of the rpc1n and rpc0n bits in the scrn register (n = 1, 3, 4, 6). 2. at least one clock is inserted in w cp by default regardless of the setting of the cpc1n and cpc0n bits in the scrn register (n = 1, 3, 4, 6). 3. the wait signal cannot be controlled using the bcyst signal when using edo dram. remarks 1. t = t cyk 2. w: wait counts based on wait 3. w da : wait count based on the dac1n and dac0n bits of the scrn register (n = 1, 3, 4, 6) 4. w cp : wait count based on the cpc1n and cpc0n bits of the scrn register (n = 1, 3, 4, 6) 5. w rp : wait count based on the rpc1n and rpc0n bits of the scrn register (n = 1, 3, 4, 6) 6. w rh : wait count based on the rhc1n and rhc0n bits of the scrn register (n = 1, 3, 4, 6) 7. i: idle state count 8. m = 0 to 3 chapter 17 electrical specifications user's manual u14359ej5v1ud 602 (d) dma flyby transfer timing (external i/o edo dram transfer) (3/3) clkout (output) trpw t1 trhw tw t2 tdaw te tcpw tw tb tdaw te <67> <66> <69> a0 to a23 (output) <80> d0 to d15 (i/o) <73> <71> <70> <103> <75> <72> <74> <104> <82> <93> <105> <106> <41> <108> <32> <32> <33> <33> <33> <113> <112> <111> <110> <115> <107> <32> <76> <114> <116> <42> rasn (output) lcas (output) ucas (output) oe (output) rd (output) we (output) dmaakm (output) iord (output) iowr (output) bcyst (output) wait (input) <44> row address column address column address note note <68> data data note at least one clock is inserted in trpw and tcpw. remarks 1. this is the timing for the following case. wait count based on the rpc1n and rpc0n bits of the scrn register (trpw): 1 wait count based on the rhc1n and rhc0n bits of the scrn register (trhw): 1 wait count based on the dac1n and dac0n bits of the scrn register (tdaw): 1 wait count based on the cpc1n and cpc0n bits of the scrn register (tcpw): 1 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6, m = 0 to 3 chapter 17 electrical specifications user's manual u14359ej5v1ud 603 (e) cbr refresh timing parameter symbol conditions min. ma x. u nit ras precharge time <70> t rp (1.5 + w rrw )t ? 10 ns ras pulse width <117> t ras (1.5 + w rcw note )t ? 10 ns cas hold time <118> t chr (0.5 + w rcw note )t ? 10 ns refrq pulse width <119> t wrfl (3 + w rrw + w rcw note )t ? 10 ns ras precharge cas hold time <120> t rpc (2.5 + w rrw )t ? 10 ns refrq active delay time (from clkout ) <121> t dkrf 2 13 ns refrq inactive delay time (from clkout ) <122> t hkrf 2 13 ns cas setup time <123> t csr t ? 10 ns note at least one clock is inserted in w rcw by default, regardless of the settings of the rcw0 to rcw2 bits of the rwc register. remarks 1. t = t cyk 2. w rrw : wait count based on the rrw0 and rrw1 bits of the rwc register 3. w rcw : wait count based on the rcw0 to rcw2 bits of the rwc register clkout (output) <70> trrw t1 t2 trcw trcw t3 t4 <119> <122> <117> <120> <123> <118> <120> rasn (output) refrq (output) lcas (output) ucas (output) <121> note 1 note 2 note 2 ti ti notes 1. at least one clock is inserted in trcw, regardless of the settings of the rcw0 to rcw2 bits of the rwc register. 2. idle state (ti) independent of the setting of the bcc register remarks 1. this is the timing for the following case. wait count based on the rrw0 and rrw1 bits of the rwc register (trrw): 1 wait count based on the rcw0 to rcw2 bi ts of the rwc register (trcw): 2 2. n = 0 to 7 chapter 17 electrical specifications user's manual u14359ej5v1ud 604 (f) cbr self-refresh timing parameter symbol conditions min. max. unit refrq active delay time (from clkout ) <121> t dkrf 2 13 ns refrq inactive delay time (from clkout ) <122> t hkrf 2 13 ns cas hold time <124> t chs ? (w rcw t ? 10) ns w rp = 0 (3 + 2w srw )t ? 10 ns ras precharge time <125> t rps w rp 1 (2 + 2w srw + w rpw )t ? 10 ns remarks 1. t = t cyk 2. w srw : wait count based on the srw0 to srw2 bits of the rwc register 3. w rcw : wait count based on the rcw0 to rcw2 bits of the rwc register 4. w rpw : wait count based on the rrw0 and rrw1 bits of the rwc register clkout (output) trrw trcw <122> tsrw <121> <125> <124> tsrw t1 refrq (output) rasn (output) lcas (output) ucas (output) note note at least one clock is inserted in trcw, regardless of the settings of the rcw0 to rcw2 bits of the rwc register. remarks 1. this is the timing for the following case. wait count based on the rrw0 and rrw1 bi ts of the rwc register (trrw): 1 wait count based on the rcw0 to rcw2 bi ts of the rwc register (trcw): 1 wait count based on the srw0 to srw2 bits of the rwc register (tsrw): 1 (twice the number of waits as the set value are inserted) 2. n = 1, 3, 4, 6 chapter 17 electrical specifications user's manual u14359ej5v1ud 605 ( 8) sdram access timing (a) read timing (sdram access) (1/2) parameter symbol conditions min. max. unit address delay time (from sdclk ) <126> t dka2 2 13 ns bcyst delay time (from sdclk ) <127> t dkbc 2 13 ns csn delay time (from sdclk ) <128> t dkcs 2 13 ns sdras delay time (from sdclk ) <129> t dkras 2 13 ns sdcas delay time (from sdclk ) <130> t dkcas 2 13 ns udqm, ldqm delay time (from sdclk ) <131> t dkdqm 2 13 ns sdcke delay time (from sdclk ) <132> t dkcke 2 13 ns data input setup time (at sdram read, to sdclk ) <133> t sdrmk 8 ns data input hold time (at sdram read, from sdclk ) <134> t hkdrm 0 ns delay time from sdclk to data output <135> t dsdod (1 + i) t ? 5 ns remarks 1. t = t cyk2 2. i = idle state count 3. n = 1, 3, 4, 6 chapter 17 electrical specifications user's manual u14359ej5v1ud 606 (a) read timing (sdram access) (2/2) remarks 1. wait count based on the bcw1n and bcw0n bi ts of the scrn register (tbcw): 2 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6 sdclk (output) tw tact tbcw tread tlate tlate <126> bcyst (output) csn (output) sdcas (output) sdras (output) we (output) oe (output) ldqm (output) udqm (output) d0 to d15 (i/o) sdcke (output) rd (output) a10 (output) a0 to a9 (output) <126> <126> <126> <127> <128> <126> <126> <126> <126> <126> <129> <130> <131> <131> <131> <133> <134> <127> <128> <129> <130> <131> <126> data address bank address (output) <135> bank address and addresses other than a10 and a0 to a9 (output) address column address <132> <132> address address bank address row address row address chapter 17 electrical specifications user's manual u14359ej5v1ud 607 (b) write timing (sdram access) (1/2) parameter symbol conditions min. max. unit address delay time (from sdclk ) <126> t dka2 2 13 ns bcyst delay time (from sdclk ) <127> t dkbc 2 13 ns csn delay time (from sdclk ) <128> t dkcs 2 13 ns sdras delay time (from sdclk ) <129> t dkras 2 13 ns sdcas delay time (from sdclk ) <130> t dkcas 2 13 ns udqm, ldqm delay time (from sdclk ) <131> t dkdqm 2 13 ns sdcke delay time (from sdclk ) <132> t dkcke 2 13 ns we delay time (from sdclk ) <136> t dkwe 2 13 ns data output delay time (from sdclk ) <137> t dkdt 2 13 ns data float delay time (from sdclk ) <138> t hzkdt 2 13 ns remark n = 1, 3, 4, 6 chapter 17 electrical specifications user's manual u14359ej5v1ud 608 (b) write timing (sdram access) (2/2) tw tact tbcw twr1 twr2 twr3 <126> <126> <126> <126> <127> <128> <126> <126> <126> <126> <126> <129> <130> <136> <131> <131> <131> <137> <138> <127> <128> <129> <130> <136> <131> <126> <132> <132> sdclk (output) bcyst (output) csn (output) sdcas (output) sdras (output) we (output) oe (output) ldqm (output) udqm (output) d0 to d15 (i/o) sdcke (output) rd (output) a10 (output) a0 to a9 (output) bank address (output) bank address and addresses other than a10 and a0 to a9 (output) data address address address address column address bank address row address row address remarks 1. wait count based on the bcw1n and bcw0n bi ts of the scrn register (tbcw): 2 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6 chapter 17 electrical specifications user's manual u14359ej5v1ud 609 (9) dmac timing parameter symbol conditions min. max. unit dmarqn setup time (to clkout ) <139> t sdrk 8 ns <140> t hkdr1 after inactive (from clkout ) 3 ns dmarqn hold time <141> t hkdr2 until dmaakn ns second dma request disable timing in single transfer <142> t akdr 2t ? 21 ns dmaakn output delay time (from clkout ) <143> t dkda 2 13 ns dmaakn output hold time (from clkout ) <144> t hkda 2 13 ns tcn output delay time (from clkout ) <145> t hktc 2 13 ns tcn output hold time (from clkout ) <146> t hktc 2 13 ns remarks 1. t = t cyk 2. n = 0 to 3 clkout (output) <141> <143> <144> <145> <139> dmaakn (output) dmarqn (input) tcn (output) <140> <146> <139> <142> remarks 1. in 2-cycle transfer, the tcn signal is output in the write cycle. 2. n = 0 to 3 chapter 17 electrical specifications user's manual u14359ej5v1ud 610 (10) bus hold timing (1/2) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) <147> t shrk 8 ns hldrq hold time (from clkout ) <148> t hkhr 3 ns delay time from clkout to hldak <149> t dkha 2 13 ns hldrq high-level width <150> t whqh t + 3 ns hldak low-level width <151> t whal t ? 11 ns delay time from hldak to bus float <152> t dkcf 0 ns delay time from hldak to bus output <153> t dhac 2 13 ns delay time from hldrq to hldak <154> t dhqha1 2t ns delay time from hldrq to hldak <155> t dhqha2 t 2t + 10 ns remark t = t cyk chapter 17 electrical specifications user's manual u14359ej5v1ud 611 (10) bus hold timing (2/2) clkout (output) ti d0 to d15 (i/o) <147> th th th ti t1 <148> <148> <147> <154> <149> <151> <155> <150> <149> <152> <153> a0 to a25 (output) address data hldrq (input) hldak (output) csn/rasn (output) bcyst (output) rd (output) we (output) lcas (output) ucas (output) wait (input) <147> undefined remarks 1. broken lines indicate high impedance. 2. n = 0 to 7 chapter 17 electrical specifications user's manual u14359ej5v1ud 612 (11) interrupt timing parameter symbol conditions min. max. unit nmi high-level width <156> t wnih 500 ns nmi low-level width <157> t wnil 500 ns intp0nm high-level width <158> t wit0h 3t + 500 ns intp0nm low-level width <159> t wit0l 3t + 500 ns intp1nm high-level width <160> t wit1h 500 ns intp1nm low-level width <161> t wit1l 500 ns remarks 1. intp0nm: n = 0 to 3, m = 0, 1 intp1nm: n = 0 to 3, m = 0 to 3 2. t = t cyk <156> <157> nmi (input) <158> <159> intp0nm (input) <160> <161> intp1nm (input) remark intp0nm: n = 0 to 3, m = 0, 1 intp1nm: n = 0 to 3, m = 0 to 3 (12) rpu timing parameter symbol conditions min. max. unit ti0n0 high-level width <162> t wtih 3t + 500 ns ti0n0 low-level width <163> t wtil 3t + 500 ns remarks 1. n = 0 to 3 2. t = t cyk remark n = 0 to 3 <162> <163> ti0n0 (input) chapter 17 electrical specifications user's manual u14359ej5v1ud 613 (13) csi0 to csi2 timing (1/3) (a) master mode parameter symbol conditions min. max. unit sckn cycle <164> t cysk1 output 320 ns sckn high-level width <165> t wsk1h output 0.5t cysk1 ? 20 ns sckn low-level width <166> t wsk1l output 0.5t cysk1 ? 20 ns sin setup time (to sckn ) 30 ns sin setup time (to sckn ) <167> t ssisk 30 ns sin hold time (from sckn ) 30 ns sin hold time (from sckn ) <168> t hsksi 30 ns son output delay time (from sckn ) 30 ns son output delay time (from sckn ) <169> t dskso 30 ns son output hold time (from sckn ) 0.5t cysk1 ? 5 ns son output hold time (from sckn ) <170> t hskso 0.5t cysk1 ? 5 ns remark n = 0 to 2 (b) slave mode parameter symbol conditions min. max. unit sckn cycle <164> t cysk1 input 200 ns sckn high-level width <165> t wsk1h input 90 ns sckn low-level width <166> t wsk1l input 90 ns sin setup time (to sckn ) 50 ns sin setup time (to sckn ) <167> t ssisk 50 ns sin hold time (from sckn ) 50 ns sin hold time (from sckn ) <168> t hsksi 50 ns son output delay time (from sckn ) 50 ns son output delay time (from sckn ) <169> t dskso 50 ns son output hold time (from sckn ) t wsk1h ns son output hold time (from sckn ) <170> t hskso t wsk1h ns remark n = 0 to 2 chapter 17 electrical specifications user's manual u14359ej5v1ud 614 (13) csi0 to csi2 timing (2/3) (c) timing when ckpn, dapn bits of csicn register = 00 <164> <166> <165> <167> <168> <169> <170> sin (input) son (output) sckn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 (d) timing when ckpn, dapn bits of csicn register = 01 remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 <167> <168> <170> sin (input) son (output) input data output data <164> <166> <165> sckn (i/o) <169> chapter 17 electrical specifications user's manual u14359ej5v1ud 615 (13) csi0 to csi2 timing (3/3) (e) timing when ckpn, dapn bits of csicn register = 10 remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 (f) timing when ckpn, dapn bits of csicn register = 11 remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 <164> <166> <165> <167> <168> <169> <170> input data output data sckn (i/o) son (output) sin (input) <167> <168> <170> sin (input) son (output) input data output data <164> <166> <165> sckn (i/o) <169> chapter 17 electrical specifications user's manual u14359ej5v1ud 616 a/d converter characteristics (t a = ? 40 to +85 c, v dd = cv dd = av dd = 3.0 to 3.6 v, v ss = cv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution ? 10 bit overall error note 1 ? 0.49 %fsr quantization error ? 1/2 lsb conversion time t conv 5 10 s sampling time t samp conversion clock note 2 /6 clocks zero-scale error note 1 ? 0.49 %fsr full-scale error note 3 ? 0.49 %fsr integral linearity error note 3 ? 4 lsb differential linearity error note 3 ? 4 lsb analog input voltage v wasn ? 0.3 av ref + 0.3 v av ref input voltage av ref av ref = av dd 3.0 3.6 v av dd supply current ai dd 10 ma notes 1. excluding quantization error ( 0.05 %fsr) 2. conversion clock is the number of clocks set by the adm1 resister. 3. excluding quantization error ( 0.5 lsb) remark lsb: least significant bit fsr: full scale range % fsr is the ratio to the full-scale value. chapter 17 electrical specifications user's manual u14359ej5v1ud 617 17.2 flash memory programming mode ( pd70f3107a and 70f3107a(a) only) basic characteristics (t a = 10 to 40 c (during rewrite), t a = ? 40 to +85 c (except during rewrite), v dd = cv dd = av dd = 3.0 to 3.6 v, v ss = cv ss = av ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit operating frequency f xx 4 50 mhz v pp1 during flash memory programming 7.5 7.8 8.1 v v ppl v pp low-level detection ? 0.5 0.2v dd v v ppm v pp , v dd level detection 0.65v dd v dd + 0.3 v v pp supply voltage v pph v pp high-voltage level detection 7.5 7.8 8.1 v v dd supply current i dd v pp = v pp1 4.8fxx + 45 ma v pp supply current i pp v pp = 7.8 v 100 ma step erase time t er note 1 0.398 0.4 0.402 s overall erase time per area t era when the step erase time = 0.4 s note 2 40 s/area writeback time t wb note 3 0.99 1 1.01 ms number of writebacks per writeback command c wb when the writeback time = 1 ms note 4 300 c ount/ writeback command number of erase/writebacks c erwb 16 count step writing time t wt note 5 18 20 22 s overall writing time per word t wtw when the step writing time = 20 s (1 word = 4 bytes) note 6 20 200 s/word notes 1. the recommended setting value of the step erase time is 0.4 s. 2. the prewrite time prior to erasure and the eras e verify time (writeback time) are not included. 3. the recommended setting value of the writeback time is 1 ms. 4. writeback is executed once by t he issuance of the writeback comm and. therefore, the retry count must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step writing time is 20 s. 6. 100 s is added to the actual writing time per word. th e internal verify time during and after the writing is not included. remarks 1. when the pg-fp4 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. do not change the settings otherwise specified. 2. area 0 = 00000h to 1ffffh, area 1 = 20000h to 3ffffh chapter 17 electrical specifications user's manual u14359ej5v1ud 618 basic characteristics (t a = 10 to 40 c (during rewrite), t a = ? 40 to +85 c (except during rewrite), v dd = cv dd = av dd = 3.0 to 3.6 v, v ss = cv ss = av ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit note 2 20 number of rewrites per area c erwr 1 erase + 1 write after erase = 1 rewrite note 1 note 3 100 count/area notes 1. when writing initially to shipped products, it is counted as one rewrite for both ?erase to write? and ?write only?. example (p: write, e: erase) shipped product ???? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites 2. lqfp package: lot number 0124pxxxx or earlier fbga package: lot number 0123pxxxx or earlier 3. lqfp package: lot number 0125pxxxx or later fbga package: lot number 0124pxxxx or later remarks 1. when the pg-fp4 is used, a time parameter require d for writing/erasing by downloading parameter files is automatically set. do not c hange the settings otherwise specified. 2. area 0 = 00000h to 1ffffh, area 1 = 20000h to 3ffffh 3. 01 indicates the year of manufacture and 23, 24, 25 indicate the week of manufacture. the products that are guarant eed for 100 rewrites are as follows. lqfp package: products manufactured in 25th week or later (25, 26, 27?) fbga package: products manufactured in 24th week or later (24, 25, 26?) chapter 17 electrical specifications user's manual u14359ej5v1ud 619 serial write operation characteristics parameter symbol conditions min. typ. max. unit v dd to v pp set time <171> t drpsr 10 s v pp to reset set time <172> t psrrf 1 s reset to v pp count start time <173> t rfof v pp = 7.8 v 10t + 1500 ns count execution time <174> t count 15 ms v pp counter high-level width <175> t ch 1 s v pp counter low-level width <176> t cl 1 s v pp counter rise time <177> t r 1 s v pp counter fall time <178> t f 1 s v pp to v dd reset time <179> t pfdr 10 s remark t = t cyk <171> <173> <176> <175> <174> <178> <177> v dd 0 v v dd 0 v v dd v pph 0 v v dd v pp reset (input) <172> <179> user?s manual u14359ej5v1ud 620 chapter 18 package drawings 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 + 4 ? 3 g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b chapter 18 package drawings user?s manual u14359ej5v1ud 621 161-pin plastic fbga (13x13) item millimeters d e 13.00 0.10 13.00 0.10 w 0.20 e x 0.08 y 0.10 a 1.48 0.10 a1 0.35 0.06 a2 1.13 0.80 index mark a a2 a1 ze zd y1 0.20 zd 1.30 ze 1.30 b 0.50 + 0.05 ? 0.10 p161f1-80-en4-1 a b c d e f g h j k l m n p 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b s y1 e s y s s w a s w b s b x ab m e d user?s manual u14359ej5v1ud 622 chapter 19 recommended soldering conditions the v850e/ma1 should be soldered and mount ed under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) chapter 19 recommended soldering conditions user?s manual u14359ej5v1ud 623 table 19-1. surface mounting type soldering conditions (1) pd703106agj-xxx-uen: 144-pin plastic lqfp (fine pitch) (20 20) pd703107agj-xxx-uen: 144-pin plastic lqfp (fine pitch) (20 20) pd70f3107agj-uen: 144-pin plastic lqfp (fine pitch) (20 20) pd70f3107agj(a)-uen: 144-pin plastic lqfp (fine pitch) (20 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125c for 10 to 72 hours) ir35-103-2 vps package peak temperature: 215c, time: 25 to 40 seconds (at 200c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125c for 10 to 72 hours) vp15-103-2 partial heating pin temperature: 350c max ., time: 3 seconds max. (per pin row) ? (2) pd703106af1-xxx-en4: 161-pin plastic fbga (13 13) pd703107af1-xxx-en4: 161-pin plastic fbga (13 13) pd70f3107af1-en4: 161-pin plastic fbga (13 13) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) ir35-107-2 vps package peak temperature: 215c, time: 25 to 40 seconds (at 200c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) vp15-107-2 note after opening the dry pack, store it at 25c or le ss and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating). remark the soldering conditions for t he following product is undetermined. ? pd703103agj-uen: 144-pin plastic lqfp (fine pitch) (20 20) ? pd703105agj-xxx-uen: 144-pin plasti c lqfp (fine pitch) (20 20) ? pd703106agj(a)-xxx-uen: 144-pin plas tic lqfp (fine pitch) (20 20) ? pd703107agj(a)-xxx-uen: 144-pin plas tic lqfp (fine pitch) (20 20) user?s manual u14359ej5v1ud 624 appendix a notes on target system design the following shows a diagram of t he connection conditions between the in -circuit emulator option board and conversion connector. design your system making allowanc es for conditions such as the form of parts mounted on the target system as shown below. appendix a notes on target system design user?s manual u14359ej5v1ud 625 figure a-1. 144-pin plastic lqfp (fine pitch) (20 20) side view target system nqpack144sd yqpack144sd 206.26 mm note in-circuit emulator option board conversion connector ie-703107-mc-em1 in-circuit emulator ie-v850e-mc-a yqguide note yqsocket144sdn (sold separately) can be inserted here to adjus t the height (height: 3.2 mm). top view target system yqpack144sd, nqpack144sd, yqguide ie-703107-mc-em1 ie-v850e-mc-a connection condition diagram 13.3 mm 27.205 mm 21.58 mm 17.99 mm 75 mm 31.84 mm target system nqpack144sd yqpack144sd ie-703107-mc-em1 connect to ie-v850e-mc-a. yqguide appendix a notes on target system design user?s manual u14359ej5v1ud 626 figure a-2. 161-pin plastic fbga (13 13) side view 206.26 mm in-circuit emulator option board conversion connector ie-703107-mc-em1 in-circuit emulator ie-v850e-mc-a target system cssocket161a1413n01n note 2 note 1 csice161a1413n02 lspack161a1413n01 notes 1. the cssocket161a1413n01s1 (sold separat ely) can be inserted here to adjust the height (height: 3.2 mm). 2. this is a target socket without guides. remove su ffix n from the part number when a target socket with guides is needed. top view ie-703107-mc-em1 ie-v850e-mc-a target system lspack161a1413n01, cssocket161a1413n01n, yqguide connection condition diagram 4.2 mm 15.7 mm 27.205 mm 17.99 mm 75 mm 31.84 mm target system csice161a1413n02 lspack161a1413n01 ie-703107-mc-em1 connect to ie-v850e-mc-a cssocket161a1413n01n pin 1 position 627 user's manual u14359ej5v1ud appendix b cautions b.1 restriction on page rom access b.1.1 description in systems connecting multiple page roms to multiple di fferent csn spaces, when the page rom of a different csn space is continuously accessed immediately after a pag e rom is accessed, if the value of the former address and that of the latter address are on the sa me page of the page rom, even if the two csn spaces are different, it is taken as access of the same page of the page rom, and the on-page cycle is issued for the latter access (n = 0 to 7). as a result, the data access time of t he latter access is insuffici ent, making it impossible to perform normal reading. caution the page rom has a page access function and includes memory, such as mask rom and flash memory, that allows high-speed continuous access on the page (refer to figure b-1). for example, if the 8xxxxx2h address of the cs4 space is accessed immediately after the 0xxxxx0h address of the cs0 space is accessed, the on-page cycl e is executed for 8xxxxx2h. (refer to figure b-1 .) figure b-1. example of structure of memory map with error page rom (b) page rom (a) area 3 area 2 area 1 area 0 fffffffh 81fffffh 8000000h 01fffffh 0000000h 0000000h c000000h bffffffh 8000000h 7ffffffh 4000000h 3ffffffh cs4 01fffffh 0000000h 01fffffh 0000000h cs0 addresses of a0 to a25 examples of conditions under which an error does not occur are shown below. ? rom with page mode is not used. ? only one rom with page mode is used. ? the addresses of a0 to a25 do not overl ap in all the roms with page mode used. appendix b cautions 628 user's manual u14359ej5v1ud b.1.2 countermeasures when using several page roms, arrange the page roms so that the addresses of a0 to a25 do not overlap. for example, when arranging two 2 mb page roms in different csn spaces, set one page rom to 0000000h to 01fffffh, and the other page rom to f800000h to f9fffffh (refer to figure b-2 ). figure b-2. example of structur e of memory map preventing error page rom (b) page rom (a) area 3 area 2 area 1 area 0 fffffffh f9fffffh f800000h 39fffffh 3800000h 0000000h c000000h bffffffh 8000000h 7ffffffh 4000000h 3ffffffh 01fffffh 0000000h 01fffffh 0000000h cs0 addresses of a0 to a25 cs7 appendix b cautions 629 user's manual u14359ej5v1ud b.2 restriction on conflict between sl d instruction and interrupt request b.2.1 description if a conflict occurs between the decode operation of an in struction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1> ma y not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 user?s manual u14359ej5v1ud 630 appendix c register index (1/8) register symbol register name unit page adcr0 a/d conversion result register 0 (10 bits) adc 416 adcr0h a/d conversion result register 0h (8 bits) adc 416 adcr1 a/d conversion result register 1 (10 bits) adc 416 adcr1h a/d conversion result register 1h (8 bits) adc 416 adcr2 a/d conversion result register 2 (10 bits) adc 416 adcr2h a/d conversion result register 2h (8 bits) adc 416 adcr3 a/d conversion result register 3 (10 bits) adc 416 adcr3h a/d conversion result register 3h (8 bits) adc 416 adcr4 a/d conversion result register 4 (10 bits) adc 416 adcr4h a/d conversion result register 4h (8 bits) adc 416 adcr5 a/d conversion result register 5 (10 bits) adc 416 adcr5h a/d conversion result register 5h (8 bits) adc 416 adcr6 a/d conversion result register 6 (10 bits) adc 416 adcr6h a/d conversion result register 6h (8 bits) adc 416 adcr7 a/d conversion result register 7 (10 bits) adc 416 adcr7h a/d conversion result register 7h (8 bits) adc 416 adic interrupt control register intc 281 adm0 a/d converter mode register 0 adc 411 adm1 a/d converter mode register 1 adc 413 adm2 a/d converter mode register 2 adc 415 asc address setup wait control register bcu 113 asif0 asynchronous serial interface tr ansmission status register 0 uart0 370 asif1 asynchronous serial interface tr ansmission status register 1 uart1 370 asif2 asynchronous serial interface tr ansmission status register 2 uart2 370 asim0 asynchronous serial interface mode register 0 uart0 365 asim1 asynchronous serial interface mode register 1 uart1 365 asim2 asynchronous serial interface mode register 2 uart2 365 asis0 asynchronous serial interface status register 0 uart0 369 asis1 asynchronous serial interface status register 1 uart1 369 asis2 asynchronous serial interface status register 2 uart2 369 bcc bus cycle control register bcu 118 bcp bus cycle period control register bcu 114 bct0 bus cycle type configuration register 0 bcu 94 bct1 bus cycle type configuration register 1 bcu 94 bec endian configuration register bcu 97 appendix c register index user?s manual u14359ej5v1ud 631 (2/8) register symbol register name unit page brgc0 baud rate generator control register 0 brg0 388 brgc1 baud rate generator control register 1 brg1 388 brgc2 baud rate generator control register 2 brg2 388 bsc bus size configuration register bcu 96 ccc00 capture/compare register c00 rpu 330 ccc01 capture/compare register c01 rpu 330 ccc10 capture/compare register c10 rpu 330 ccc11 capture/compare register c11 rpu 330 ccc20 capture/compare register c20 rpu 330 ccc21 capture/compare register c21 rpu 330 ccc30 capture/compare register c30 rpu 330 ccc31 capture/compare register c31 rpu 330 ckc clock control register cg 306 cksr0 clock select register 0 uart0 387 cksr1 clock select register 1 uart1 387 cksr2 clock select register 2 uart2 387 cmd0 compare register d0 rpu 354 cmd1 compare register d1 rpu 354 cmd2 compare register d2 rpu 354 cmd3 compare register d3 rpu 354 cmicd0 interrupt control register intc 281 cmicd1 interrupt control register intc 281 cmicd2 interrupt control register intc 281 cmicd3 interrupt control register intc 281 csc0 chip area select control register 0 bcu 90 csc1 chip area select control register 1 bcu 90 csic0 clocked serial interface cl ock selection register 0 csi0 398 csic1 clocked serial interface cl ock selection register 1 csi1 398 csic2 clocked serial interface cl ock selection register 2 csi2 398 csiic0 interrupt control register intc 280 csiic1 interrupt control register intc 281 csiic2 interrupt control register intc 281 csim0 clocked serial interf ace mode register 0 csi0 396 csim1 clocked serial interf ace mode register 1 csi1 396 csim2 clocked serial interf ace mode register 2 csi2 396 dadc0 dma addressing control register 0 dmac 204 dadc1 dma addressing control register 1 dmac 204 dadc2 dma addressing control register 2 dmac 204 dadc3 dma addressing control register 3 dmac 204 appendix c register index user?s manual u14359ej5v1ud 632 (3/8) register symbol register name unit page dbc0 dma byte count register 0 dmac 206 dbc1 dma byte count register 1 dmac 206 dbc2 dma byte count register 2 dmac 206 dbc3 dma byte count register 3 dmac 206 dchc0 dma channel control register 0 dmac 209 dchc1 dma channel control register 1 dmac 209 dchc2 dma channel control register 2 dmac 209 dchc3 dma channel control register 3 dmac 209 dda0h dma destination address register 0h dmac 204 dda0l dma destination address register 0l dmac 205 dda1h dma destination address register 1h dmac 204 dda1l dma destination address register 1l dmac 205 dda2h dma destination address register 2h dmac 204 dda2l dma destination address register 2l dmac 205 dda3h dma destination address register 3h dmac 204 dda3l dma destination address register 3l dmac 205 ddis dma disable status register dmac 211 dmaic0 interrupt control register intc 281 dmaic1 interrupt control register intc 281 dmaic2 interrupt control register intc 281 dmaic3 interrupt control register intc 281 drst dma restart register dmac 211 dsa0h dma source address register 0h dmac 202 dsa0l dma source address register 0l dmac 203 dsa1h dma source address register 1h dmac 202 dsa1l dma source address register 1l dmac 203 dsa2h dma source address register 2h dmac 202 dsa2l dma source address register 2l dmac 203 dsa3h dma source address register 3h dmac 202 dsa3l dma source address register 3l dmac 203 dtfr0 dma trigger factor register 0 dmac 213 dtfr1 dma trigger factor register 1 dmac 213 dtfr2 dma trigger factor register 2 dmac 213 dtfr3 dma trigger factor register 3 dmac 213 dtoc dma terminal count output control register dmac 212 dwc0 data wait control register 0 bcu 111 dwc1 data wait control register 1 bcu 111 flpmc flash programming mode control register cpu 549 appendix c register index user?s manual u14359ej5v1ud 633 (4/8) register symbol register name unit page imr0 interrupt mask register 0 intc 284 imr1 interrupt mask register 1 intc 284 imr2 interrupt mask register 2 intc 284 imr3 interrupt mask register 3 intc 284 intm0 external interrupt mode register 0 intc 287 intm1 external interrupt mode register 1 intc 287 intm2 external interrupt mode register 2 intc 287 intm3 external interrupt mode register 3 intc 287 intm4 external interrupt mode register 4 intc 287 ispr in-service priority register intc 285 lockr lock register cpu 309 ovic00 interrupt control register intc 281 ovic01 interrupt control register intc 281 ovic02 interrupt control register intc 281 ovic03 interrupt control register intc 281 p0 port 0 port 474 p00ic0 interrupt control register intc 281 p00ic1 interrupt control register intc 281 p01ic0 interrupt control register intc 281 p01ic1 interrupt control register intc 281 p02ic0 interrupt control register intc 281 p02ic1 interrupt control register intc 281 p03ic0 interrupt control register intc 281 p03ic1 interrupt control register intc 281 p1 port 1 port 477 p10ic0 interrupt control register intc 281 p10ic1 interrupt control register intc 281 p10ic2 interrupt control register intc 281 p10ic3 interrupt control register intc 281 p11ic0 interrupt control register intc 281 p11ic1 interrupt control register intc 281 p11ic2 interrupt control register intc 281 p11ic3 interrupt control register intc 281 p12ic0 interrupt control register intc 281 p12ic1 interrupt control register intc 281 p12ic2 interrupt control register intc 281 p12ic3 interrupt control register intc 281 p13ic0 interrupt control register intc 281 p13ic1 interrupt control register intc 281 p13ic2 interrupt control register intc 281 appendix c register index user?s manual u14359ej5v1ud 634 (5/8) register symbol register name unit page p13ic3 interrupt control register intc 281 p2 port 2 port 479 p3 port 3 port 483 p4 port 4 port 486 p5 port 5 port 489 p7 port 7 port 491 pah port ah port 492 pal port al port 492 pbd port bd port 510 pcd port cd port 507 pcm port cm port 504 pcs port cs port 498 pct port ct port 502 pdl port dl port 496 pfc0 port 0 function control register port 472 pfc2 port 2 function control register port 482 pfc3 port 3 function control register port 485 pfc4 port 4 function control register port 488 pfccd port cd function control register port 508 pfccm port cm function control register port 506 pfccs port cs function control register port 501 phcmd peripheral command register cpu 305 phs peripheral status register cpu 308 pm0 port 0 mode register port 474 pm1 port 1 mode register port 477 pm2 port 2 mode register port 480 pm3 port 3 mode register port 483 pm4 port 4 mode register port 486 pm5 port 5 mode register port 489 pmah port ah mode register port 495 pmal port al mode register port 492 pmbd port bd mode register port 510 pmc0 port 0 mode control register port 475 pmc1 port 1 mode control register port 478 pmc2 port 2 mode control register port 481 pmc3 port 3 mode control register port 484 pmc4 port 4 mode control register port 487 pmc5 port 5 mode control register port 490 appendix c register index user?s manual u14359ej5v1ud 635 (6/8) register symbol register name unit page pmcah port ah mode control register port 495 pmcal port al mode control register port 493 pmcbd port bd mode control register port 493 pmccd port cd mode control register port 511 pmccm port cm mode control register port 505 pmccs port cs mode control register port 500 pmcct port ct mode control register port 503 pmcd port cd mode register port 507 pmcdl port dl mode control register port 497 pmcm port cm mode register port 504 pmcs port cs mode register port 499 pmct port ct mode register port 502 pmdl port dl mode register port 496 prc page rom configuration register memc 145 prcmd command register cpu 312 psc power-save control register cpu 313 psmr power-save mode register cpu 312 pwmb0 pwm buffer register 0 pwm 452 pwmb1 pwm buffer register 1 pwm 452 pwmc0 pwm control register 0 pwm 450 pwmc1 pwm control register 1 pwm 450 refresh control register 1 memc 161 rfs1 sdram refresh control register 1 memc 190 refresh control register 3 memc 161 rfs3 sdram refresh control register 3 memc 190 refresh control register 4 memc 161 rfs4 sdram refresh control register 4 memc 190 refresh control register 6 memc 161 rfs6 sdram refresh control register 6 memc 190 rwc refresh wait control register memc 163 rxb0 receive buffer register 0 uart0 371 rxb1 receive buffer register 1 uart1 371 rxb2 receive buffer register 2 uart2 371 dram configuration register 1 memc 153 scr1 sdram configuration register 1 memc 174 dram configuration register 3 memc 153 scr3 sdram configuration register 3 memc 174 appendix c register index user?s manual u14359ej5v1ud 636 (7/8) register symbol register name unit page dram configuration register 4 memc 153 scr4 sdram configuration register 4 memc 174 dram configuration register 6 memc 153 scr6 sdram configuration register 6 memc 174 seic0 interrupt control register intc 281 seic1 interrupt control register intc 281 seic2 interrupt control register intc 281 sesc0 valid edge select register c0 intc 289, 336 sesc1 valid edge select register c1 intc 289, 336 sesc2 valid edge select register c2 intc 289, 336 sesc3 valid edge select register c3 intc 289, 336 sio0 serial i/o shift register 0 csi0 400 sio1 serial i/o shift register 1 csi1 400 sio2 serial i/o shift register 2 csi2 400 sioe0 receive-only serial i/o shift register 0 csi0 401 sioe1 receive-only serial i/o shift register 1 csi1 401 sioe2 receive-only serial i/o shift register 2 csi2 401 sotb0 clocked serial interface tr ansmit buffer register 0 csi0 402 sotb1 clocked serial interface tr ansmit buffer register 1 csi1 402 sotb2 clocked serial interface tr ansmit buffer register 2 csi2 402 sric0 interrupt control register intc 281 sric1 interrupt control register intc 281 sric2 interrupt control register intc 281 stic0 interrupt control register intc 281 stic1 interrupt control register intc 281 stic2 interrupt control register intc 281 tmc0 timer c0 rpu 328 tmc1 timer c1 rpu 328 tmc2 timer c2 rpu 328 tmc3 timer c3 rpu 328 tmcc00 timer mode control register c00 rpu 332 tmcc01 timer mode control register c01 rpu 334 tmcc10 timer mode control register c10 rpu 332 tmcc11 timer mode control register c11 rpu 334 tmcc20 timer mode control register c20 rpu 332 tmcc21 timer mode control register c21 rpu 334 tmcc30 timer mode control register c30 rpu 332 tmcc31 timer mode control register c31 rpu 334 appendix c register index user?s manual u14359ej5v1ud 637 (8/8) register symbol register name unit page tmcd0 timer mode control register d0 rpu 356 tmcd1 timer mode control register d1 rpu 356 tmcd2 timer mode control register d2 rpu 356 tmcd3 timer mode control register d3 rpu 356 tmd0 timer d0 rpu 356 tmd1 timer d1 rpu 356 tmd2 timer d2 rpu 356 tmd3 timer d3 rpu 356 txb0 transmit buffer register 0 uart0 372 txb1 transmit buffer register 1 uart1 372 txb2 transmit buffer register 2 uart2 372 vswc system wait control register bcu 86 user?s manual u14359ej5v1ud 638 appendix d instruction set list d.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose register : used as source register. reg2 general-purpose register: used main ly as destination register. also used as source register in some instructions. reg3 general-purpose register: used mainly to store the re mainders of division result s and the higher 3 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the conditions code sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list s 1-bit data that specifies a system register in the register list appendix d instruction set list user?s manual u14359ej5v1ud 639 (3) register symbols used in operation register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword halfword (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in an execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency). appendix d instruction set list user?s manual u14359ej5v1ud 640 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition formula explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z/e 0 0 1 0 z = 1 zero equal nz/ne 1 0 1 0 z = 0 not zero not equal nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) n 0 1 0 0 s = 1 negative p 1 1 0 0 s = 0 positive t 0 1 0 1 ? always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed appendix d instruction set list user?s manual u14359ej5v1ud 641 d.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1, reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5, reg2 rrrrr010010iiiii gr[reg2] gr[reg2]+sign-extend (imm5) 1 1 1 addi imm16, reg1, reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend (imm16) 1 1 1 and reg1, reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16, reg1, reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend (imm16) 1 1 1 0 0 when conditions are satisfied 3 note 2 3 note 2 3 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend (disp9) when conditions are not satisfied 1 1 1 bsh reg2, reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23:16) ll gr[reg2] (31:24) ll gr[reg2] (7:0) ll gr[reg2] (15:8) 1 1 1 0 bsw reg2, reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7:0) ll gr[reg2] (15:8) ll gr[reg2] (23:16) ll gr[reg2] (31:24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2 (return pc) ctpsw psw adr ctbp+zero-extend (imm6 logically shift left by 1) pc ctbp+zero-extend (load-memory (adr, halfword)) 5 5 5 bit#3, disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 0) 3 note 3 3 note 3 3 note 3 clr1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, 0) 3 note 3 3 note 3 3 note 3 cccc, imm5, reg2, reg3 rrrrr111111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended (imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc, reg1, reg2, reg3 rrrrr111111rrrr wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1, reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5, reg2 rrrrr010011iiiii result gr[reg2]?sign-extend (imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 4 4 4 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 4 4 4 r r r r r appendix d instruction set list user?s manual u14359ej5v1ud 642 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (returned pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 4 4 4 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5, list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend (imm5 logically shift left by 2) gr[reg in list12] load-memory (sp, word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5, list12, [reg1] 0000011001iiiiil lllllllllllrrrrr note 5 sp sp+zero-extend (imm5 logically shift left by 2) gr[reg in list12] load-memory (sp, word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1, reg2, reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1, reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1, reg2, reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1, reg2, reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1, reg2, reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2, reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2] (15:0) ll gr[reg2] (31:16) 1 1 1 0 jarl disp22, reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend (disp22) 3 3 3 jmp [reg1] 00000000011rrrrr pc gr[reg1] 4 4 4 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend (disp22) 3 3 3 ld.b disp16[reg1], reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend (disp16) gr[reg2] sign-extend (load-memory (adr, byte)) 1 1 note 11 ld.bu disp16[reg1], reg2 rrrrr11110brrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend (disp16) gr[reg2] zero-extend (load-memory (adr, byte)) 1 1 note 11 appendix d instruction set list user?s manual u14359ej5v1ud 643 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1], reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend (disp16) gr[reg2] sign-extend (load-memory (adr, halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2, regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1], reg2 rrrrr111111rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend (disp16) gr[reg2] zero-extend (load-memory (adr, halfword) 1 1 note 11 ld.w disp16[reg1], reg2 rrrrr111001rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend (disp16) gr[reg2] load-memory (adr, word) 1 1 note 11 reg1, reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5, reg2 rrrrr010000iiiii gr[reg2] sign-extend (imm5) 1 1 1 mov imm32, reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16, reg1, reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend (imm16) 1 1 1 movhi imm16, reg1, reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1, reg2, reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2] gr[reg1] 1 2 note 14 2 mul note 22 imm9, reg2, reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2] sign-extend (imm9) 1 2 note 14 2 reg1, reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 gr[reg1] note 6 1 1 2 mulh imm5, reg2 rrrrr010111iiiii gr[reg2] gr[reg2] note 6 sign-extend (imm5) 1 1 2 mulhi imm16, reg1, reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 imm16 1 1 2 reg1, reg2, reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2] gr[reg1] 1 2 note 1 4 2 mulu note 22 imm9, reg2, reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2] zero-extend (imm9) 1 2 note 1 4 2 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1, reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not (gr[reg1]) 1 1 1 0 bit#3, disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, z flag) 3 note 3 3 note 3 3 note 3 not1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, z flag) 3 note 3 3 note 3 3 note 3 appendix d instruction set list user?s manual u14359ej5v1ud 644 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1, reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16, reg1, reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend (imm16) 1 1 1 0 list12, imm5 0000011110iiiiil lllllllllll00001 store-memory (sp?4, gr[reg in list12], word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend (imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12, imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory (sp?4, gr[reg in list12], word) gr[reg in list12] load memory (sp, word) sp sp?4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 4 4 4 r r r r r reg1, reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2] arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5, reg2 rrrrr010101iiiii gr[reg2] gr[reg2] arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc, reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2] logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2] logically shift left by 1) or 00000000h 1 1 1 reg1, reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated (gr[reg2]+gr[reg1]) 1 1 1 satadd imm5, reg2 rrrrr010001iiiii gr[reg2] saturated (gr[reg2]+sign-extend (imm5) 1 1 1 satsub reg1, reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated (gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16, reg1, reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated (gr[reg1]?sign-extend (imm16) 1 1 1 satsubr reg1, reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated (gr[reg1]?gr[reg2]) 1 1 1 setf cccc, reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1 appendix d instruction set list user?s manual u14359ej5v1ud 645 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3, disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 1) 3 note 3 3 note 3 3 note 3 set1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, 1) 3 note 3 3 note 3 3 note 3 reg1, reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5, reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend (imm5) 1 1 1 0 reg1, reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5, reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend (imm5) 1 1 1 0 sld.b disp7[ep], reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend (disp7) gr[reg2] sign-extend (load-memory (adr, byte)) 1 1 note 9 sld.bu disp4[ep], reg2 rrrrr0000110dddd note 18 adr ep+zero-extend (disp4) gr[reg2] zero-extend (load-memory (adr, byte)) 1 1 note 9 sld.h disp8[ep], reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend (disp8) gr[reg2] sign-extend (load-memory (adr, halfword)) 1 1 note 9 sld.hu disp5[ep], reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend (disp5) gr[reg2] zero-extend (load-memory (adr, halfword)) 1 1 note 9 sld.w disp8[ep], reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend (disp8) gr[reg2] load-memory (adr, word) 1 1 note 9 sst.b reg2, disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend (disp7) store-memory (adr, gr[reg2], byte) 1 1 1 sst.h reg2, disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend (disp8) store-memory (adr, gr[reg2], halfword) 1 1 1 sst.w reg2, disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend (disp8) store-memory (adr, gr[reg2], word) 1 1 1 st.b reg2, disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend (disp16) store-memory (adr, gr[reg2], byte) 1 1 1 st.h reg2, disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend (disp16) store-memory (adr, gr[reg2], halfword) 1 1 1 st.w reg2, disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend (disp16) store-memory (adr, gr[reg2], word) 1 1 1 stsr regid, reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1 appendix d instruction set list user?s manual u14359ej5v1ud 646 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1, reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1, reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2)+(gr[reg1] logically shift left by 1) pc (pc+2)+(sign-extend (load-memory (adr, halfword))) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7:0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15:0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc + 4 (return pc) eipsw psw ecr.eicc exception code (40h to 4fh, 50h to 5fh) psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh (exception code: 40h to 4fh)) 00000050h (when vector is 10h to 1fh (exception code: 50h to 5fh)) 4 4 4 tst reg1, reg2 r r rr r0 01 01 1 r rrr r result gr[reg2] and gr[reg1] 1 1 1 0 bit#3, disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) 3 note 3 3 note 3 3 note 3 xor reg1, reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16, reg1, reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7:0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15:0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 4 if there is an instructi on that rewrites the content s of psw immediately before 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the total num ber of list12 registers. same op eration as when n = 1 if n = 0) 5. rrrrr: other than 00000. 6. the lower halfword data only is valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states). appendix d instruction set list user?s manual u14359ej5v1ud 647 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. t herefore, the meaning of register specificat ion in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. in the case of reg2 = reg3 (the lower 32 bits of the results are not written in the register) or reg3 = r0 (the higher 32 bits of the results are not wri tten in the register), shortened by 1 clock. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8. 22. do not make a register combination that satisfie s all the following conditions when executing the ?mul reg1, reg2, reg3? and ?mulu reg1, reg2, reg3? inst ructions. if an instruction that satisfies these conditions is executed, the operation is not guaranteed. ? reg1 = reg3 ? reg1 reg2 ? reg1 r0 ? reg3 r0 user?s manual u14359ej5v1ud 648 appendix e revision history e.1 major revisions in this edition (1/3) page description p. 37 modification of description in 2.2 pin status pp. 44, 45 addition of caution to 2.3 (9) (b) (i) wait (wait) and (v) hldrq (hold request) p. 50 modification of description in 2.3 (13) (b) (i) a16 to a25 (address) p. 50 modification of description in 2.3 (14) (b) (i) a0 to a15 (address) p. 51 modification of description in 2.3 (15) (b) (i) d0 to d15 (data) p. 54 change of i/o circuit type of cksel in 2.4 pin i/o circuits and recommended connection of unused pins p. 55 addition of remark to 2.5 pin i/o circuits p. 88 modification of description in 4.2.1 pin status during internal rom, internal ram, and on-chip peripheral i/o access p. 94 addition of description to 4.4 (1) bus cycle type configuration registers 0, 1 (bct0, bct1) p. 119 addition of description to 4.8.1 function outline p. 131 deletion of description from 4.10.1 program space p. 171 addition of description to 5.4.3 (1) output of each address and connection of sdram p. 173 addition of description to 5.4.3 (2) bank address output p. 174 addition of caution to 5.4.4 sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) p. 190 addition of caution to 5.4.6 (1) sdram refresh control registers 1, 3, 4, 6 (rfs1, rfs3, rfs4, rfs6) p. 202 modification of description in 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) p. 202 addition of description and caution to 6.3.1 (1) dma source address registers 0h to 3h (dsa0h to dsa3h) p. 204 modification of description in 6.3.2 dma destination address registers 0 to 3 (dda0 to dda3) p. 204 addition of description and caution to 6.3.2 (1) dma destination address registers 0h to 3h (dda0h to dda3h) p. 206 addition of cautions and modification of description in 6.3.3 dma byte count registers 0 to 3 (dbc0 to dbc3) p. 207 addition of description and cautions to 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) pp. 209, 210 modification of description in 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) p. 211 modification of description in 6.3.6 dma disable status register (ddis) p. 211 modification of description in 6.3.7 dma restart register (drst) pp. 213, 215 addition of caution and modification of description in 6.3.9 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) p. 223 addition of caution to 6.6.1 2-cycle transfer p. 251 deletion of note from table 6-2 external bus cycles during dma transfer p. 252 modification of description in 6.9 next address setting function p. 254 addition of cautions to 6.10 dma transfer start factors p. 256 modification of description in 6.11 terminal count output upon dma transfer end p. 256 addition of figure 6-22 terminal count signal (tcn) timing example (2) p. 257 modification of description in 6.12 forcible suspension p. 258 modification of description of remark in figure 6-23 example of forcible termination of dma transfer appendix e revision history user?s manual u14359ej5v1ud 649 (2/3) page description p. 259 addition of 6.13.1 restriction related to dma transfer forcible termination p. 261 modification of description in 6.14 times related to dma transfer pp. 261, 262 addition of caution and modification of description in 6.15.1 example of response time to dma request p. 263 addition of 6.15.2 maximum response time for dma transfer request p. 264 addition of 6.16 (4) holding dmarqn signal p. 264 addition of description to 6.16 (5) dmaakn signal output p. 264 addition of 6.16 (7) program execution and dma transfer with internal ram p. 264 addition of 6.16 (8) restrictions related to automatic clearing of tcn bit of dchcn register p. 265 addition of 6.16 (9) read values of dsan and ddan registers p. 269 deletion of description from 7.2 non-maskable interrupts p. 281 addition of caution to 7.3.4 interrupt control register (xxicn) p. 285 addition of caution to 7.3.6 in-service priority register (ispr) p. 300 modification of description in figure 7-14 pipeline operation at interrupt request acknowledgement (outline) p. 301 addition of description to 7.8 periods in which interrupts are not acknowledged p. 319 addition of description to 9.5.4 (2) (a) release according to a non-maskable interrupt request or an unmasked maskable interrupt request p. 322 addition of description to 9.5.5 (2) (a) release according to a non-maskable interrupt request or an unmasked maskable interrupt request pp. 341, 342 addition of timing to figure 10-5 compare operation example p. 343 change of timing of figure 10-6 tmc1 compare operati on example (set/reset output mode) pp. 365, 366 addition of caution and notes to 11.2.3 (1) asynchronous serial interface mode registers 0 to 2 (asim0 to asim2) p. 377 addition of caution to 11.2.5 (3) continuous transmission operation pp. 411, 412 modification of description in 12.3 (1) a/d converter mode register 0 (adm0) p. 413 addition of cautions to 12.3 (2) a/d converter mode register 1 (adm1) p. 419 addition of description to 12.4.2 (1) (b) timer trigger mode p. 421 modification of description in figure 12-3 select mode operation timing: 1-buffer mode (ani1) p. 422 modification of description in figure 12-4 select mode operation timing: 4-buffer mode (ani6) p. 423 modification of description in figure 12-5 scan mode operation timing: 4-channel scan (ani0 to ani3) p. 442 addition of 12.8.5 reconversion operation in timer 1 trigger mode p. 443 addition of 12.8.6 supplementary information on a/d conversion time p. 457 addition of remark to 14.2 port configuration p. 491 modification of description of caution in 14.3.7 (1) operation in control mode p. 504 addition of note to 14.3.13 (1) operation in control mode p. 511 addition of 14.4 setting to use alternate function of port pin p. 520 addition of 14.5 operation of port function p. 521 addition of 14.6 cautions p. 522 addition of description to table 15-1 operation status of each pin during reset p. 561 addition of chapter 17 electrical specifications p. 620 addition of chapter 18 package drawings p. 622 addition of chapter 19 recommended soldering conditions appendix e revision history user?s manual u14359ej5v1ud 650 (3/3) page description p. 624 addition of appendix a notes on target system design p. 627 addition of appendix b cautions pp. 643, 646, 647 addition of description and note to d.2 instruction set (in alphabetical order) p. 648 addition of appendix e revision history e.2 revision history up to preceding edition the following table shows the revision hi story up to the previous edition. the ?applied to:? column indicates the chapters of each edition in wh ich the revision was applied. (1/7) edition major revision from pr evious edition applied to: 2nd bit numbers of bits defined as reserved words in the device file are enclosed in brackets. change of bit unit for manipulati on for the following registers: vswc, ddis, drst, adm1, bcp, rwc, tmccn1, sescn, ckc, dtoc, intmn, csicn, sotbn, rxbn, asisn, txbn, cksrn, brgcn (n = 0 to 3, 1 to 4, or 0 to 2) change of names of ce, cae, and cs bits of each register throughout addition of description to 2.3 (9) (b) (vii) selfref change from type 5-k to type 5-ac in 2.4 pin i/o circuits and recommended connection of unused pins change from type 5-k to type 5-ac in 2.5 pin i/o circuits chapter 2 pin functions modification of r2 in 3.2 cpu register set modification of description of r2 in 3.2.1 program register set deletion of caution 1 from 3.4.5 (3) internal peripheral i/o area deletion of description from 3.4.7 recommended use of address space modification of pal, pah, pdl, pmal, pmah, pmdl, pmcal, pmcah, and pmcdl registers in 3.4.8 peripheral i/o registers modification of imr0 to imr3 registers in 3.4.8 peripheral i/o registers change of symbol of drcn register to scrn register (n = 1, 3, 4, 6) in 3.4.8 peripheral i/o registers change of symbol of rfcn register to rfsn register (n = 1, 3, 4, 6) in 3.4.8 peripheral i/o registers change of symbol of unlock register to lockr in 3.4.8 peripheral i/o registers modification of address of dtoc register in 3.4.8 peripheral i/o registers addition of description to 3.4.9 specific registers change of set value in 3.4.10 system wait control register (vswc) addition of description to 3.4.11 cautions chapter 3 cpu function modification of description in 4.2.1 pin status during internal rom, internal ram, and peripheral i/o access addition of caution 3 to 4.6.1 (3) bus cycle period control register (bcp) chapter 4 bus control function appendix e revision history user?s manual u14359ej5v1ud 651 (2/7) edition major revision from pr evious edition applied to: 2nd change of symbol of drcn register to scrn register (n = 1, 3, 4, 6) in 5.3.4 dram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) change of symbol of rfcn register to rfsn register (n = 1, 3, 4, 6) in 5.3.6 (1) refresh control registers 1, 3, 4, 6 (rfs1, rfs3, rfs4, rfs6) addition of caution 2 to 5.3.7 self-refresh control function addition of note 1 to figure 5-10 self refresh timing (dram) addition of caution 2 to 5.4.7 self-refresh control function addition of note 1 to figure 5-19 self refresh timing (sdram) chapter 5 memory access control function change of bit name in 6.3.8 dma terminal count output control register (dtoc) addition of dfn bit to 6.3.9 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) change and addition of description in 6.5.1 single transfer mode addition of note 1 to figure 6-8 timing of 2-cycle dma transfer (external i/o sram) addition timing of 2-cycke dma transfer to figures 6-9 through 6-12 addition of description to 6.6.2 flyby transfer change of remark 1 in 6.7.1 transfer type and transfer object change of description in 6.17 (3) bus arbitration for cpu chapter 6 dma functions (dma controller) modification of names of interrupt sources in table 7-1 interrupt/exception source list change and addition of description in 7.3.5 interrupt mask registers 0 to 3 (imr0 to imr3) modification of caution in 7.3.9 (2) valid edge selection registers c0 to c3 (sesc0 to sesc3) chapter 7 interrupt/excep tion processing function addition of description of ckdiv0 to ckdiv2 bits to 9.3.4 clock control register (ckc) change of symbol of unlock register to lockr register and addition of caution in 9.4 pll lockup addition of caution to 9.5.3 (1) setting and operation status addition of timing of clkout to 9.6.1 (1) securing the time using an on-chip time base counter chapter 9 clock generator function modification of generated interrupt signal names in table 10-1 timer c configuration chapter 10 timer/counter function (real- time pulse unit) addition of description to caution in 11.2.3 (1) asynchronous serial interface mode registers 0 to 2 (asim0 to asim2) addition of description to caution in 11.2.6 (2) (a) clock select registers 0 to 2 (cksr0 to cksr2) addition of high-speed transfer in slave mode to 11.3.1 features addition of description to caution and pin status with csin operation disabled to 11.3.3 (1) clocked serial interface mode registers 0 to 2 (csim0 to csim2) chapter 11 serial interface function addition of description to 12.3 (4) a/d conversion result registers (adcr0 to adcr7, adcr0h to adcr7h) modification of description in 12.6.1 (2) (a) 1-trigger mode chapter 12 a/d converter appendix e revision history user?s manual u14359ej5v1ud 652 (3/7) edition major revision from pr evious edition applied to: 2nd modification of block diagram of each type in figures 14-2, 14-4, 14-5 , and 14-7 through 14- 14 addition of description and note to 14.3.8 port al addition of description and note to 14.3.9 port ah addition of description and note to 14.3.10 port dl addition of note to 14.3.11 (2) (b) port cs mode control register (pmccs) addition of note to 14.3.12 (2) (b) port ct mode control register (pmcct) addition of caution and note to 14.3.13 (2) (b) port cm mode control register (pmccm) addition of description to 14.3.13 (2) (c) port cm function control register (pfccm) addition of note to 14.3.14 (2) (b) port cd mode control register (pmccd) chapter 14 port functions modification of figure 16-1 connection example of adapter (fa-144gj-uen) for v850e/ma1 flash memory programming addition of handshake-supporting csi as communication mode to 16.6.3 selection of communication mode change and addition of description in 16.7 flash memory programming by self writing chapter 16 flash memory ( pd70f3107) 3rd ? the following produc ts have been developed pd703016gj-xxx-uen, 703107gj-xxx-uen, and 70f3107gj-uen ? addition of product under development 161-pin plastic fbga package throughout change of pin names in pin identification modification of description in 1.6.2 (11) ports chapter 1 introduction change of pin names in 2.1 (2) non-port pins addition of description to 2.3 (12) (b) (ii) sdclk (sdram clock output) change of description in 2.4 pin i/o circuits and recommended connection of unused pins chapter 2 pin functions addition of note and modification of caution 1 in 3.4.5 (3) internal peripheral i/o area modification of note in figure 3-9 recommended memory map change of description in 3.4.10 system wait control register (vswc) chapter 3 cpu function addition of note to 4.3 memory block function modification of description in 4.5.1 number of access clocks modification of description in table 4-1 bus cycles in which wait function is valid modification of description in 4.9 bus priority order chapter 4 bus control function addition of note to figure 5-5 page rom access timing modification of figure 5-18 cbr refresh timing (sdram) modification of figure 5-19 self-refresh timing (sdram) chapter 5 memory access control function modification of remark 1 in table 6-1 relationship between transfer type and transfer object chapter 6 dma functions (dma controller) appendix e revision history user?s manual u14359ej5v1ud 653 (4/7) edition major revision from pr evious edition applied to: 3rd modification of figure 7-14 pipeline operation at interrupt request acknowledgement (outline) addition of description to 7.8 periods in which interrupts are not acknowledged chapter 7 interrupt/excep tion processing function modification of description in 9.3.1 direct mode modification of caution in 9.3.2 pll mode modification of caution 3 in 9.3.4 clock control register (ckc) modification of caution 4 in 9.5.2 (3) power-save control register (psc) modification of figure in 9.6.1 (1) securing the time using an on-chip time base counter modification of figure in 9.6.1 (2) securing the time according to the signal level width (reset pin input) chapter 9 clock generation function addition of caution to 10.1.5 (1) timer mode control registers c00 to c30 (tmcc00 to tmcc30) addition of description to 10.1.6 (4) compare operation modification and addition in figure 10-5 compare operation example modification of figure 10-8 interval timer operation timing example modification of figure 10-10 pwm output timing example modification of figure 10-12 cycle measurement operation timing example modification of figure 10-14 tmd0 compare operation example chapter 10 timer/counter function (real- time pulse unit) modification of caution in 11.2.3 (1) asynchronous serial interface mode registers 0 to 2 (asim0 to asim2) modification of description in 11.3.4 (1) transfer mode chapter 11 serial interface function addition of description to 12.3 (2) a/d converter mode register 1 (adm1) modification of caution in 12.3 (3) a/d converter mode register 2 (adm2) chapter 12 a/d converter modification of figure 14-10 block diagram of type k chapter 14 port functions modification of remark in figure 16-1 connection example of adapter (fa-144gj-uen) for v850e/ma1 flash memory programming modification of description in 16.5.6 port pins addition of description to 16.7.1 outline of self-programming modification of table 16-8 flash information modification of caution 1 in 16.7.12 flash programming mode control register (flpmc) chapter 16 flash memory ( pd70f3107) 4th ? deletion of the following products: pd703103, 703105, 703106, 703107, and 70f3107 ? addition of the following product names: pd703103a, 703105a, 703106a, 703106a(a), 703107a, 703107a(a), 70f3107a, and 70f3107a(a) throughout change of description in 1.4 ordering information change of pin configuration in 1.5 pin configuration (top view) 161-pin plastic fbga (13 13) addition of 1.7 differences among products chapter 1 introduction appendix e revision history user?s manual u14359ej5v1ud 654 (5/7) edition major revision from pr evious edition applied to: 4th modification of description in 2.3 (9) (b) (i) wait (wait) addition of caution to 2.3 (9) (b) (vii) selfref (self-refresh request) chapter 2 pin functions modification of caution in 3.4.3 (1) program space change of description and addition of caution in 3.4.5 (2) internal ram area deletion of description from 3.4.7 (1) program space change of bit units for manipulation for dma terminal count output control register in 3.4.8 peripheral i/o registers change of description in table and addition of remark to 3.4.10 system wait control register (vswc) chapter 3 cpu function change of description in 4.2.1 pin status during internal rom, internal ram, and peripheral i/o access addition of caution to 4.3.1 chip select control function addition of description to 4.4.1 (1) bus cycle type configuration registers 0, 1 (bct0, bct1) change of description in 4.5.1 number of access clocks addition of description to 4.5.2 (1) bus size configuration register (bsc) addition of caution to 4.5.3 (1) endian configuration register (bec) addition of caution to 4.6.1 (2) address setup wait control register (asc) change of description and addition of caution in 4.6.1 (3) bus cycle period control register (bcp) chapter 4 bus control function addition of description to 5.3.4 dram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) change of description to ltm2n to ltm0n bits = 00x in 5.4.4 sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) change of description in figure 5-16 sdram access timing chapter 5 memory access control function addition of caution to 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) change of description and addition of reserved word < > of device file to bits 3 to 0 in 6.3.8 dma terminal count output control register (dtoc) addition of caution to 6.3.9 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) addition of description and figure to 6.5.1 single transfer mode addition of description to 6.5.3 block transfer mode addition of caution to 6.8 dma channel priorities addition of description to 6.16 one-time transfer during single transfer via dmarq0 to dmarq3 signals addition of 6.17 (5) dma start factors chapter 6 dma functions (dma controller) appendix e revision history user?s manual u14359ej5v1ud 655 (6/7) edition major revision from pr evious edition applied to: 4th deletion of description from chapter 7 interrupt/exception processing function change of description in figure 7-2 acknowledging non-maskable interrupt request addition of caution to and deletion of reserved word < > of device file from 7.3.5 interrupt mask registers 0 to 3 (imr0 to imr3) addition of caution to 7.3.9 (1) external interrupt mode registers 1 to 4 (intm1 to intm4) addition of caution to 7.3.9 (2) valid edge select registers c0 to c3 (sesc0 to sesc3) change of description in figure 7-14 pipeline operation at interrupt request acknowledgement (outline) change of description in 7.8 periods in which interrupts are not acknowledged chapter 7 interrupt/excep tion processing function addition of description to 9.5.4 (2) (a) release according to a non-maskable interrupt request or an unmasked maskable interrupt request addition of description to 9.5.5 (2) (a) release according to a non-maskable interrupt request or an unmasked maskable interrupt request change of figure in 9.6.1 (1) securing the time using an on-chip time base counter change of figure in 9.6.1 (2) securing the time according to the signal level width (reset pin input) chapter 9 clock generation function addition of caution to 10.1.4 (2) (a) setting these registers as capture registers (cmsn0 and cmsn1 of tmccn1 = 0) addition of description and change of bit name to bit 5 in 10.1.5 (2) timer mode control registers c01 to c31 (tmcc01 to tmcc31) addition of note and deletion of caution from figure 10-12 cycle measurement operation timing example change of description in figure 10-13 example of timing during tmdn operation addition of caution to 10.2.5 (1) timer mode control registers d0 to d3 (tmcd0 to tmcd3) chapter 10 timer/counter function (real- time pulse unit) addition of description to caution in 11.2.3 (1) asynchronous serial interface mode registers 0 to 2 (asim0 to asim2) change of description to pen bit = 0, fen bit = 0, oven bit = 0 in 11.2.3 (2) asynchronous serial interface status registers 0 to 2 (asis0 to asis2) change of description to txbfn bit, txsfn bit in 11.2.3 (3) asynchronous serial interface transmission status registers 0 to 2 (asif0 to asif2) change of description in and addition of figure to 11.2.5 (3) continuous transmission operation change of description and addition of note in figure 11-5 continuous transmission starting procedure change of description in figure 11-6 continuous transmission ending procedure modification of figure 11-7 and addition of caution to figure 11-7 asynchronous serial interface reception completion interrupt timing addition of caution to 11.2.6 (2) (a) clock select registers 0 to 2 (cksr0 to cksr2) addition of (2) to 11.2.7 cautions addition of description to 11.3.3 (1) clocked serial interface mode registers 0 to 2 (csim0 to csim2) chapter 11 serial interface function appendix e revision history user?s manual u14359ej5v1ud 656 (7/7) edition major revision from pr evious edition applied to: 4th addition of description to 12.2 (5) successive approximation register (sar) change of bit names in 12.3 (4) a/d conversion result registers (adcr0 to adcr7, adcr0h to adcr7h) addition of 12.9 how to read a/d converter's characteristic table chapter 12 a/d converter change of bit names in 13.3 (2) pwm buffer registers 0, 1 (pwmb0, pwmb1) chapter 13 pwm unit change of block type to ports 3 and 4 in 14.2 (1) function of each port change of figure 14-4 block diagram of type d change of figure 14-5 block diagram of type e addition of figure 14-7 block diagram of type g change of figure 14-8 block diagram of type h change of figure 14-9 block diagram of type i change of figure 14-12 block diagram of type l change of figure 14-13 block diagram of type m change of figure 14-14 block diagram of type n partial deletion of description from pmc0n bit = 0 in 14.3.1 (2) (b) port 0 mode control register (pmc0) partial deletion of description from pmc2n bit = 0 in 14.3.3 (2) (b) port 2 mode control register (pmc2) change of block type to p30 and p33 in 14.3.4 (1) operation in control mode change of block type to p40 and p43 in 14.3.5 (1) operation in control mode addition of caution to 14.3.7 (1) operation in control mode addition of caution to 14.3.10 (2) (b) port dl mode control register (pmcdl) chapter 14 port functions addition of caution to 16.2 writing with flash programmer addition of table 16-1 wiring of adapter for v850e/ma1 flash memory programming (fa-144gj-uen) addition of figure 16-2 wiring example of adapte r (fa-161f1-en4) for v850e/ma1 flash memory programming addition of table 16-2 wiring of adapter for v850e/ma1 flash memory programming (fa-161f1-en4) change of execution status of program in table 16-5 software environmental conditions chapter 16 flash memory ( pd70f3107) change of description in b.2 instruction set (in alphabetical order) appendix b instruction set list |
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